31st July 2008 AIDA FEE Report 1

AIDA Front end electronics

Report July 2008•Progress•Virtex5 FPGA choice•Milestones for prototype delivery

31st July 2008 AIDA FEE Report 2

Progress• Completed the FEE specification.

• Currently out for comments (1st July)

• Schematic capture started.• FPGA part design.

• Processor peripheral component choices • ML507 purchased and delivered

• Development kit with new FPGA.

31st July 2008 AIDA FEE Report 3

Virtex5 FPGA choice

• Will Linux work and be useable in an FPGA without a processor ?

• Software development environment, Gbit rates, who else is doing it ?

• Can data channels share FPGA resources ?

• RAM and DSP blocks.

31st July 2008 AIDA FEE Report 4

Experiences with ML507Xilinx development kit ML507 : Virtex5-FXT70 containing a

PowerPC 440 with 256Mbyte RAM, Gbit ethernet and other peripherals

– DENX ELDK 4.1 : Public domain Embedded Linux Development Kit => cross compilers and tool kit for PPC 440

– Xilinx supply Linux kernel 2.6.25 with drivers for Virtex5 specific hardware (for example LLTemac - Gbit ethernet)

– Using the ELDK can configure and build the Linux kernel for the ML507 on a Linux workstation.

– Root file system via NFS on a standard server.– This was working within a couple of days of receiving the

ML507– Clear advantage of using PPC processor and Linux

31st July 2008 AIDA FEE Report 5

Experiences with ML507• Testing network performance.

– Use standard test program from the MIDAS data acquisition suite which uses the data acquisition transfer library to send simulated data.

– Receiver is a Dell workstation running Linux with the MIDAS tape server receiver stage discarding received data. Block size 64 Kbytes.

– Data transfer rate 440 blocks/sec or 28Mbyte/sec

• This took just as long as needed to compile the test program with the PC440 cross compiler.

• All MIDAS software etc will run within the PPC Linux processor

31st July 2008 AIDA FEE Report 6

FPGA outline block diagram

4One of

64One of

Microblaze runningLINUX

Max rate = ( 60K 8x )

+( 10k 2024 )x

=>20720000, ,bytes/sec

Include edge events=>

61200000, ,bytes/sec

SharedRAM

60Max rate K events/sec

SharedRAM

SharedRAM

SharedRAM

60Max rate K events/sec

666 0 K events/sec

60Max rate K events/secState

machine

Q

ADC

ASIC16

channels

Timestamp

16 Discriminators

Sync/Pse/Res

ToDigital

Max rate 30K - 16events/sec bit data

Statemachine

Q 1024 x

(48 + 64 + 3)

Energy MWD

Leading Edgediscriminator

Slow in Fast out Waveform RAM "Circulating Buffer"

Timestamp

Sync/Pse/Res

1024 long (20uS ) Floating pointtime vernier

calc.

Q 10 36x

Energy

DMAMemorymanager

64DDR

SDRAM 32 bit

FIFO 3072 16x

31st July 2008 AIDA FEE Report 7

FPGA resources

• Digital channel ( x 64 ) : 4,217kbits• Memory - 65kbits per channel

– Circulating buffer ( slow in fast out ): 1024x16– Waveform store : 3072x16– Energy queue : 10 x 36

• DSP - two– MWD : one for multiply and add– Discriminator : one for multiply and add

• Analog channels (one per ASIC) :65kbits• Buffer memory : 1024 x 16

31st July 2008 AIDA FEE Report 8

FPGA choice• Require

– Memory : 4,282 kbits– DSP : 128

• SX95T– Memory : 8,576 kbits– DSP : 640– No processor

• FX70T– Memory : 5,328 kbits– DSP : 128– PowerPC 440 processor with large LINUX user community

• Both types are Virtex5 with the same pcb footprint. Further FPGAs with greater resources are planned.

31st July 2008 AIDA FEE Report 9

Milestones for Prototype FEE delivery (Changes included in blue)

• Complete Specification :– 1st July 2008 => Achieved

• Complete Schematic and PCB layout : – 15th Sept 2008. => Delayed

• Deliver 6 FEE cards ( 6 weeks ) : – 27th Oct 2008 => medium risk

• Complete Prototype VHDL : – 1st December 2008 => Medium

risk• Commission FEE cards :

– 1st February 2009 => High risk

• Design ASIC Mezzanine– 29th Sept 2008. => Delayed

• Deliver 6 ASIC Mezzanines– 17th Nov 2008 => medium

risk• Assemble ASICs onto

Mezzanines– During Dec 2008 at

Liverpool• Complete Kapton board :

– 1st February 2009 => low risk