3d-ic economics and design enablement · rc/et dft and atpg for 3dic voltus/tempus/qrc digital...

22
Brandon Wang June 4, 2014 3D-IC Economics and Design Enablement

Upload: others

Post on 21-Apr-2020

4 views

Category:

Documents


2 download

TRANSCRIPT

Page 1: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

Brandon WangJune 4, 2014

3D-IC Economics and Design Enablement

Page 2: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

2 © 2014 Cadence Design Systems, Inc.

• Semiconductor Challenges – More Moore or beyond Moore?

• 3D/2.5D Advantages and Challenges• Design enablement for 2.5D/3D realization• Conclusion

Outline

Page 3: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

3 © 2014 Cadence Design Systems, Inc.

• System Requirements : Bandwidth, Power, functionality, COMPLEXITY• Obvious Solution : Jump to next process node:20nm/14nm/10nm , BUT

– NOT really shrinking!! (Analog Circuit? Variability, Leakage? And Utilization%?)– Expense of IP re-built and validation! Verification cost? Risk? T2M?– And what about COST ? – What about CIS, MEMS, Silicon Photonics, RF, Non-volatile, PMIC NOT always in

a single die!

It’s not always about process scaling

“We know how to get to smaller size nodes, but we see economic indicators slowing and we are worried about it — we can see the end from here. If we can’t make cheaper transistors, we’ll look to other things like 3D.”

Paul Jacobs, CEO, Qualcomm 8/22/13

Page 4: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

4 © 2014 Cadence Design Systems, Inc.

3D-IC Benefits and Challenges

Page 5: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

5 © 2014 Cadence Design Systems, Inc.

Various 3D Die Stacking

•1 logic die and 2 memory dies• All Dies are face down

•Die 1 and Die 2 face each other• Connected through uBump• TSV for C4Bump

Die3, TC2 –Logic Die. Die 1,2: Memory Dies;

Page 6: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

6 © 2014 Cadence Design Systems, Inc.

Why 3D?

Source: Samsung Electronics 2012Source: Chipworks

3D-IC Brings PPA-T benefit simultaneously

Page 7: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

7 © 2014 Cadence Design Systems, Inc.

Heterogeneous 2.5D, best of both worlds

• Virtex-7 H870T

• two eight-channel transceiver dice alongside three FPGA logic dice on a single device

• a total of sixteen 28-Gbps transceivers, seventy-two 13.1-Gbps transceivers and 876,160logic cells

• A high density device is made possible through 2.5D heterogeneous integration using TSMC CoWos (Silicon Interposer)

Source: Xilinx

Page 8: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

8 © 2014 Cadence Design Systems, Inc.

What Are The Markets For 3D-IC’s?

Source: Yole Développement, July 2012

Page 9: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

9 © 2014 Cadence Design Systems, Inc.

Short-, medium-, and long-term path to 3D-IC

Si Partitioning with TSV

Interposer

• Market : FPGA

• Xilinx in 2010

• 2011-2013

Memory Cube with TSVs

• MARKET : Server and computing

• IBM and Micron

• 2012-2014

Memory Cube with TSVs

• MARKET : Server and computing

• IBM and Micron

• 2012-2014

Logic + memory w/ 2.5D TSV Interposer

• MARKET : Server Network , gaming

console

• 2013-2014

Logic + memory w/ 2.5D TSV Interposer

• MARKET : Server Network , gaming

console

• 2013-2014

Wide IO + Logic with TSVs

•MARKET : Mobile, tablet, gaming

processors

• 2015-2016

Wide IO + Logic with TSVs

•MARKET : Mobile, tablet, gaming

processors

• 2015-2016

High-performance

computing

• MARKET : CPU, MCMs etc

•ST-E /LETI WIOMING in 2011

• ~ 2015

High-performance

computing

• MARKET : CPU, MCMs etc

•ST-E /LETI WIOMING in 2011

• ~ 2015

Standards, ecosystem, cost Standards, ecosystem, cost

Page 10: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

10 © 2014 Cadence Design Systems, Inc.

Other 2.5D/3D-IC Advantages

De-Risk SOC implementation and better T2M Re-use of silicon proven Analog/MS/PHY Only port the digital to advanced process nodes

Reduce power through Light I/O, with minimized distributed ESD

Much improved SI/PI compared to discrete/POP

Improve yield for larger die at advanced nodes

Reduce Form factor

Secure against supply chain attack while using hybrid foundries ( Trusted + Un-trusted )

Page 11: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

11 © 2014 Cadence Design Systems, Inc.

Thermal Challenges in Mobile Application

Source: ST-Ericson

Page 12: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

12 © 2014 Cadence Design Systems, Inc.

3D DFT Challenges

• Pre-bond test– Focus on die-internal circuitry– Original thick or thinned-down wafer– Probe access at DUT– Probe on micro-bumps or dedicated pads

die

• Mid-bond / post-bond / final tests– Focus on interconnects and die-internal circuitry– Test access (probe or socket) at bottom die– Require DFT to propagate test

stimuli / responses up / down through stackbottom die

middle die

top die

• Architecture Impact– Enhance Memory Redundancy Repair– Yield Focused Digital Design– Product Test as part of 3D architecture– BIST Coverage

Page 13: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

13 © 2014 Cadence Design Systems, Inc.

3DIC Design Flow Challenges

3D Aware Die FloorplanOptimize power &TSV/Bump locations

3D Aware Die FloorplanOptimize power &TSV/Bump locations

System Level ExplorationSystem Level Exploration Die ImplementationPlacement, Optimization and Routing

Die ImplementationPlacement, Optimization and Routing

Multi Die Extraction & AnalysisManage Power, Thermal and SI

Multi Die Extraction & AnalysisManage Power, Thermal and SI

DFT for 3DIC Stack& Diagnostics

DFT for 3DIC Stack& Diagnostics Silicon Package Co-DesignSilicon Package Co-Design

TSV /Bump RDL RoutingTSV /Bump RDL Routing

Silicon Interposer

Multi-FabricPlanning View

Device Data Source

BGA BGA.txt from Cadence APD

Si Interposer Created on-the-fly

Die Slice 1 LEF / OrbitIO IOview

Die Slice 2 ASCII data

Page 14: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

14 © 2014 Cadence Design Systems, Inc.

ST-Erricson, LETI and Cadence on Wide IO project

Page 15: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

15 © 2014 Cadence Design Systems, Inc. 15 © 2011 Cadence Design Systems, Inc. All Rights Reserved

3D-IC: STMicroelectronics + CadenceSource: RTI 3D conference 2010 proceedings

Page 16: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

16 © 2014 Cadence Design Systems, Inc.

• Prices drive business – 3D-IC currently not as cost effective– TSV is still an expensive process– Silicon Interposer is an additional cost

• Eventually, overall system level cost advantages will drive 3DIC adoption, but for now, 3DIC is driven by performance, power, and form factor.

• 2.5D-IC may provide more than a transition– Wider Applications– Lesser dependent on standardization– Lesser technical challenges ( Yield, Thermal, Stress, etc)

3D-IC Business ChallengesCost

Page 17: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

17 © 2014 Cadence Design Systems, Inc.

• While not necessary for market adoption, standards will be important to volume production at all levels of 3D

• How will those standards be established?

• KGD, and Who owns what?

• Power grid analysis/ Signal Integrity Analysis for TSV die stacking together with package

3D-IC Business ChallengesStandardization and Supply Chain

Source: GSAGlobal.org

Page 18: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

18 © 2014 Cadence Design Systems, Inc.

• Developed to Enable Power Distribution Network Design and Analysis– also supports interposers, boards and other arbitrary system components– also supports signal nets

• Information in native comment lines at the top of a SPICE model

• Publishes physical information for the design and electrical information for the SPICE model– e.g. design type, external ‘connections’, pin attributes (location, name, pwr/gnd/signal

type, electrical grouping, etc)

• Enables EDA tools to automatically connect high pin-count models, eliminating tedious and error-prone manual effort– enables connectivity based on both physical location and pin/net names, since

mismatches often occur across domain boundaries– not intended for mechanical assembly support

Si2 CPIP FormatChip Package Interface Protocol

Page 19: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

19 © 2014 Cadence Design Systems, Inc.

Si2 CPIP 3D IC Applications

Page 20: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

20 © 2014 Cadence Design Systems, Inc.

Cadence 3D-IC Integrated Solution

Complete Implementation Platforms for flexible Entry Point and Seamless Co-design

Using OpenAccess, EDI, Virtuoso™ each has dedicated 3DIC functions that work together, plus co-design with Cadence SiP tools for complete End to End implementation including early stage system exploration and feasibility

Full Spectrum Analysis Capability RC/ET DFT and ATPG for 3DIC

Voltus/Tempus/QRC Digital Analysis ToolVirtuoso™ Based Full Spice Simulation Capacity

SiP/Sigrity™ based Extraction, SI, and PI System/Package AnalysisPowerDC Thermal Analysis

Ecosystem partnership and Real Experiences/Proof PointsCadence has been working with ecosystem partners since 2007 on 3DIC

8 test chips completed and 1 production chip doneSeveral projects ongoing, with one tapeout Q2, 2014

Page 21: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based

21 © 2014 Cadence Design Systems, Inc.

• 3D/2.5D presents an effective system scaling, as alternative to silicon process scaling;

• 3D/2.5D has its own challenges;• 3D/2.5D realization involves entire cycles with multiple 3D featured

tools working together on the following phases: – Planning, – Implementation, – Physical Verification ( LVS, DRC, ERC)– Electrical and Thermal Analysis, and Digital Signoff – Manufacture Test;

• Standards will be important to volume production at all levels of 3D;

Summary

Page 22: 3D-IC Economics and Design Enablement · RC/ET DFT and ATPG for 3DIC Voltus/Tempus/QRC Digital Analysis Tool Virtuoso™ Based Full Spice Simulation Capacity SiP/Sigrity™ based