3d ic presented by tripti kumari, school of engineering, cusat
DESCRIPTION
A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit. In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other. In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs). Architectural issues Traditional shared buses do not scale well – bandwidth saturation Chip IO is pad limited Physical issues On-chip Interconnects become increasingly slower w.r.t. logic IOs are increasingly expensive Consequences Performance losses Power/Energy cost Design closure issues or infeasibility Reduced wire length Total wire length Larger circuits produce more improvement Lower power per transistor Decreased interconnect delay Higher transistor packing densities Smaller chip areas There are four ways to build a 3D IC: Monolithic Wafer-on-Wafer Die-on-Wafer Die On Die At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty 2 - Thermal Issues In 3-D ICs Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options. 3 - Reliability Issues In 3-D ICs Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips. TSV check on reset Control use dedicated Vias in order to establish which vias are corrupted. If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped! Pads routing shift as show in the figure Need to define The handling protocol during the TSVs check 3D IC design is a relief to interconnect driven IC design. Still many manufacturing and technological difficulties Physical Design needs to consider the multiple layers of Silicon available. Optimization of both temperature and wirelength Placement and routing algorithms need to be modified [1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001. [2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.TRANSCRIPT
3D IC
PRESENTED BY
TRIPTI KUMARI
REG NO – 12110081
S7, CSE, SOE, CUSAT
ROLL NO - 79
SEMINAR GUIDE
MISS LATHA R NAIR
ASSISTANT PROFESSOR
COMPUTER SCIENCE & ENGINEERING
SOE, CUSAT
CONTENTS
INTRODUCTION
WHY 3D
BENEFITS OF 3D INTEGRATION
ARCHITECTURE
MANUFACTURING
PERFORMANCE CHARACTERISTICS
CHALLENGES AND ISSUES
CONCLUSIONS
REFERENCES
INTRODUCTION
• A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit.
• In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
• In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).
EVOLUTION IN INTEGRATION
WHY 3D ?
• Multi-core are bandwidth-hungry:
• Limited caches
• Multi-threading
• Virtualization
“The Bandwidth Challenge”
2.5D VS 3D IC
COMMUNICATION BOTTLENECK
• Architectural issues• Traditional shared buses do not scale
well – bandwidth saturation• Chip IO is pad limited
• Physical issues• On-chip Interconnects become
increasingly slower w.r.t. logic• IOs are increasingly expensive
• Consequences• Performance losses• Power/Energy cost• Design closure issues or infeasibility
BENEFITS OF 3D INTEGRATION
• Reduced wire length
• Total wire length
• Larger circuits produce
more improvement
• Lower power per transistor
• Decreased interconnect
delay
• Higher transistor packing
densities
• Smaller chip areas
ARCHITECTURE
ARCHITECTURE CONT…
IEEE
ARCHITECTURE CONT…
MANUFACTURING
• There are four ways to build a 3D IC:
1.Monolithic
2.Wafer-on-Wafer
3.Die-on-Wafer
4.Die On Die
MONOLITHIC
• A technology breakthrough allows the fabrication of semiconductor devices with multiple thin tiers (<1um) of copper connected active devices utilizing conventional fab equipment.
• Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs.
• There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon via.
WAFER-ON-WAFER
• Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs.
• Each wafer may be thinned before or after bonding.
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Bulk Substrate
Inter-layerbonds
Metal levelof wafer 1
Devicelevel 1
SOI wafers
with bulk substrate removed
Bulk wafer
500mm
10mm
1mm
Detailed view
Generalized view
DIE-ON-WAFER
• Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer
INTER-LAYER INTERCONNECT
DICE
WAFER
DIE ON DIE
• Electronic components are built on multiple dice, which are then aligned and bonded.
• Thinning and TSV creation may be done before or after bonding.
3D FABRICATION TECHNOLOGIES
PERFORMANCE CHARACTERISTICS
• Timing
• Energy
• With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
PERFORMANCE CHARACTERISTICS CONT…
• Timing• In current
technologies, timing is interconnect driven.
• Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
• The graph below shows the results of a reduction in wire length due to 3D routing
PERFORMANCE CHARACTERISTICS CONT…
• Energy
• Wire length reduction has an impact on the cycle time and the energy dissipation
• Energy dissipation decreases with the number of layers used in the design
CHALLENGES AND ISSUES
1- Clock Distribution in 3D
• 2D clock tree very hard but feasible (H-Tree, Differential, Single Ended Clock Distribution)
• Minimizing the clock skew of a clock tree in a complex 3D structure is an extremely challenging task
Clock Root
CHALLENGES AND ISSUES CONT…
high number of vertical vias
• At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty
CHALLENGES AND ISSUES CONT…
2 - Thermal Issues In 3-D ICs
• Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in
power density
• Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different
3D technology and design options.
3 - Reliability Issues In 3-D ICs
• Electro thermal and Thermo-mechanical effects between various active layers can influence
electro-migration and chip performance
• Die yield issues may arise due to mismatches between die yields of different layers, which
affect net yield of 3D chips.
RELIABILITY ENHANCEMENT
• TSV check on reset• Control use dedicated Vias
in order to establish which vias are corrupted.
• If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped!
• Pads routing shift as show in the figure
• Need to define The handling protocol during the TSVs check
CONCLUSION
• 3D IC design is a relief to interconnect driven IC design.
• Still many manufacturing and technological difficulties
• Physical Design needs to consider the multiple layers of Silicon available.
• Optimization of both temperature and wirelength
• Placement and routing algorithms need to be modified
REFERENCES
[1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
THANKYOU
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