3d-ic test standard ieee p1838 · •3d-test standardization study group –january –november...
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3D-IC Test Standard IEEE P1838
Overview
Adam Cron, Principal Engineer
ITC 2016
Special Session 2
2
Participants
•Chair: Saman Adham, TSMC
•Discussant: Sandeep Goel, TSMC
•Overview: Adam Cron, Synopsys
•Serial Control Mechanism: Al Crouch, SiliconAid
•Die Wrapper Register: Teresa McLaurin, ARM
•Flexible Parallel Port: Adam Cron, Synopsys
•Description Language: Sandeep Bhatia, Google
Erik Jan Marinissen
Principal Scientist, imec
Chair, IEEE Std P1838
3
Goals
Extending test access to a stack of die
4
3D-IC StackTop Die
Bottom Die
Top Die Bumps
Bottom Die BumpsBottom Die Bumps
Bottom Die Metal Layers
Bottom Die TSVs
5
Package Possibilities
Image source: Erik Jan Marinissen - IEEE European Test Symposium, 2016
2.5D 3D
•2.5D, 3D, 5.5D: many topologies
•Digital + memory is most prevalent
•Heterogeneous technology nodes
•Higher bandwidth
•Smaller footprint
•Lower power
6
Test Context
1
2
Functional (DFT) logic
Scan Compression
Logic BIST Memory BIST
Scan Compression
Logic BIST Memory BIST
Interconnect Test
Interconnect Test
7
Access Issues and Solutions
• TSVs not accessible
• Contacts too small and close together
• Contacts disappear
Die-Level Pre-Bond Test Partial Stack Mid-Bond Test Complete Stack Post-Bond Test
8
Access Issues and Solutions
Final Package Test System-Level TestComplete Stack Post-Bond Test
Board
9
IEEE Std 1149.1
A little pertinent review
10
In-Circuit Test System
PROBES
CIRCUIT BOARD
IC
TEST EQUIPMENT
11
Boundary-Scan Architecture
CORE CORE
TDITMSTCKTDO
CONNECTOR CIRCUIT BOARD
Virtual Test
Probe
TRST*
12
Basic IEEE Std 1149.1 Architecture
CORE
TDI
TMS
TCK
TDO
TAP
FSM
D QTRST*
13
TAP Output Control Connections
Test
Access
Port
Controller
Data
Registers
ClockIRUpdateIRShiftIRReset*SelectEnableShiftDRUpdateDRClockDR
TMS
TCK
TRST*
TDI
TDO
MSB LSB
MSB LSB
Instruction
Register
14
Instruction
Register
Scans
Data
Register
Scans
Test-Logic-Reset
Run-Test/Idle Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR Pause-IR
Exit2-IR
Update-IR
1
0 011
0
0
1
1
0
1
1
1
0
1
00
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR Pause-DR
Exit2-DR
Update-DR
1
0
0
1
1
0
1
1
1
0
1
00
00
TAP Controller State Machine
TMS
15
Single Chip View at the System Level
TAP Controller
TRST*
TMS
TCK
CaptureIR
ShiftIR
UpdateIR
Reset*
Select
CaptureDR
ShiftDR
UpdateDR
F
S
M
Internal
Protocol
IEEE
1149.1
Core
…
WDRWBYWIR1
50
0
1149.1
ExternalIEEE
1687
IEEE
1500
16
IEEE Std P1838
Technical overview
17
Current Thinking – Each Die Has a TAP
TDI TMS TCK TRST* TDO
Primary
1
WSP1
Secondary
TAP1
18
Current Thinking – Serial Access Up and Down
TDI TMS TCK TRST* TDO
Primary
1
WSP1
Secondary
Primary
Primary
Secondary
2
3 TAP3
TAP2
WSP2
WSP3
TAP1
19
Current Thinking – Multi-Tower Support
TDI TMS TCK TRST* TDO
Primary
1
WSP1
Secondary
Primary
Primary
Secondary
2
3 TAP3
TAP2
WSP2
WSP3
TAP1
4 TAP4
WSP4
20
Current Thinking – Serial Access
TDI TMS TCK TRST* TDO
Primary
1
WSP1
Secondary
Primary
Primary
Secondary
2
3 TAP3
TAP2
WSP2
WSP3
C2C1
C3TAP1
21
Current Thinking – Parallel Access
TDI TMS TCK TRST* TDO
Primary
1
WSP1
Secondary
Primary
Primary
Secondary
2
3 TAP3
TAP2
WSP2
WSP3
C2C1
C3TAP1
SE SI SO
22
IEEE Std P1838
Working Group
23
IEEE P1838 History
•3D-Test Standardization Study Group
– January – November 2010
– Submitted PAR to IEEE-SA NesCom in November 2010
•3D-Test Standardization Working Group
– Active since February 2011 after approval of PAR P1838 by IEEE-SA NesCom
•P1838: “Standard for Test Access Architecture for
Three-Dimensional Stacked Integrated Circuits”
•Timeline
– 2011-2013: Alignment on standardization direction
– Since October 2013: “Tiger Teams” formed in focus areas
– December 2015: Extension of PAR until December 2018
24
P1838 Working Group Organization
http://www.ieee.org/
http://www.computer.org
http://tab.computer.org/tttc/
http://grouper.ieee.org/groups/ttsg/
Test TechnologyStandards Committee
http://grouper.ieee.org/groups/3Dtest/
http://standards.ieee.org/
IEEE StandardsAssociation
Test Technology Technical Council
Working Groupon 3D Test
• P1838 WG Officers
– Chair : Erik Jan Marinissen (imec)
– Vice-Chair : Adam Cron (Synopsys)
– Secretary : Sophocles Metsis (AMD)
– Editor : Michael Wahl (Univ. Siegen)
• WG Meetings
– Bi-weekly conference calls:
Thursdays 5-6pm Europe / 8-9am Pacific
– Ad-hoc face-to-face meetings (e.g., @ITC)
• WG Membership
− Open to professionals, no dues or fees
− ~50 members across the industry
• Public Web-Site
– http://grouper.ieee.org/groups/3Dtest/
25
IEEE P1838 Sub-Groups
•Serial Control Mechanism – Al Crouch
– Test access through serial IEEE 1149.1 TAP interface
•Die Wrapper Register (DWR) – Teresa McLaurin
– Controllability and observability at die boundary
•Flexible Parallel Port (FPP) – Adam Cron
– Multi-bit test access for high bandwidth
•Description Language – Sandeep Bhatia
Thank You
P1838Serial Test Access Architecture
2016 International Test Conference
Al CrouchSiliconAid Solutions
Outline
• Problem Statement
• Recap of a 2D solution
• The Pieces of the 2.5D and 3D Solution
• The Primary TAP Controller
• Secondary TAPs
• Feature Configuration Registers
• Instructions
2
Problem Statement
The configuration of packaging such that die are connected to each other directly or through interposers creates an issue with the access to on-die test features, INTEST capabilities, and requires that die-to-die interconnect be verified in a manner similar to that of verifying the chip’s package connection being attached to a board. This drives the need for a 3D Serial Access solution.
3
Recap of 2D Solution – 1149.1 TAP Controller
TDI
TMS
TCKTDO
TRSTN
Boundary Scan Register
N-Test Data Registers
Bypass Register
IDCode Register
Finite State Machine
DecodeDQ
MUX
MUX
Instruction Register
IR vs DR
4
Recap of 2D Solution – 1149.1 TAP Controller
TDI
TMS
TCKTDO
TRSTN
Boundary Scan Register
N-Test Data Registers
Bypass Register
IDCode Register
Finite State Machine
DecodeDQ
MUX
MUX
Instruction Register
IR vs DR
All the Signalpins on the
package
5
The 1149.1 TAP and TAP Controller
• Provides a defined signal interface
• Provides Instructions to select Registers
• Provides a Serial Access to Read/Write Registers
• Provides defined Registers for Test Features– Boundary Scan Register (interconnect, safety)– Bypass Register (reduction at board to 1-bit)– ID Code Register (identifies chip)
6
The P1838 3D Serial Access Requirements
• Must be Plug-and-Play (per die)
• Must provide a defined signal interface
• Must accommodate 2 or more signal connection interfaces
• Must extend vertically (direct die-to-die)
• Must provide defined Test Features– Die Wrapper Register (interconnect, safety)– Bypass Register (board compliance, stack management)– ID Code Register (identifies die)
7
Example of 2.5D / 3D Added Requirements
TDI
TMS
TCKTDO
TRSTN
Die Wrapper Register(s)
N-Test Data Registers
Bypass Register
IDCode Register
Finite State Machine
DecodeDQ
MUX
MUX
Instruction Register
Lower Upper
Next Die
Return
Up vsDownSelection
IR vs DR
8
Elevator
Example of 2.5D / 3D Added Requirements
TDI
TMS
TCKTDO
TRSTN
Die Wrapper Register(s)
N-Test Data Registers
Bypass Register
IDCode Register
Finite State Machine
DecodeDQ
MUX
MUX
Instruction Register
IR vs DR
Lower Upper
Next Die
Return
Up vsDownSelection
These are selectionchoices – how areselections managed?
9
Elevator
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
10
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
11
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
12
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
13
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
14
Up vs Down
Example of 2.5D / 3D TAP Controller Solution
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
QD
MUX
MUX
Decode
RTI_or_TLR_S1Select_S1
SSTAP_S1_TDO_Int
SSTAP_Sn_TDI_Int
Select_S1_IntRTI_or_TLR_S1_Int
TRSTN_IntTCK_IntTMS_Int
DWR_TDO_Int DWR_TDI_Int
IR vs DR
FPP-Config Register (FPP-CR)
Bypass Register
ID-Code Register
Instruction Register
Finite State Machine
Secondary Config Register (2CR)
Die Wrapper Register(s)
N-Test Data RegistersMUX
15
The P1838 3D Secondary TAP Requirements
• Must be Plug-and-Play (per next die attach point)
• Must provide a defined secondary signal interface
• Must accommodate multiple towers/stacks
• Must allow selected/non-selected configuration– Synchronized TAPC on current die and next die– Parked in Run-Test-Idle (default)– Parked in Test-Logic-Reset
16
The Elevator
Example of 2.5D / 3D Secondary Serial TAP
1
TDO_S1
TMS_S1TCK_S1
TDI_S1
TRSTN_S1
Secondary SerialTAP (SSTAP_Sn) with
2CR control
DQ
MUX
DQSSTAP_Sn_TDO_Int
SSTAP_Sn_TDI_IntSelect_Sn_Int
RTI_or_TLR_Sn_Int
TRSTN_IntTCK_IntTMS_Int
TMS Handler(TMS-H)
MUX1
0
SSTAP_SnTo Primary TDI of
Next Die
From Primary TDO of Next Die
To Primary TMS of Next Die
To Primary TCK of Next Die
To Primary TRSTN of Next Die
17
Sync’s or Parks on UpdateDR-to-RTI
Example of 2.5D / 3D Secondary Serial TAP
1
TDO_S1
TMS_S1TCK_S1
TDI_S1
TRSTN_S1
Secondary SerialTAP (SSTAP_Sn) with
2CR control
DQ
MUX
DQSSTAP_Sn_TDO_Int
SSTAP_Sn_TDI_IntSelect_Sn_Int
RTI_or_TLR_Sn_Int
TRSTN_IntTCK_IntTMS_Int
TMS Handler(TMS-H)
MUX1
0
SSTAP_SnTo Primary TDI of
Next Die
From Primary TDO of Next Die
To Primary TMS of Next Die
To Primary TCK of Next Die
To Primary TRSTN of Next Die
18
Sync’s or Parks on UpdateDR-to-RTI
The Secondary Serial TAP Configuration Register (2CR)
19
TDI
TCK
TRSTNTLR-Rst
RTIorTLR_Sn
S
U
S
U
Select_Sn
S
U
RTIorTLR_S2
S
U
Select_S2 Select_S1
S
U
RTIorTLR_S1
S
U
TDO
S
U
ConfigHold_2CR
ConfigHold_2CR
The P1838 3D Die Wrapper Requirements
• Must be Plug-and-Play (per die)
• Must accommodate multiple surfaces/interfaces
• Must allow segmented configurations
• Must allow featured mode configurations– Inward-facing test– Outward-facing test– Functional configuation (transparent)
20
Example of 2.5D / 3D Die Wrapper Register
21
Primary Die Wrapper Register (PDWR)
Secondary Die Wrapper Register (SDWR)
Die Wrapper Register Segment (SDWR_S1)
Die Wrapper Register Example Architecture
DWR_TDI_Int DWR_TDO_Int
MUX
SU
MUX
SU
MUX
SU
MUX
SU
Select PrimaryDWR
Select Secondary DWR
Select DWRSegment
Select DWRSegment
Configuration of Active Scan Segments done withIn-Line Segment-Insertion-Bits (SIBs)
The P1838 3D Instruction Requirements
• Must allow 1149.1 Mandated/Optional Instructions
• Must manage Instruction Explosion
• Must allow P1838 Mandated/Optional Features
• Instructions are allowed to be represented in other ways– In-Line control and configuration bits– Configuration Registers (includes 1500 WIRs)– Feature Registers
22
Table of Instructions
InstructionName
SelectsRegister
SelectsDirection
SelectsPersistence
SelectsSegments
ConfiguresDWR
Comments
BYPASS1 Bypass 2CR NA NA NA 1149.1 = BypassDownIDCODE1 ID Code 2CR NA NA NA 1149.1 = JEDEC #sEXTEST1 DWR Primary 2CR TMP Reg SIBs Outfacing 1149.1 permissionINTEST1 DWR Primary 2CR TMP Reg SIBs Infacing 1149.1 permissionPRELOAD1 DWR 2CR TMP Reg SIBs Transparent 1149.1 permissionSAMPLE1 DWR 2CR TMP Reg SIBs Transparent 1149.1 permissionCLAMP1 Bypass 2CR TMP Reg NA Outfacing 1149.1 permissionSELDWR2 DWR 2CR TMP Reg SIBs DWR-CR P1838 DWR ManagementSEL2CR2 2CR NA ConfigHold NA NA P1838 Elevator ManagementSELFPP2 FPP-CR NA ConfigHold NA NA P1838 Parallel Port
23
1. With the 2CR zero’ed out, these instructions match their 1149.1 definitions2. The Select Config Register Instructions select only the target CR, no concatenations allowed
Conclusion: P1838 Per Die Serial Test Architecture
Primary Die Wrapper Register (PDWR)
Secondary Die Wrapper Register (SDWR)
Die Wrapper Register Segment (SDWR_Sn) MUX S
U
MUX S
UMUX S
U
Die Wrapper Register Architecture
Serial Portion: Updated Aug 9, 2016Big Picture Architecture
1TDO_S1
TMS_S1
TCK_S1
TDI_S1
TRSTN_S1
TMS-H
Secondary SerialTAP (SSTAP_Sn) with
2CR control
DQ
DQMUX
2TDO_S2
TMS_S2
TCK_S2
TDI_S2
TRSTN_S2
TMS-H
Secondary SerialTAP (SSTAP_Sn) with
2CR control
DQ
DQMUX
TDI
TMS
TCK
TDO
TRSTN
After TAPPoint
MUX
Up vs Down
QD
MUX
MUX
Mandated Primary TAP andTAP Controller Architecture
IR vs DR
ID-Code Register
Bypass Register
Decode
Instruction Register
Finite State Machine
FPP-Config Register
RTI_or_TLR_S1Select_S1
RTI_or_TLR_S2Select_S2
2 Config Register
24
Thank You
Title 44pt sentence case
Affiliations 24pt sentence case
20pt sentence case
3D-IC Test Standard IEEE P1838 – Die Wrapper Register
Teresa McLaurin
ITC 2016
ARM Fellow and DFT Architect
16 Nov 2016
© ARM 2016 2
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Collection of P1838 compliant wrapper cells connected into one or more scan chains
Test data required at a die terminal is contained solely in the wrapper cell provided to this terminal
What is a Die Wrapper Register (DWR)
CTI
CTO
CFICFO
CLK
CTI
CTO
CFICFO
CLK
CTO
CTI
CFICFO
CLK
CTO
CTI
CFICFO
CLK
DFI_0 functional die input logic
functional die output logic DFO_0
TI[0] TI[1]
DFI_1DFO_1
functional die input logic
functional die output logic
WrapperTO[0] TO[1]
CTI
CTO
CFICFO
CLK
CTI
CTO
CFICFO
CLK
CTO
CTI
CFICFO
CLK
CTO
CTI
CFICFO
CLK
DFI_0 functional die input logic
functional die output logic DFO_0
TI TO
DFI_1DFO_1
functional die input logic
functional die output logic
Wrapper
© ARM 2016 3
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Die Wrapper Register
Last Die
First Die
interconnect
Die Wrapper Register
Enables isolated INTEST of the die
Enables EXTEST (using only the wrapper logic) of the TSV interconnect logic
All digital die terminals, with some exceptions, must have a fully-provisioned wrapper
cell. Non-digital signals under discussion
Example exceptions – clocks, asynchronous set or reset, specified test signals
© ARM 2016 4
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1TI
Second Die
First Die
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TO
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
D Q
ENR Q
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TI
TDI TDO
TDI TDO
One serial configuration in which all DWR cells are concatenated into a single chain
At least one DWR cell between TI and TO when a segment is selected
Can reuse 1149.1 bscan and most 1500 WBR cells
DWR
© ARM 2016 5
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Die Wrapper Register
Secondary Functional Interface 2 DWR
Secondary Functional Interface 1 DWR
Primary Functional Interface DWR
Die 1
Die 2 Die 3
Recommendation: each primary and secondary functional interface segment should have
its own DWR serial chain
© ARM 2016 6
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
More DWR segments permitted. When multiple segments (scan chains) must be run
simultaneously the Flexible Parallel Port (FPP) is used.
Die Wrapper Register
Die 1
Die 2
© ARM 2016 7
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Die Wrapper Register (DWR) Cells
© ARM 2016 8
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Fully-provisioned – minimum requirements
One cell between the CFI and CFO
One cell between the CTI and CTO
Service Shift event – An event whereby the data is moved from CTI into the storage element
Service Capture event – An event whereby the data is moved from CFI into the storage element
Enable Apply event – An event where by the data is applied at CFO
Two types of DWR cells
SC
CTI
CTO
CFI CFO
D
SI
CFI CFO
Q
CTI
CTO
SC
shift
capture
apply
shift
capture apply
capture
© ARM 2016 9
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Partially-provisioned
Shift
Capture or Apply
Two types of DWR cells
Functional path
Observe-Only DWR Cell
CTI
Shift Enable
Die Input Terminal
CTO CFI
Functional path
Control-Only DWR Cell
CTI
Shift Enable
Die Input Terminal CFO
CTO
© ARM 2016 10
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Shared and Dedicated Wrapper Cells
Registered Input Port
Unregistered Input Port
SI
D
Shared DWR Cell
Dedicated DWR Cell
© ARM 2016 11
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
DWR cells can have an update capability and it is required or recommended in
some cases
For safety
For special control
Reuse of a boundary scan cell
DWR cells can have safe gates
DWR cells can be observe or control only
DWR cells can have multiple sequential elements
Options
© ARM 2016 12
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Implementation independent representation
Graphical building blocks:
Storage element
(e.g. Flipflop)
Data path
Data flow decision point
(e.g. mux)
??
S: Shift
C: Capture
U: Update
F: Functional element
Describing DWR cells Bubble diagram
© ARM 2016 13
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
S
CTO
CTI
SHIFT
C CFI
C CFO
CAPTURE UPDATE
U CFO
SC F CFI CFO
CFI CFO
FUNCTIONAL
DWR cell operations
Bubble diagram representation
© ARM 2016 14
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
DWR Naming Convention
© ARM 2016 15
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
/DC(_S[DF]\d+)(_C([IO\d+]))|N)?(_U)?(_O)?(_G[01]?)?/
DWR Naming Convention
SCF
CTI
CTO
CFI CFO
DC_SF1_CI1
SC
CTI
CTO
CFI CFO
DC_SD1_CO1 DC_SD1_CI1
D
SI
CFI CFO
CTI
CTO
SCF
© ARM 2016 16
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Shared DWR cell with the optional Gate
SCF
CTI
CTO
CFI
CFO
G
DC_SF1_CI1_G
Safe
Value
© ARM 2016 17
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
DWR cell with the update option
SC
CTI
CTO
CFI
CFO
U
DC_SD1_CI1_U
© ARM 2016 18
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
DWR cell with multiple sequential elements
SC
CTI
CTO
CFI CFO
DC_SD2_CI1
S
S
SC
DC_SD2_CI2
© ARM 2016 19
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Partially-provisioned DWR cell
SC
CTI
CTO
CFI CFO
DC_SD1_CI1_O
© ARM 2016 20
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Reuse of IEEE 1500 wrapper cells in DWR
TI TO
WIR
© ARM 2016 21
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
/DC(_S[DF]\d+)(_C([IO\d+]))|N)?(_U)?(_O)?(_G[01]?)?/
/((WC)|(WH))((_S[DF]\d+)|(_CI?))(_C([IOB][IOU])|N)?(_U[DF])?(_O)?(_G[01]?)?/
Reuse of IEEE 1500 wrapper cells in DWR
TI TO
SD2
CIU
UF G
/WC(_S[DF]\d+)(_C([IO])|N)?(_U)?(_O)?(_G[01]?)?/
© ARM 2016 22
Title 40pt sentence case
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Sub-bullets 20pt sentence case
Safe Operation pertains to moving into and out of a test mode safely
In addition there are rules and recommendations around safe operation during test
The control signal on any three-state buffer on an output terminal of a die shall have a fully-provisioned
wrapper cell.
Any three-state buffer on an output terminal of a die shall include control that is able to establish a
persistent safe drive state on that output terminal during shift.
Safe Operation
Fully-provisioned
DWR cell
Fully-provisioned DWR cell
w/ optional safe gate
© ARM 2016 23
Title 40pt sentence case
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Sub-bullets 20pt sentence case
Safe Operation
Die 1
Die 2 Die 3
The unselected segments can be in a test mode or functional mode
If the DWR cell has update capability, the update must not occur if the segment in which
the DWR cell resides is not selected
Die 1
SC CTI
CFO
CTO
CFI
U
© ARM 2016 24
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
All die wrapper cells inline with other scan wrapper cells which control die wrapper segmentation
multiplexers shall include a shift, capture, and update capability; the update shall be with delay such that
the output of the inline segment select cell does not change until at least one half TCK cycle after
UPDATE-DR.
Safe Operation
DWR Segments UpdateDR
1
0
© ARM 2016 25
Title 40pt sentence case
Bullets 24pt sentence case
Sub-bullets 20pt sentence case
Registered Input Port
Unregistered Input Port
SI
D
SI
D
Shared DWR Cell
Inland Shared DWR Cell
Registered Input Port
Unregistered Input Port
D
SI
D
Shared DWR Cell
Dedicated DWR Cell
SI
D Internal Cell
Inland Wrapping
3D-IC Test Standard IEEE P1838
Flexible Parallel Port
Adam Cron, Principal Engineer
ITC 2016
Special Session 2
2
3
Registered Lane, Logical ImplementationSecondary Port
Primary Port
Lane
1
0die
0 1
FPP_PRI_EN
FPP_SEC_EN
FPP_REGPU_BYP
FPP_REGN_BYP
FPP_CORE_SEL
FPP_PRI_SEL
10
FPP_FROM_CORE
FPP_TO_CORE
FPP_CLK_IN
FPP_SEC
FPP_PRI
FPP_SIDE_SEL
FPP_FROM_SIDE
FPP_TO_SIDE
0 1
0 1
1
0
FPP_REGPD_BYP
01
4
Non-Registered Lane, Logical Implementation
Lane
die
FPP_PRI_EN
FPP_SEC_EN
FPP_CORE_SEL
FPP_PRI_SEL
FPP_FROM_CORE
FPP_TO_CORE
FPP_SEC
FPP_PRI
FPP_SIDE_SEL
FPP_FROM_SIDE
FPP_TO_SIDE
0 1
0 1
1
0
5
Registered Lane, Up Only
Lane
1
0die
FPP_SEC_EN
FPP_REGPU_BYP
FPP_REGN_BYP
FPP_TO_CORE
FPP_CLK_IN
FPP_SEC
FPP_PRI
0 1
6
Simple Clock Path
Lane
die
FPP_SEC_EN
FPP_TO_CORE
FPP_SEC
FPP_PRI
FPP_CLK_OUT
7
Non-Registered Lane, Down Only
Lane
die
FPP_PRI_EN
FPP_CORE_SEL FPP_FROM_CORE
FPP_SEC
FPP_PRI
1
0
8
FPP Application
1
2
Functional (DFT) logic
Scan Chains
Test Modes
9
3
FPP Broadcast Application
1
2
Functional (DFT) logic
10
FPP Configuration Register
TR
ST
*
TC
K
TM
S
TD
I
TD
O
FPPCONFIG Reg
C U C U
ShiftDR
FPP_CONFIG
UpdateDR
C U
1
0
1
0
1
0
1
0
1
0
1
0C U
1
0
1
0
Reset*
FPP0FPP1FPP2
Lane
FPP_SEC
FPP_PRI
1
0
die
11
Bi-Directional “Layout”
1
0
0 1
FPP_PRI
1
0
1 0
FPP_TO_CORE
FPP_FROM_CORE
0 1
1
0
0 11
0
011
0
10
FPP_TO_CORE
FPP_FROM_CORE
1
0
FPP_PRI
FPP_SECFPP_SEC
12
Bypassable Pipe-Lined Entity
1
0
13
Bi-Directional “Layout” with Bypassable Elements
1
0
0 1
FPP_PRI
1
0
1 0
FPP_TO_CORE
FPP_FROM_CORE
0 10 1
1
0
011
0
10
FPP_TO_CORE
FPP_FROM_CORE
FPP_PRI
FPP_SECFPP_SEC
Thank You
P1838 Test Description Language(s)Sandeep BhatiaGoogle
P1838 Elements
● Serial Control● Die Wrapper Register● Flexible Parallel Port
Language Options
Extend and Reuse existing languages
● 1149.1 BSDL (Serial Control)● 1450.6 CTL (Die Wrapper Register, FPP)● 1687 ICL (FPP)
Or use a New Language
Challenges with Reuse
● Language Extensions ● Mix of languages to describe the complete standard● Complexity - irrelevant language constructs
Test Data Languages
● Key-Value tuples● Bundling of data● Nesting/Hierarchy of data
Environment { CTL config1 { Internal { Ck { DataType TestClock { AssumedInitialState ForceDown; } } } SI { DataType TestData ScanDataIn; } }}
CTL
Key Value tuplesCTLEnvironment { CTL config1 { Internal { Ck { DataType TestClock { AssumedInitialState ForceDown; } } } SI { DataType TestData ScanDataIn; } }}
BSDLAttribute TAP_SCAN_IN of TDI : signal is True;Attribute TAP_SCAN_OUT of TDO : signal is True;Attribute TAP_SCAN_MODE of TMS : signal is True;Attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);Attribute INSTRUCTION_LENGTH of foo : entity is 2;Attribute INSTRUCTION_OPCODE of foo: entity is “BYPASS (11), “&& Attribute INSTRUCTION_OPCODE of foo: entity is “EXTEST (00), “&&
BSDLKey Value tuples
Attribute TAP_SCAN_IN of TDI : signal is True;Attribute TAP_SCAN_OUT of TDO : signal is True;Attribute TAP_SCAN_MODE of TMS : signal is True;Attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);Attribute INSTRUCTION_LENGTH of foo : entity is 2;Attribute INSTRUCTION_OPCODE of foo: entity is “BYPASS (11), “&& Attribute INSTRUCTION_OPCODE of foo: entity is “EXTEST (00), “&&
ICLModule SIB { ScanInPort si; ScanOutPort so { Source SIB; LaunchEdge Falling; } SelectPort en; ScanRegister sr { ScanInSource mux1; CaptureSource 1’b0; ResetValue 1’b0; }}
ICLKey Value tuples
Module SIB { ScanInPort si; ScanOutPort so { Source SIB; LaunchEdge Falling; } SelectPort en; ScanRegister sr { ScanInSource mux1; CaptureSource 1’b0; ResetValue 1’b0; }}
Protocol Buffers● Structured data representation● Key:Value tuple format with data bundling and nesting ● Schema definition for specific format● Open source Parser with automatic API generation to access data● Multiple platforms
○ OSX, Linux, Windows● Multiple Programming language support
○ Python, C++, Java, Go, Ruby, C#, Javanano
[1] https://developers.google.com/protocol-buffers/[2] Licensed under 3BSD License (https://github.com/google/protobuf/blob/master/LICENSE)
IEEE 1838 EDA Integration
Open Source Proto-Compiler
IEEE1838 proto-buffer (Schema)
EDA Application
Design Specific proto-buffer
(data)
FPP Proto Buffer Schema
message Fpp { int32 channel_count = 1; repeated Channel channel = 2; }
FPP Proto Buffer Schema
message Fpp { int32 channel_count = 1; repeated Channel channel = 2; }
message Channel { string name = 1; ChannelType type = 2; string clock = 3; int32 lane_count = 4; repeated Lane lane = 5; }
FPP Proto Buffer Schema
message Fpp { int32 channel_count = 1; repeated Channel channel = 2; }
message Channel { string name = 1; ChannelType type = 2; string clock = 3; int32 lane_count = 4; repeated Lane lane = 5; }
enum ChannelType { Registered = 0; Unregistered = 1; }
FPP Proto Buffer Schema
message Fpp { int32 channel_count = 1; repeated Channel channel = 2; }
message Channel { string name = 1; ChannelType type = 2; string clock = 3; int32 lane_count = 4; repeated Lane lane = 5; }
enum ChannelType { Registered = 0; Unregistered = 1; }
message Lane { string name = 1; string fpp_pri = 2; string fpp_sec = 3; string from_side = 4; string to_side = 5; }
FPP Proto Buffer Data channel { name: “bar” type: Registered clock: “foo.lane_1” lane_count: 2 lane { name: “lane_1” fpp_pri: “pdata[0]” fpp_sec: “sdata[0]” } lane { name: “lane_2” fpp_pri: “pdata[1]” fpp_sec: “sdata[1]” } }}
Fpp { channel_count: 2
channel { name: “foo” type: Unregistered lane_count: 1 lane { name: “lane_1” fpp_pri: “pck” fpp_sec: “sck” } }
sck
pck pdata
sdatafoo bar
Current Status
● Evaluating different options○ Proto Buffer Schema design○ Existing Language suitability, extensions, complexity
● Unify
Questions