3rd 3ddresd: valerie
TRANSCRIPT
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POLITECNICO DI MILANO
SyCERSSystemC Embedded Reconfigurable systems Simulator
Dynamic Reconfigurability in Embedded Systems Design
Chiara Sandionigi: [email protected]
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Outline
SyCERS beginsIssuesAimsIntegration in EarendilRefactoringExperimental resultsComparison between SyCERS versionsFuture workConclusions
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SyCERS begins
SyCERSFramework for design and simulation of dynamically reconfigurable embedded systems
SystemC choiceHW/SW co-simulationSeparation between system functionalities and communication details
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SyCERS begins
SystemC choiceModeling of reconfiguration exploiting SystemC module’s structure
sc_method/sc_thread
sc_module
Unlocked
Locked
Reconfiguration
Elaboration
Time
*f() *g() *g() *g()
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SyCERS begins
ApplicationsDES encoderMD5Adaptive filter
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Issues
Applications use SyCERS modules, and not the other way around
It is needed to write ad hoc applicationsApplications can not directly run on FPGA
It is needed to create a new SyCERS instance for each application
Scheduler module is integrated with reconfiguration controller moduleSyCERS uses only one scheduling policySyCERS doesn’t use placement policySyCERS considers only one time and size for blackboxes reconfiguration
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Aims
SyCERS refactoring in order toseparate SyCERS structure from applicationshave a dynamic loading of applications
have a plugin structure for applications loading
Integration with EarendilIntegration with ReSP (Reflective Simulation Platform)Enhancement of existing modules, e.g. scheduling moduleCreation of new modules, e.g. placement moduleEnhancement of reconfiguration modeling, considering different times and sizes for reconfiguration
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Integration in Earendil
Earendil: DRESD tool chain software developmentAims
centralize and manage DRESD team’s workdefine a complete work flow for dynamically reconfigurable embedded systems
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RefactoringDynamic loading of applicationsApplications can run on FPGA
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Experimental resultsInput parameters for DES applied to 1,28 kb fileMemory dimension: 500 kBMemory reading time: 30 nsMemory writing time: 30 nsReconfiguration time: 500 ms
Blackbox Number of operations
Activity Execution time (ms)
1 2 0,18 500,00102
2 11 1 500,0024
3 6 0,54 500,00216
4 6 0,54 500,00204
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Comparison between SyCERS versions
Old SyCERSChoice between 3 SyCERS versions
Input parameters depending both by the system and the applicationApplications not runnable on FPGA
New SyCERSChoice between applications found in a path specified by the userInput parameters depending only by the system
Applications runnable on FPGA
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Future work
Integration with ReSP (Reflective Simulation Platform)Enhancement of existing modules, e.g. scheduling moduleCreation of new modules, e.g. placement moduleEnhancement of reconfiguration modeling, considering different times and sizes for reconfigurationApplications running on FPGA
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Conclusions and future work
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Conclusions and future work
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Conclusions and future work