February 7, 2019 10:21 am EE457 Quiz - Spring 2019 9/12 C Copyright 2019 Gandhi Puvvada

4 ( 19 +39 = 58 points) 25 min. Memory addresses

4.1 You are aware that the Intel 80486 processor is a 32-bit data 32-bit logical address byte addressable processor and the Intel i860 processor is a 64-bit data 32-bit logical address byte addressable processor. The address spaces are ______ (A/B) where A: 4 GB for each, B: 16 GB (232 locations each of 32 bits wide) for 80486 and 32 GB (232 locations each of 64 bits wide) for i860

Intel follows ___________ (Little Endian / Big Endian) system. In the Intel 80486 processor system address space, byte 1234_567FH is the ____________ (most / least) significant byte of the 32-bit word with system address __________________ (state in hexadecimal). State the next three 32-bit word addresses (in hex), next to the 32-bit word containing the above byte _________________________ _________________________ _________________________Let us now repeat the above question for the Intel i860 processor. In the Intel i860 processor system address space, byte 1234_567FH is the ____________ (most / least) significant byte of the 64-bit word with system address __________________ (state in hexadecimal). State the next three 64-bit word addresses (in hex), next to the 64-bit word containing the above byte _________________________ _________________________ _________________________

4.2 Shown on the side is the memory interface to a byte-wide memory chip in a memory system based on minimum number of byte-wide banks for an exotic USC512 processor (512-bit data, 32-bit logical address, byte-addressable processor) . USC processors are similar to Intel processors (Byte Enable pins and Endianess). The address pins on this processor are (select) (i) A[31:0] (ii) A[31:3],/BE[7:0] (iii) A[31:4],/BE[15:0](iv) A[31:5],/BE[31:0] (v) A[31:6],/BE[63:0] (vi) A[31:7],/BE[127:0]

Fill-in the 6 blanks (marked by the 6 arrows) in the figure on the side. Also find the system addresses corresponding to the lowest-addressed two bytes of this memory chip. The lowest-addressed two bytes of this chip map to the system byte addresses (in hex) _______________________________ _________________________________________________.

The system addresses mapping to any location in this memory chip will have the same upper _____ (state a number) bits namely ________________ (state their labels in the form X[13:2]).

The system addresses mapping to any location in this memory chip will have the same lower _____ (state a number) bits namely ________________ (state their labels in the form Y[13:2]).

If this chip goes bad, until you replace, you should avoid using memory addresses ______ (X/Y) where X: which map to this bad chip only, Y: which map to the composite space occupied by this chip as well as similar sized spaces in all other banks (Note: Here the words "composite space" mean contiguous or continuous address range). Address range with "holes" (bad spots) is useless!.

State the range of the unusable address range in hex: _____________________________________

19pts

8 pts

8 pts

1 pts

2 pts

A31A30A29A28A27A26A25A24

CS

WERD

A[ : ]D[7:0]

D[ : ]

A[23: ]

BE6

______KB

Note

Shift in address for 80486: ______Shift in address for USC512: ______

39pts

3 pts

11 pts

5 pts

2 pts

2 pts

2 pts

4 pts

February 7, 2019 10:21 am EE457 Quiz - Spring 2019 9/12 C Copyright 2019 Gandhi Puvvada

4 ( 19 +39 = 58 points) 25 min. Memory addresses

4.1 You are aware that the Intel 80486 processor is a 32-bit data 32-bit logical address byte addressable processor and the Intel i860 processor is a 64-bit data 32-bit logical address byte addressable processor. The address spaces are ______ (A/B) where A: 4 GB for each, B: 16 GB (232 locations each of 32 bits wide) for 80486 and 32 GB (232 locations each of 64 bits wide) for i860

Intel follows ___________ (Little Endian / Big Endian) system. In the Intel 80486 processor system address space, byte 1234_567FH is the ____________ (most / least) significant byte of the 32-bit word with system address __________________ (state in hexadecimal). State the next three 32-bit word addresses (in hex), next to the 32-bit word containing the above byte _________________________ _________________________ _________________________Let us now repeat the above question for the Intel i860 processor. In the Intel i860 processor system address space, byte 1234_567FH is the ____________ (most / least) significant byte of the 64-bit word with system address __________________ (state in hexadecimal). State the next three 64-bit word addresses (in hex), next to the 64-bit word containing the above byte _________________________ _________________________ _________________________

4.2 Shown on the side is the memory interface to a byte-wide memory chip in a memory system based on minimum number of byte-wide banks for an exotic USC512 processor (512-bit data, 32-bit logical address, byte-addressable processor) . USC processors are similar to Intel processors (Byte Enable pins and Endianess). The address pins on this processor are (select) (i) A[31:0] (ii) A[31:3],/BE[7:0] (iii) A[31:4],/BE[15:0](iv) A[31:5],/BE[31:0] (v) A[31:6],/BE[63:0] (vi) A[31:7],/BE[127:0]

Fill-in the 6 blanks (marked by the 6 arrows) in the figure on the side. Also find the system addresses corresponding to the lowest-addressed two bytes of this memory chip. The lowest-addressed two bytes of this chip map to the system byte addresses (in hex) _______________________________ _________________________________________________.

The system addresses mapping to any location in this memory chip will have the same upper _____ (state a number) bits namely ________________ (state their labels in the form X[13:2]).

The system addresses mapping to any location in this memory chip will have the same lower _____ (state a number) bits namely ________________ (state their labels in the form Y[13:2]).

If this chip goes bad, until you replace, you should avoid using memory addresses ______ (X/Y) where X: which map to this bad chip only, Y: which map to the composite space occupied by this chip as well as similar sized spaces in all other banks (Note: Here the words "composite space" mean contiguous or continuous address range). Address range with "holes" (bad spots) is useless!.

State the range of the unusable address range in hex: _____________________________________

19pts

8 pts

8 pts

1 pts

2 pts

A31A30A29A28A27A26A25A24

CS

WERD

A[ : ]D[7:0]

D[ : ]

A[23: ]

BE6

______KB

Note

Shift in address for 80486: ______Shift in address for USC512: ______

39pts

3 pts

11 pts

5 pts

2 pts

2 pts

2 pts

4 pts

Page 23 of 55

Page 43 of 55

September 20, 2018 8:55 am EE457 Quiz - Fall 2018 C Copyright 2018 Gandhi Puvvada

4 ( 5 + 7 + 20 + 12 = 44 points) 20 min. MIPs Instructions and Memory addresses

4.1 The ______ (1/2/3) instruction(s) _______________ (preceding/following) the JAL instruction in execution (in execution = in the dynamic execution trace), together with the JAL instruction in MIPS make up the CISC CALL instruction. Similarly the ______ (1/2/3) instruction(s) _______________ (preceding/following) the JR $31 instruction in execution (in execution = in the dynamic execution trace), together with the JR $31 instruction in MIPS make up the CISC RTN (Return) instruction.

4.2 Intel follows ___________ (Little Endian / Big Endian) system. In the Intel 80486 processor system address space, byte 0000_800CH is the ____________ (most / least) significant byte of the 32-bit word with system address ______________ (state in hexadecimal).The 32-bit word 8000 consists of the four bytes 8000, 8001, 8002, and 8003 in ________________________________ (Little-Endian / Big-Endian / both kinds of /neither kind of) processor.

4.3 Intel processors, 80486 and i860, are both 32-bit logical address, byte addressable processors.The 80486 is a 32-bit data processor where as the i860 is a 64-bit data processor. Their address space(s) is/are ________ (the same / different). State the size of their address space(s): ____________________. If stacks of 4 MByte SRAM chips are placed in their byte-wide memory banks to fill-up their entire address spaces, what are the lowest and highest system byte addresses which map to the bottom and the top of the specific 4 MByte chip to which the system byte address 2345_ABC6 hex maps to?

In the case of 80486, the bottom is _ _ _ _ _ _ _ _ _ hex and the top is _ _ _ _ _ _ _ _ _ hex.

And in the case of i860, the bottom is _ _ _ _ _ _ _ _ _ hex and the top is _ _ _ _ _ _ _ _ _ hex.And if this chip goes bad, what is the total system address range in hex that needs to be declared as unusable?

(i) in the case of 80486 processor, it is _ _ _ _ _ _ _ _ _ hex to _ _ _ _ _ _ _ _ _ hex.

(ii) in the case of i860 processor, it is _ _ _ _ _ _ _ _ _ hex to _ _ _ _ _ _ _ _ _ hex.

4.3.1 Complete address decoding to generate Group-Selects (/GS_486 and /GS_860) for the row of chips and also show the rest of the labels for address, data, and byte-enable.

4+1pts

5+2pts

16+4 pts

12pts

A31A30A29A28

CS

WERD

A[ ]D[7:0]

D[ ]

A[ : ]

BE

4 MByte

2

/GS_486

A31A30A29A28

CS

WERD

A[ ]D[7:0]

D[ ]

A[ : ]

BE

4 MByte

2

/GS_860

Intel 80486 Intel i860

September 20, 2018 8:55 am EE457 Quiz - Fall 2018 C Copyright 2018 Gandhi Puvvada

4 ( 5 + 7 + 20 + 12 = 44 points) 20 min. MIPs Instructions and Memory addresses

4.1 The ______ (1/2/3) instruction(s) _______________ (preceding/following) the JAL instruction in execution (in execution = in the dynamic execution trace), together with the JAL instruction in MIPS make up the CISC CALL instruction. Similarly the ______ (1/2/3) instruction(s) _______________ (preceding/following) the JR $31 instruction in execution (in execution = in the dynamic execution trace), together with the JR $31 instruction in MIPS make up the CISC RTN (Return) instruction.

4.2 Intel follows ___________ (Little Endian / Big Endian) system. In the Intel 80486 processor system address space, byte 0000_800CH is the ____________ (most / least) significant byte of the 32-bit word with system address ______________ (state in hexadecimal).The 32-bit word 8000 consists of the four bytes 8000, 8001, 8002, and 8003 in ________________________________ (Little-Endian / Big-Endian / both kinds of /neither kind of) processor.

4.3 Intel processors, 80486 and i860, are both 32-bit logical address, byte addressable processors.The 80486 is a 32-bit data processor where as the i860 is a 64-bit data processor. Their address space(s) is/are ________ (the same / different). State the size of their address space(s): ____________________. If stacks of 4 MByte SRAM chips are placed in their byte-wide memory banks to fill-up their entire address spaces, what are the lowest and highest system byte addresses which map to the bottom and the top of the specific 4 MByte chip to which the system byte address 2345_ABC6 hex maps to?

In the case of 80486, the bottom is _ _ _ _ _ _ _ _ _ hex and the top is _ _ _ _ _ _ _ _ _ hex.

And in the case of i860, the bottom is _ _ _ _ _ _ _ _ _ hex and the top is _ _ _ _ _ _ _ _ _ hex.And if this chip goes bad, what is the total system address range in hex that needs to be declared as unusable?

(i) in the case of 80486 processor, it is _ _ _ _ _ _ _ _ _ hex to _ _ _ _ _ _ _ _ _ hex.

(ii) in the case of i860 processor, it is _ _ _ _ _ _ _ _ _ hex to _ _ _ _ _ _ _ _ _ hex.

4.3.1 Complete address decoding to generate Group-Selects (/GS_486 and /GS_860) for the row of chips and also show the rest of the labels for address, data, and byte-enable.

4+1pts

5+2pts

16+4 pts

12pts

A31A30A29A28

CS

WERD

A[ ]D[7:0]

D[ ]

A[ : ]

BE

4 MByte

2

/GS_486

A31A30A29A28

CS

WERD

A[ ]D[7:0]

D[ ]

A[ : ]

BE

4 MByte

2

/GS_860

Intel 80486 Intel i860