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A 24Gb/s Software Programmable Multi-Channel TransmitterA. Amirkhany1, A. Abbasfar2, J. Savoj2, M. Jeeradit2, B. Garlepp2, V. Stojanovic2'3, and M. Horowitz' 2

Stanford University, 2Rambus Inc., 3Massachusetts Institute of Technology

Abstract DAC network and the equalizer network to resolve setup andA 24Gb/s transmitter with a digital linear equalizer is hold time violations. Equalizer clock distribution is in the

implemented in 90nm CMOS technology. It supports 4- form of a mesh. The clock to the pattern-generator blockchannel Analog Multi-Tone (AMT) transmission, where each branches off from an ending leaf of the equalizer clock mesh.channel supports 3GSym/Sec 4PAM data, as well as a variety Clock distribution latency in the pattern-generator block isof baseband (BB) modes ranging from 2 PAM to 256 PAM. constrained such that setup time is met at the interfaceThe transmitter operates at maximum rate of 24Gb/s, between the pattern-generator block and the equalizer.dissipating 510mW of power in 0.8mm2 Fig. 3 shows the digital equalizer programmed in AMT

mode and in 6GSym/Sec 16PAM BB mode. Due to spaceIntroduction limitations 8-taps per channel (instead of 16) are shown. In the

An Analog Multi-Tone system has been recently proposed chip, 12GSym/Sec 2PAM/4PAM mode can have up to 13[1] as an alternative to traditional baseband systems [2] to taps, 6GSym/Sec 8PAM/16PAM mode up to 14 2-times over-improve the scaling of energy-efficient link data rates over sampled taps, and 3GSym/Sec 128/256PAM up to 16 4-timesband-limited channels. A conceptual architecture of a 4- over-sampled taps. The transmitter can also be programmed inchannel AMT system is shown in Fig. 1. Each 4-times over- a 2-channel AMT mode. As shown in this figure, an AMTsampled equalizer in the transmitter has control over the entire transmitter is very similar to a parallelized basebandtransmission bandwidth, so it can perform both equalization transmitter, where parallel branches are allowed to beand up-conversion. Mixers and integrators in the receiver (Rx) programmed independently. A similar argument applies to theseparate the channels and a Multi-Input Multi-Output (MIMO) MIMO DFE in the receiver.Decision Feedback Equalizer (DFE) in the Rx cancels post-cursor ISI and ICI (inter-channel interference). The entire Measured Resultssystem frequency response (channel bandwidths and center Fig. 4 shows the un-equalized and equalized eye diagramsfrequencies) scales as the frequency of the input clock. of the transmitter in 12GSym/Sec 2PAM and 4PAM modes asAMT is most suitable for transmission over tough channels, seen on an equivalent-time scope. Only transmit equalization

particularly those with notches in their frequency response, is employed to equalize the channel consisting of thewhile BB transmission is suitable for channels with smooth transmitter output capacitance including ESD, the package,frequency characteristics. This paper describes the board traces, and the cable to the scope. The impulse responseimplementation of a unified transmitter architecture that of the overall channel exhibits 14.5dB of attenuation at 6GHz.supports the AMT system of Fig. 1 as well as a variety of BB Measured SNR at the center of the eye is 21dB while analysismodes. Transmission mode is set simply by the way the 64 10- predicts that residual ISI only limits system to 25dB.bit equalizer coefficients in the system are programmed. Estimated wideband SNDR of the transmitter obtained

The transmitter test-chip consists of eight parallel PN through Least Squares Estimation methods [4] is 23dB, andsequence generators (2 per channel), 4 parallel 16-tap FIR accounts for the difference. In AMT mode, eye diagrams canfilters with 2-bit inputs and 10-bit coefficients generating four only be drawn after channels are separated through mixing and3GHz 8-bit outputs feeding an 8-bit 12GHz DAC with an integration in the receiver. Since an AMT receiver is notembedded 4-to-I serializer. The transmitter uses an off-chip available, we post process the sampled data at the output of12GHz clock. The internal design of the DAC is described in a the same cables in Matlab to generate the AMT eyes. Fig. 5companion paper. shows the AMT eye-diagrams obtained with this method at

total data rate of 18Gb/s. Again only transmit equalization isTransmitter Architecture employed.

Fig. 2 shows the top level block diagram of the transmitter This transmitter is a platform with sufficient flexibility toarchitecture. The pattern-generator block is synthesized using enable evaluation of different transmission algorithms ina standard cell library. The digital equalizer is designed using different environments. Table 1 summarizes the measuredan in-house semi-custom data-path flow [3], and is 2-way performance of the transmitter. Digital power includes theparallelized to use a 1.5GHz clock. 2-bit by 10-bit power of the pattern generator block, the equalizer, and the 4-multiplications are performed using 4:1 multiplexers and to-I serializer. Fig. 6 shows the chip micrograph.additions are performed using 3 stages of 4:2 compressors anda pseudo Kogge-Stone adder. A thermometer encoder encodes References

a pseudoK oggeStone ealizer. thermomepts e7uncbits before [1] A. Amirkhany, et al., "Analog Multi-Tone Signaling for High-Speedthe 3 MSB bits of the equalizer outputs to 7 unary bits before Backplane Electrical Links," GlobeCom, Nov 2006passing to the DAC. The digital equalizer has 6 levels of [2] B. Casper, er al., "A 20Gb/s Forwarded Clock Transceiver in 90nmpipelining. CMOS," ISSCC, pp. 90-91, Feb 2006

Fig. 2 also shows the clock distribution network of the [3] A. Amirkhany, et al., "Automated Design of a 3GHz, 24Gb/s Digitalof- Equalizer," submitted to Design Automation Conference 2007transmitter. A phase interpolator which is programmed of- [4] J. Savoj, et al. "A New Technique for Characterization of Digital to

line based on feedback from a sampler is placed between the Analog Converters in High-Speed Systems, DATE 2007

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2007 Symposium on VLSI Circuits Digest of Technical Papers 39