4 point bend testing

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High-Speed Bend Test Method and Failure Prediction for Drop Impact Reliability

Seah S.K.W., Wong E.H., Mai Y.W.*, Rajoo R., Lim C.T.**

Institute of Microelectronics, Singapore

*University of Sydney

**National University of Singapore

AbstractThe objective of this study is to obtain experimental

failure models governing solder joint failure during drop

impact testing of board assemblies. A high-speed bend tester

was developed to perform displacement-controlled bend tests

of board assemblies at the high flexing frequencies of drop

impact. These test frequencies and amplitudes are not

achievable by conventional universal testers. Experimental

data was obtained for various PCB strain amplitudes, flexural

frequencies, solder alloys and pad finishes. Results from the

high-speed bend tests are used to construct constant-

amplitude power law fatigue curves. Solder joint reliability is

found to be dependent on the test frequency, and therefore

strain rate. The experimental failure data from these high-speed bend tests are a required basis for a drop impact failure

criterion which can take into account frequency and

amplitude effects and which is general enough to be applied

to product level testing.

1. Introduction

1.1 Board level testing

Interest in the drop impact reliability of electronic

packaging is motivated by 1) the widespread use of portable

electronics; 2) miniaturization trends which can lead to

smaller and more fragile interconnections; and 3) the use of

lead-free solder, some of which have been shown to result in

fragile joints under drop impact conditions [1-4]. For several

years now, the standard in the electronic packaging industryfor board assembly drop impact testing has been the JESD22-

B111 standard [5] by JEDEC. This is a board-level test in

which a standard board assembly test vehicle is used, in

contrast to the product-level test in which actual products

such as mobile phones are tested. The board-level test is

shown in Fig. 1.

A significant number of experimental and numerical

simulation studies have been performed based on the JEDEC

board-level drop test [6-11]. Most of these studies involve: 1)

comparison studies of the impact performance for different

packaging parameters and different solder joint locations on

the JEDEC board [6-8]; and 2) finite element (FE) modeling

methodologies for simulating the JEDEC drop test [6-11].Failure predictions using the JEDEC drop test standard are

typically based on the number of drops to failure at a certain

reference load. An example of a reference load could be the

initial peak value of the interconnection stress waveform

obtained from drop impact modeling [6]. These failure

predictions rely on the assumption that in a comparison study

of drop performance, the PCBs of the test vehicles being

compared have the exactly the same construction and

boundary (mounting) conditions and therefore have the same

dynamic behavior. Only if the dynamic responses of the PCBs

are almost identical can the number of drops to failure be used

as a comparative measure of reliability.

Figure 1: Board-level drop test showing dynamic

flexing of PCB

Figure 2: FEA plot (magnified) of board assembly flexure

showing deformation of outermost solder joint

1.2 Failure criteria studies

There have also been several studies and proposals aimed

at developing failure criteria which are more fundamental and

less dependent on the PCB dimensions and mounting. Such

failure criteria can be general enough to be applicable to

product level-testing rather than certain board-level test

setups.

Zhu and Williams [12] proposed a plastic strain criterion.

In FE modeling, the plastic strain is a representation of the

accumulation of damage as the solder material deforms

plastically during the dynamic board flexing induced by drop

impact (Fig. 2). The accumulated plastic strain criterion is

attractive due to its convenience and simplicity, because it isable to convert complex loading sequences, such as the

damping behaviour of a flexural strain waveform, shown in

Fig. 3, into a single damage estimate.

Yeh et. al. [9] explored the use of accumulated plastic

strain in an FE drop impact study of the effects of kinematic

and isotropic hardening on solder material response. The

accumulated plastic strain results were used to explain the

relative performance of joints at different locations within a

single test vehicle. This relative comparison is similar to

relative comparisons using peak interconnection stresses [6].

PCB

outermost solder

joint

package

Shock table

Test

vehicle

1-4244-0152-6/06/$20.00 2006 IEEE 1003 2006 Electronic Components and Technology Conference


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Figure 3: Typical drop impact strain waveform

indicating rapid damping of strain oscillations

However, the FE studies using the concept of accumulated

plastic strain have yet to establish a quantitative link, beyond

relative comparisons, between plastic strain and failure. For

example, it has yet to be proven if two different loading

histories will result in failure when the same accumulated

plastic strain is reached. Figure 4 illustrates this issue.

Figure 4: Does failure occur at the same accumulated

plastic strain for different loading histories?

A very comprehensive test methodology and failure model

for impact testing was introduced by Varghese and Dasgupta

[13]. The proposed failure model is based on the calculation

of a damage estimate which takes into account local PCB

strain amplitudes, flexural modes and number of flexural

cycles. Although the Paris Law for crack propagation is

stated as the basis of the failure criterion, the assumptions

used in the analysis result in a basic power law (e.g. Coffin-Manson) equation. The power law fatigue constants were

deduced from impact experiments, based on several implicit

assumptions which are discussed later in this paper. The

complex dynamic responses of the PCB during impact were

handled through 1) wavelet analysis to decompose the

waveforms into their flexural mode components; and 2)

fatigue cycle counting methods, similar to those

recommended by fatigue test standards such as ASME

E1049-85 [14], for determining the equivalent numbers of

constant-amplitude cycles that can define the complex

waveforms. A weightage factor is also applied to various

modes to account for their different severities in causing joint

damage. The damage estimate proposed is therefore the total

amount of damage (be it crack initiation or growth)

contributed by the various modes and amplitudes present in

the drop impact waveforms. Lall et. al. [15] proposed a

similar failure criterion involving wavelet analysis and fatigue

cycle counting, but did not detail a treatment for various

flexural modes.

In view of the failure criteria described above, this paperintroduces high-speed bend testing methods for determining

the constant-amplitude fatigue life of board assemblies rather

than deducing them from drop impact tests. The results

obtained will be able to provide insight into these failure

criteria.

1.3 Drop testing vs bend testing

The use of bend tests instead of drop tests to study the

drop impact reliability of PCB assemblies is motivated by

earlier findings [16-17] showing that solder joint damage due

to direct inertial loading is minimal. The studies found that

the major cause of solder joint damage is the differential

flexing between PCB and package, as shown in the FE plot of

Fig. 2. In any case, the rapid motion of the PCB during adynamic bend test would already include some inertial

loading. The JEDEC standard can in fact be viewed as a bend

test method, although the bending is induced in an indirect

manner using a shock pulse.

The high frequencies and local accelerations of the PCB in

drop impact pose challenges to performing displacement-

controlled bend testing at drop impact strain rates. In a

JEDEC board-level drop test, the impact pulse applied to the

board assembly results in free vibration of the board at

frequencies which ranging from 200 to 300 Hz. In product-

level tests, the free vibration frequency of the PCB mounted

within its housing has been found to be even higher [17-18],

with frequencies of 400 to 500 Hz being common. Severalcases of higher flexural modes approach 1000 Hz. Given a

frequency of 300 Hz and displacement amplitude of 3 mm for

example, the accelerations at local points of the PCB can

exceed 1000 Gs. The fastest hydraulic universal testers can

achieve frequencies of at most 50 Hz at very low amplitudes.

Electromagnetic shakers are unable to achieve large enough

displacements and accelerations at the frequencies required.

Hence the need for a new test equipment and method for

performing high-speed bend testing.

The JEDEC board-level drop test is also costly in terms of

the time required to run the tests [7]. Several studies have

even reported performing up to a hundred drops to induce

failure. One of the reasons for having 15 packages on thestandard test vehicle is to generate several loading histories at

different locations on the board in a single drop test.

However, subsequent analysis is complicated as evident from

the FE modeling studies done to model the JEDEC drop test.

The ideal bend test is a four-point bend test on a single

package board, provided it can be performed fairly quickly.

Also, a displacement-controlled bend test and simple test

dimensions may be consistent enough to eliminate the need

for strain gauging.

-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

0 100 200 300 400 500

Time (ms)

Strain

(

)

0 0.02 0.04 0.06 0.08 0.1 0.12 0 0.02 0.04 0.06 0.08 0.1 0.12

0 0.02 0.04 0.06 0.08 0.1 0.120 0.02 0.04 0.06 0.08 0.1 0.12

Failure observed Predicted failure?

1004 2006 Electronic Components and Technology Conference


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Several novel bend test methods have been recently

proposed for drop impact reliability testing. Reiff and Bradley

[4] proposed a four-point bend test method in which a loading

anvil is dropped onto a board assembly test vehicle, thus

producing a bending pulse of a high frequency. The reported

results showed a single half-sine bending pulse instead of the

series of rapidly damping oscillations of drop impact. Their

bend test method is similar in concept to the use of a

pendulum impact test to induce bending in the PCB [13].However, the tests are velocity-controlled, and the flexing

frequencies are largely dependent on both the anvil mass as

the board stiffness. Chai et. al. [8] performed cyclic bend

testing at frequencies of up to 20 Hz at the strain amplitudes

of drop impact using a hydraulic universal tester. They

concluded that because of the large differences in the

frequencies (strain rates) of the cyclic tests and drop tests, no

correlation was observed between the bend test and drop

impact results.

Figure 5: High-speed bend tester with 4-point

bend test anvil

Figure 6: Strain waveforms generated by high-speed

bend tester using a sinusoidal cam

The high-speed bend tester presented in this paper

performs constant-amplitude displacement-controlled bendtesting at frequencies up to 500 Hz. Displacement control is

possible through the use of a cam driven by a rotary motor.

The cam enforces a particular displacement profile such as a

sinusoidal or versine pulse. A lever connected to the cam

follower controls the deflection amplitude. Fig. 5 shows the

bend tester with four-point bend test anvil while Fig. 6 shows

successive PCB strain waveforms generated by the tester.

Each sinusoidal pulse is a single bending cycle. This

equipment is estimated to achieve the equivalent bending

cycles of 100 drops in several minutes. The tester is also able

to perform single bending cycles at high speed, which is not

possible in a drop test owing to the oscillations of the board.

The relative performance of the various alloy/pad

combinations in the high-speed bend tests has been found to

be a match to their relative performance in JEDEC drop

testing.

2. Experimental procedure

The test vehicles used were single-component board

assemblies with solder mask defined (SMD) pads. The

packages used were not actual IC packages, but PCB

substrates with an identical pad finish to the boards, as shown

in Fig. 7. The reason for using such dummy packages is to

ensure that the joint qualities at the component and board

sides are the same, and that the correct interface is being

tested to failure. This is in view of several studies which have

reported failures occurring at the package side [11,19]. Given

similar board and component interfaces, fatigue failure should

occur at the board side, according to earlier modeling studies

performed [20].

Figure 7: Board assembly test vehicle

Figure 8: Pad layout showing corner joints and daisy

chain circuitry

The pad layout of the board is designed such that joint

failures will occur at only the four corner interconnections

shown in Fig. 8. This is because PCB bending results in the

largest stresses occurring on the outermost joints (Fig. 2).

These joints almost always fail first. FE modeling has shown

that the failure of a corner joint has a minimal effect on rest of

the corner joints. Also, due to symmetry, the stresses on thecorner joints are similar. The corner joints are essentially

independent of one another and four independent data points

can be obtained from one board sample. The board and

components have circuitry for daisy chain monitoring, also

seen in Fig. 8. In addition, each corner joint has its own

resistance monitoring circuit. This design will aid failure

analysis because the failure joint is known immediately, in

contrast to a full array BGA package where the daisy chains

may run through multiple solder joints. Failure is considered

to be 10which is more than enough to represent a complete

Loading anvil

Board assembly

-2000

-1000

0

1000

2000

0 100 200 300

Time (ms)

PCBs

train(

)

PCB substrate

as component

Corner pad



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500

1000

1500

2000

2500

3000

3500

0 200 400 600 800

Cycles to failure (N)

PCBs

train

()

PbSn/ENIG 40 HzPbSn/ENIG 140HzPbSn/ENIG 250HzSnAg/ENIG 40HzSnAg/ENIG 250HzSnAgCu/ENIG 40Hz

opening of a solder joint. The tracking of crack progression in

each corner solder joint is also possible and is described in

another study [21]. Other details on the board and component

dimensions are shown below:

Board/component dimensions

Pitch: 1 mm

Solder ball diameter: 0.3 mm

SMD pad diameter: 0.25 mm

Board thickness: 0.8 mm

Component thickness: 0.8 mm

I/O count: 40 (refer to Fig. 8 for exact design)

To obtain data for constructing the power law fatigue

curves, a series of high-speed four-point bend tests were

performed for various frequencies, strain amplitudes and

alloy/pad combinations. The following variables were used:

Bend test variables

Bending frequencies: 40 Hz, 140 Hz, 250 Hz

PCB strains: Ranging from 1000 to3000

Solder alloys: PbSn, SnAg, SnAgCu

Pad finish: ENIG, Organic solder preservative (OSP)

The four-point bend test setup had an inner span of 30 mm

and an outer span of 90 mm, as shown in Fig. 9. A strain

gauge was mounted at a specific location on the PCB adjacent

to the package, as shown in Fig. 9. This will measure the

reference strain which may be used in FE modeling. Using the

high-speed bend tests, the number of cycles to failure for a

specific frequency and amplitude is obtained for each corner

solder joint. The failure curves of PCB strain vs. cycles-to-

failure N (-N curves) were then plotted from the data

collected.

Figure 9: Four-point high-speed bend test setup

3. Experimental results

Figures 10 and 11 show the -N curves for ENIG and OSP

pad finish respectively. Several trends may be seen. The lead-

free solders fail in significantly fewer cycles than the PbSn

solders on both ENIG and OSP pads. A decrease in reliability

with frequency is seen for PbSn on both finishes and

SnAg/OSP, but not for SnAg/ENIG. Tests were also done on

two batches of PbSn/OSP boards to determine the effect of

different processing parameters. Batch 1 can be seen to have

a better reliability than Batch 2 of the PbSn/OSP boards.

More tests will be done in the future to obtain statistically

robust experimental curves. To obtain failure criteria based on

solder materials, the PCB strain will also need to be

converted to solder strain in FE modeling using accurate

dynamic materials properties.

Figure 10: -N curves for ENIG pad finish with various

solder alloys and test frequencies

Figure 11: -N curves for OSP pad finish with various

solder alloys and test frequencies

Figure 12: Crack through bulk solder material transitioning to

intermetallic failure (SnAg/ENIG, 250Hz, 1500strain)

PCB

ComponentStrain

gauge Sliding support

30 mm

90 mm

1500

1700

1900

2100

2300

2500

2700

2900

3100

3300

3500

0 200 400 600 800

Cycles to failure (N)

PCBs

train

()

PbSn/OSP - Batch 1 - 40HzPbSn/OSP - Batch 1 - 140HzPbSn/OSP - Batch 2 - 40HzPbSn/OSP - Batch 2 - 140HzSnAg/OSP 40HzSnAg/OSP 140HzSAC/OSP 40Hz



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The high-bend tests produce similar failure modes as drop

impact, with various mixes of bulk and intermetallic failure.

Figures 12 and 13 show the cross-sections of two joints from

the same board with different failure modes.

Figure 13: Almost completely intermetallic failure

(SnAg/ENIG, 250Hz, 1500)

4. Discussion on failure criteria

The damage estimate methodologies [13,15] which

deduce the power law fatigue constants from drop testexperiments depend on two important assumptions:

1) A linear damage rule (also known as Miners rule) [22] is

assumed when calculating the damage contributed by the

various amplitudes. For example, given that the fatigue life

at a certain strain amplitude S is N cycles, each cycle at

amplitude S will consume 1/N of the fatigue life of the

joint. In a load history consisting of various amplitudes, it

is then assumed that the same linear damage rule is applied

for all amplitudes.

2) The effect of load sequence is ignored. For example, it is

assumed that the damage estimate is the same whether

testing is conducted at A) strain S1for N1cycles followed

by strain S2 for N2 cycles or; B) strain S2 for N2 cyclesfollowed by strain S1 for N1cycles. This assumption may

not be a critical issue given that most board-level tests

consist of a series of similar drops. It may be an issue if the

failure criteria is to have a more general application

beyond specific board level test setups.

These studies also reported that validation of the

calculated damage estimates was performed by conducting

impact tests at different impact orientations or by validating

different board locations other than those used to derive the

power law constants. Based on the reported information, it is

uncertain if the strain waveforms of the validation tests were

sufficiently dissimilar to be able to independently verify

whether the above assumptions hold true. If the validationwaveforms are too similar to the waveforms used to derive the

constants, the damage criteria might be applicable only to that

specific type of waveform and the specific test setup. The

failure data obtained from high-speed bend tests will be able

to verify if the above assumptions are reasonable.

If accumulated plastic strain obtained from modeling is to

be used as an accurate damage estimate, the material

characteristics of the solder would have to be such that the

failure criterion from modeling predicts the failure data of the

experimental -N curves. For example, a purely kinematic

hardening plastic model will not work because the implied

linear relation between accumulated damage and number of

plastic strain cycles results in a power law fatigue exponent of

1. Even after conversion of solder plastic strain to PCB strain,

the exponent for a kinematic model will not reach the

exponent values of the experimental -N curves which range

from 0.12 to 0.75 (Figs. 10 and 11). Also, if the plastic strain

criterion is to have general applications beyond board-level

drop, the material models used would have to incorporate aproper damage rule (linear or non-linear) and the effect of

amplitude sequence (if any).

It should noted that the -N curves of Figs. 10 and 11 do

not distinguish between the stages of failure, be it crack

initiation or crack propagation. For example, a high strain

amplitude may result in immediate crack propagation while a

low strain amplitude may have a relatively much longer

initiation phase, but both are used to construct the same -N

curve. The -N curves also do not distinguish between failure

modes, such as bulk failure or intermetallic failure. There is

still uncertainty as to whether basic power law fatigue curves

can be applied across all failure phenomena encountered in

drop impact. The fatigue failure in drop impact is much closerto very low cycle fatigue (VLCF) than low cycle fatigue

(LCF). A model for solder based purely on strain range might

not work in the VLCF regime.

The failure data in this paper is presented as PCB strain

vs number of cycles to failure N. A proper failure criteria

would ideally be materials-based. This will involve

converting PCB strain to solder strain using accurate dynamic

solder material properties and taking into account the details

of the solder joint structure.

The -N failure curves only represent constant-amplitude

failure data. Future work in this study will focus on 1) how

damage is accumulated in a complex drop impact response; 2)

the effect of sequence; and 3) the combined effect of variousfrequencies.

5. Future challenges

Much work has yet to be done to develop a practical and

sufficiently accurate failure criterion which can have general

applications other than board-level impact tests. Among the

issues to be resolved are:

1) Determining the damage rule to use in fatigue damage

estimates.

2) Assessing the effect of amplitude sequence in fatigue

damage.

3) Obtaining a full range of dynamic solder material

properties since a solder joint in drop impact can

experience a wide range of strain rates.

4) Determining the effect of failure mode and crack

progression on the damage estimate.

5) Confirming or determining the fatigue model to use in the

VLCF regime.

6. Conclusions

A high-speed bend test method has been introduced for

more controllable and effective testing of drop impact

reliability. The test method is being used to obtain failure

criteria for drop impact.



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The development of a practical failure criteria for drop

impact is a very challenging but valuable area of study.

Various groups have proposed several interesting drop impact

failure criteria and test methodologies. The current methods

for failure prediction in drop impact are:

1) Number of drops to failure in the JEDEC drop test, where

comparisons of drops-to-failure are heavily dependent on

the test setup.

2) An accumulated plastic strain failure criterion.3) Damage estimate failure criteria based on drop impact

waveforms and power law fatigue equations.

7. References

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Reflow Profiles on the Board Level Drop Reliability of

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Tsan-Hsien Chen, Correlation Between Package-level

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