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SET-1RRCode No: RR410506
B.Tech IV Year I Semester Examinations, December-2011 FAULT TOLERANT SYSTEMS
(COMPUTER SCIENCE ENGINEERING) Time: 3 hours Max. Marks: 80
Answer any five questions All questions carry equal marks
--- 1. Explain different faults with an examples. [16]
2. Explain Random, transition and signature Analysis testing methods with examples. [16]
3. Explain with an example Practical fault tolerant system. [16]
4. Explain self Checking sequential machine and partially self checking circuit. [16]
5. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16]
6. Explain totally self-check PLA design. [16]
7. Explain testability, controllability and observability. [16]
8. Explain Scan Path technique and level sensitive scan design, built in self test. [16]
******
SET-2RRCode No: RR410506
B.Tech IV Year I Semester Examinations, December-2011 FAULT TOLERANT SYSTEMS
(COMPUTER SCIENCE ENGINEERING) Time: 3 hours Max. Marks: 80
Answer any five questions All questions carry equal marks
--- 1. Explain with an example Practical fault tolerant system. [16]
2. Explain self Checking sequential machine and partially self checking circuit. [16]
3. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16]
4. Explain totally self-check PLA design. [16]
5. Explain testability, controllability and observability. [16]
6. Explain Scan Path technique and level sensitive scan design, built in self test. [16]
7. Explain different faults with an examples. [16]
8. Explain Random, transition and signature Analysis testing methods with examples. [16]
******
SET-3RRCode No: RR410506
B.Tech IV Year I Semester Examinations, December-2011 FAULT TOLERANT SYSTEMS
(COMPUTER SCIENCE ENGINEERING) Time: 3 hours Max. Marks: 80
Answer any five questions All questions carry equal marks
--- 1. Explain fail safe design of a sequential circuit using partition Theory and Berger
codes. [16] 2. Explain totally self-check PLA design. [16]
3. Explain testability, controllability and observability. [16]
4. Explain Scan Path technique and level sensitive scan design, built in self test. [16]
5. Explain different faults with an examples. [16]
6. Explain Random, transition and signature Analysis testing methods with examples. [16]
7. Explain with an example Practical fault tolerant system. [16]
8. Explain self Checking sequential machine and partially self checking circuit. [16]
******
SET-4RRCode No: RR410506
B.Tech IV Year I Semester Examinations, December-2011 FAULT TOLERANT SYSTEMS
(COMPUTER SCIENCE ENGINEERING) Time: 3 hours Max. Marks: 80
Answer any five questions All questions carry equal marks
--- 1. Explain testability, controllability and observability. [16]
2. Explain Scan Path technique and level sensitive scan design, built in self test. [16]
3. Explain different faults with an examples. [16]
4. Explain Random, transition and signature Analysis testing methods with examples. [16]
5. Explain with an example Practical fault tolerant system. [16]
6. Explain self Checking sequential machine and partially self checking circuit. [16]
7. Explain fail safe design of a sequential circuit using partition Theory and Berger codes. [16]
8. Explain totally self-check PLA design. [16]
******