4706－ds00－r bcm4706 advance data sheet nda clear

4/12/2011 DXKOG

Advance Data Sheet

BCM4706

4706-DS00-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 June 02, 2010

Communications Processor with Network Acceleration Hardware

Figure 1: Functional Block Diagram

GENERAL DESCRIPTION FEATURES

The Broadcom® BCM4706 processor is a communications device targeted for wireless access points and routers.

At the center of the device is a high-performance 600 MHz MIPS32® 74K™ core with a 32 KB four-way set associative instruction cache, a 32 KB four-way set associative data cache, and a 64-entry translation lookaside buffer (TLB). Enhanced CPU memory subsystem architecture provides increased system performance. The device uses state-of-the-art, low power, and low leakage 65 nm LP technology.

The BCM4706 integrates several peripheral interfaces including Gigabit Ethernet MACs, USB 2.0, PCI Express®, serial and parallel Flash, DDR memory, and audio/voice TDM subsystem. Various common I/O controllers are also integrated. These I/O controllers include JTAG, UART, MDIO, GPIO, and SPI.

• Advanced MIPS32 74K Core- 32 KB I-cache, 32 KB D-cache- BCM4706 CPU runs at 600 MHz/1200 DMIPs

• On-chip SoC – RAM™ provides low latency read/write access to improve system performance

• Advanced Gigabit Ethernet MAC • MII/RGMII/SGMII interface• Supports external GbE switch (such as

BCM53115/BCM53125)• Supports external 10/100 switch (such as

BCM5325E)• One USB 2.0 host port• 16-bit/32-bit DDR2 300 MHz memory interface• Supports serial or parallel Flash• Dual PCI Express interface compliant with PCI

Express base specification revision 1.1• UART/MDIO/SPI/JTAG interface, up to 16 GPIOs• I8S audio/TDM voice interfaces• BCM4706 package: 23 mm × 23 mm, 484-pin

PBGA

SerDes

PCle1x1

SerDes

PCle1x1

USB 2.0Host

USB Phy GMAC

2.5 Gbps2.5 Gbps 480 Mbps

RGMIIor MII SGMII/

SerDes

Parser/FP

DMA

SerDes

GMAC

Parser/FP

DMA

MIPS32 Core(600 MHz)

I-Cache32 KB

D-Cache32 KB

EJTAG

SoC-RAM(512 KB)

CPU Local Bus

System Bus System Bus

DDR2Memory Controller

TDM

I8S/TDM

2 VOIP Channelsor

8 Audio Channels

GPIOSerialFlash

ParallelFlash8b/16b

SPI I2CUART/I2C

UART

Peripheral Interface

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Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/

or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,

pollution control, hazardous substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES,

EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.

Broadcom Corporation5300 California Avenue

Irvine, CA 92617

© 2010 by Broadcom CorporationAll rights reserved

Printed in the U.S.A.

Revision History

Revision Date Change Description

4706-DS00-R 06/02/10 Initial release

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Table of Contents BCM4706 Advance Data Sheet

BROADCOM June 02, 2010 • 4706-DS00-R

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Table of Contents

Section 1: Functional Description ...................................................................................... 9

Overview.........................................................................................................................................................9

MIPS Core .......................................................................................................................................................9

Reset ...............................................................................................................................................................9

Crystal Oscillator and Clock Generator ..........................................................................................................9

DDR2 SDRAM Interface ................................................................................................................................10

USB 2.0 Host Controllers ..............................................................................................................................10

PCI Express Interface ....................................................................................................................................10

Transaction Layer Interface ...................................................................................................................11

Data Link Layer.......................................................................................................................................11

Physical Layer.........................................................................................................................................12

Logical Subblock.....................................................................................................................................12

Scrambler/Descrambler.........................................................................................................................12

8B/10B Encoder/Decoder ......................................................................................................................12

Elastic FIFO.............................................................................................................................................12

Electrical Subblock .................................................................................................................................13

Configuration Space...............................................................................................................................13

10/100/1000 Ethernet MAC Controller .......................................................................................................13

Flash Interface ..............................................................................................................................................13

SPI/UART/GPIO Interface.............................................................................................................................14

I8S/TDM Interface ........................................................................................................................................14

Section 2: Hardware Signal Descriptions.......................................................................... 15

BCM4706 Pin Tables .....................................................................................................................................21

BCM4706 Ballmap ........................................................................................................................................27

Section 3: Electrical Characteristics.................................................................................. 28

Absolute Maximum Ratings .........................................................................................................................28

Recommended Operating Conditions and DC Characteristics ....................................................................29

Core and I/O Power Sequencing Requirements ..........................................................................................30

DDR2 SDRAM Memory Interface DC Characteristics ..................................................................................31

USB Host Interface DC Characteristics .........................................................................................................31

PCIe DC Characteristics.................................................................................................................................33

1G SGMII/SerDes Port Signals......................................................................................................................33

Standard 3.3V Signals ...................................................................................................................................34

Standard 2.5V Signals ...................................................................................................................................34

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Table of Contents


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BCM4706 Advance Data Sheet

XTAL Oscillator Interface ..............................................................................................................................34

Section 4: Timing Characteristics ..................................................................................... 35

Reset and Clock Timing ................................................................................................................................35

Parallel Flash Timing.....................................................................................................................................36

Parallel Flash READ Timing.....................................................................................................................36

Parallel Flash WRITE Timing...................................................................................................................37

Serial Flash Timing (ST Micro-compatible Device) ......................................................................................38

DDR2 SDRAM AC Timing Characteristics .....................................................................................................39

USB Host Interface AC Timing Characteristics .............................................................................................40

PCIe Interface Timing ...................................................................................................................................41

PCIe_REFCLKP/N Timing ........................................................................................................................41

MII Interface Timing .....................................................................................................................................43

MII Input Timing.....................................................................................................................................43

MII Output Timing..................................................................................................................................44

RGMII Interface Timing ................................................................................................................................45

RGMII Output Timing (Normal Mode) ...................................................................................................45

RGMII Output Timing (Delayed Mode) ..................................................................................................46

RGMII Input Timing (Normal Mode) ......................................................................................................47

RGMII Input Timing (Delayed Mode) .....................................................................................................48

SGMII/SerDes Serial Interface......................................................................................................................49

Serial Interface Output Timing...............................................................................................................49

Serial Interface Input Timing..................................................................................................................50

I8S/TDM Audio/Video AC Specification ......................................................................................................51

JTAG Interface ..............................................................................................................................................52

MDC/MDIO Master Interface ......................................................................................................................53

SPI Master Interface .....................................................................................................................................54

Timing Parameters for CPHA=0 .............................................................................................................54

Timing Parameters for CPHA=1 .............................................................................................................55

Section 5: Thermal Specifications .................................................................................... 56

BCM4706.......................................................................................................................................................56

BCM4706 Thermal Specifications Without External Heatsink at 70°C ..................................................56

BCM4706 Thermal Specifications with External Heatsink at 70°C.........................................................57

BCM4706 Thermal Specifications Without External Heatsink at 85°C ..................................................58

BCM4706 Thermal Specifications with External Heatsink at 85°C.........................................................59

Section 6: Mechanical Information.................................................................................. 60

BCM4706.......................................................................................................................................................60

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Table of Contents BCM4706 Advance Data Sheet


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Section 7: Ordering Information ...................................................................................... 61

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List of Figures BCM4706 Advance Data Sheet


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List of FiguresFigure 1: Functional Block Diagram....................................................................................................................1

Figure 2: PCI Express Layer Model ...................................................................................................................11

Figure 3: BCM4706 Ballmap—Top View...........................................................................................................27

Figure 4: Power Supply Sequencing .................................................................................................................30

Figure 5: Reset and Clock Timing......................................................................................................................35

Figure 6: Parallel Flash READ Timing Diagram..................................................................................................36

Figure 7: Parallel Flash WRITE Timing Diagram ................................................................................................37

Figure 8: Serial Flash Timing Diagram ..............................................................................................................38

Figure 9: PCIe_REFCLKP/N Timing ....................................................................................................................41

Figure 10: PCIe[1:0]_RDP/N Timing..................................................................................................................41

Figure 11: PCIe[1:0]_TDP/N Timing..................................................................................................................42

Figure 12: MII Input Timing ..............................................................................................................................43

Figure 13: MII Output Timing ...........................................................................................................................44

Figure 14: RGMII Output Timing (Normal Mode).............................................................................................45

Figure 15: RGMII Output Timing (Delayed Mode)............................................................................................46

Figure 16: RGMII Input Timing (Normal Mode)................................................................................................47

Figure 17: RGMII Input Timing (Delayed Mode)...............................................................................................48

Figure 18: Serial Interface Output Timing ........................................................................................................49

Figure 19: Serial Interface Input Timing ...........................................................................................................50

Figure 20: IXS Transmitter Timing ....................................................................................................................51

Figure 21: IXS Receiver Timing .........................................................................................................................51

Figure 22: JTAG Interface .................................................................................................................................52

Figure 23: MDC/MDIO Master Interface..........................................................................................................53

Figure 24: SPI Master Interface: Timing Parameters for CPHA=0 ....................................................................54

Figure 25: SPI Master Interface: Timing Parameters for CPHA=1 ....................................................................55

Figure 26: BCM4706 Mechanical Information .................................................................................................60

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List of Tables BCM4706 Advance Data Sheet


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List of TablesTable 1: Hardware Signals ................................................................................................................................15

Table 2: BCM4706 Sorted by Pin Location .......................................................................................................21

Table 3: BCM4706 Sorted by Signal Name .......................................................................................................24

Table 4: Absolute Maximum Ratings................................................................................................................28

Table 5: Recommended Operating Conditions ................................................................................................29

Table 6: Total Power and Supply Current.........................................................................................................29

Table 7: DC Characteristics for DDR2 SDRAM Interface...................................................................................31

Table 8: USB Host Interface DC Characteristics................................................................................................31

Table 9: USB 1.1 Electrical and Timing Parameters..........................................................................................32

Table 10: PCIe DC Characteristics.....................................................................................................................33

Table 11: 1G SGMII/SerDes Port Signals ..........................................................................................................33

Table 12: Standard 3.3V Signals .......................................................................................................................34

Table 13: Standard 2.5V Signals .......................................................................................................................34

Table 14: XTAL Oscillator Interface ..................................................................................................................34

Table 15: Reset and Clock Timing.....................................................................................................................35

Table 16: Parallel Flash READ Timing ...............................................................................................................36

Table 17: Parallel Flash WRITE Timing..............................................................................................................37

Table 18: Serial Flash Timing ............................................................................................................................38

Table 19: AC Characteristics for DDR SDRAM Interface ...................................................................................39

Table 20: USB 2.0 Host Interfaces Timing Parameters .....................................................................................40

Table 21: USB 1.1 Timing Parameters ..............................................................................................................40

Table 22: PCIe_REFCLKP/N Timing ...................................................................................................................41

Table 23: PCIe[1:0]_RDP/N Timing...................................................................................................................42

Table 24: PCIe[1:0]_TDP/N Timing ...................................................................................................................42

Table 25: MII Input Timing ...............................................................................................................................43

Table 26: MII Output Timing ............................................................................................................................44

Table 27: RGMII Output Timing (Normal Mode) ..............................................................................................45

Table 28: RGMII Output Timing (Delayed Mode).............................................................................................46

Table 29: RGMII Input Timing (Normal Mode) .................................................................................................47

Table 30: RGMII Input Timing (Delayed Mode)................................................................................................48

Table 31: Serial Interface Output Timing .........................................................................................................49

Table 32: Serial Interface Input Timing ............................................................................................................50

Table 33: IXS Receiver Timing...........................................................................................................................51

Table 34: JTAG Interface...................................................................................................................................52

Table 35: MDC/MDIO Master Interface ...........................................................................................................53

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List of Tables BCM4706 Advance Data Sheet


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Table 36: SPI Master Interface .........................................................................................................................54

Table 37: Timing Parameters for CPHA=1 ........................................................................................................55

Table 38: Package for 2s2p Board, TA = 70°C, P = 2.7W from Simulation..............................................................................................56

Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70°C .............................................56

Table 40: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 70°C, P = 2.7W from Simulation..............................................................................................57

Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70°C............................57

Table 42: Package for 2s2p Board, TA = 85° C, P = 2.7 W from Simulation ............................................................................................58

Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85°C .............................................58

Table 44: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 85°C, P = 2.7W from Simulation..............................................................................................59

Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85°C............................59

Table 46: Ordering Information .......................................................................................................................61

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Functional Description


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Section 1: Functional Description

OverviewThe Broadcom® BCM4706 is a family of processors optimized for power and cost without compromising performance. Integrating a high-performance 600 MHz MIPS32® 74KTM core with a 32 KB four-way set associative instruction cache, a 32 KB four-way set associative data cache, and a 64-entry TLB, the BCM4706 offers significant performance improvements in both transfer rates and CPU utilization.

Flexible support for a variety of system bus interfaces is provided including Gigabit Ethernet MACs, an audio/voice TDM unit, a USB 2.0 host port, PCI Express® (X1 lane), 16-bit/32-bit DDR2 300 MHz memory control, serial Flash port, and 16-bit parallel Flash port. There are 16 GPIOs on the BCM4706 processor. All inputs can be used to generate processor interrupts.

MIPS CoreThe chip integrates an advanced 600 MHz MIPS32 74K core with a 32 KB four-way set associative I-cache and a 32 KB four-way set associative D-Cache. The MIPS32 74K core has an integrated 32 × 32-bit single-cycle multiply/accumulate block running at CPU core speed, providing additional signal or media processing capabilities. The integrated MMU with a 64-entry TLB block is included, allowing support for common multithreaded real-time operating systems (RTOS) such as the standard Linux® distribution.

ResetA power-on or hard reset is initiated by an active low reset pulse on the RESET_N Schmitt-triggered input pin. The reset signal has a minimum required low pulse duration to guarantee that a sufficiently long reset is applied to all internal circuits, including integrated PHYs (see Table 15: “Reset and Clock Timing,” on page 35). The initialization process loads all pin configurable modes, resets all internal processes, and puts the device in the idle state. During initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be stable.

Crystal Oscillator and Clock GeneratorA typical BCM4706-based platform requires only a single crystal to clock the entire device. Several internal PLLs are driven by the oscillator and generate the various clocks, including the clock for the 10/100/1000 MAC core and the MIPS32 74K, DDR2 SDRAM, PCIe, UART, and USB 2.0 host controllers.

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DDR2 SDRAM Interface


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DDR2 SDRAM InterfaceThe integrated DDR2 controller has on-chip serial termination resistors on the address, data and control signals, except DDR clocks. The differential clock pair needs external serial termination resistors. Additionally, VREF pin must be set to half of the DDR_OVDD_1P8 voltage. This can be accomplished by using two equal value resistors to divide the DDR_OVDD_1P8 voltage.

USB 2.0 Host ControllersThe BCM4706 integrates a USB 2.0 host controller that supports high-speed USB 2.0 ports. It is also backward compatible with full-speed and low-speed USB 1.1 devices. Each host port has a dedicated overcurrent input to notify the OS or driver to take appropriate action. Individual port power control is also available.

PCI Express InterfaceThe PCI Express (PCIe) core on the BCM4706 is a high performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification v1.1. This core contains all the necessary blocks, including logical and electrical functional subblocks, to perform PCIe functionality and maintain high-speed links using existing PCI system configuration software implementations without modification.

The PCIe core is organized in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 2. A configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and reception of System Management Messages by communicating with PCIe layers.

Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and BCM4706 device. The transmit side processes outbound packets while the receive side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to indicate the packet type and any other optional fields.

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PCI Express Interface


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Figure 2: PCI Express Layer Model

Transaction Layer InterfaceThe PCIe core employs a packet-based protocol to transfer data between the host and BCM4706 device, delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer, which is primarily responsible for assembly and disassembly of transaction layer packets (TLPs). TLP structure contains header, data payload, and end-to-end CRC (ECRC) fields, which are used to communicate transactions, such as read and write requests and other events.

A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.

Data Link LayerThe data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is to provide a reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services provided by the data link layer include data exchange, initialization, error detection and correction, and retry services.

Data link layer packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including TLP acknowledgement, power management, and flow control.

TransactionLayer

Data LinkLayer

Logical Subblock

Electrical Subblock

Physical Layer

TransactionLayer

Data LinkLayer

Logical Subblock

Electrical Subblock

Physical Layer

HW/SW Interface HW/SW Interface

TX RX TX RX

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PCI Express Interface


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Physical LayerThe physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks. Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between the host and PCIe device. The transmit section prepares outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received information before passing it to the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a specific format.

Logical SubblockThe logical subblock’s primary functions are to prepare outgoing data from the data link layer for transmission and identify received data before passing it to the data link layer.

Scrambler/DescramblerThis PCIe PHY component generates a pseudo-random sequence for scrambling of data bytes and the idle sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and recovery for testing and debugging purposes.

8B/10B Encoder/DecoderThe PCIe core on the BCM4706 uses an 8b/10b encoder/decoder scheme to provide DC balancing, clock synchronization and data recovery, and error detection. The transmission code is specified in ANSI X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.

Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit Symbol, which is then transmitted serially. Special Symbols are used for link management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.

Elastic FIFOAn elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock domain and the receive clock domain, with worst case clock frequency specified at 600 ppm tolerance. As a result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique reduces the elastic FIFO size and the average receiver latency by half.

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10/100/1000 Ethernet MAC Controller


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Electrical SubblockThe high-speed signals utilize the common mode logic (CML) signaling interface with on-chip termination and deemphasis for best in class signal integrity. A deemphasis technique is employed to reduce the effects of intersymbol interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to receive data with an acceptable bit-error rate (BER).

To further minimize ISI, multiple bits of the same polarity that are output in succession are deemphasized. Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for maximum interoperability while minimizing the complexity of controlling the deemphasis values. The high-speed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF.

Configuration SpaceThe PCIe function in the BCM4706 implements the configuration space as defined in the PCI Express Base Specification v1.1.

10/100/1000 Ethernet MAC ControllerThe BCM4706 integrates a high performance yet flexible Ethernet MAC controller. GMAC port 0 of the BCM4706 supports the following interfaces through strap pin settings:

• RGMII: 10/100/1000 Mbps mode

• MII: 10/100 Mbps mode

The BCM4706 supports a second GMAC with SGMII interface in 10/100/1000 Mbps mode. These interfaces can work with a wide variety of Ethernet PHYs and switches.

In RGMII mode, the bus signals operate at 2.5V, with the exception that the MDIO and MDC pins operate at 3.3V. All the Ethernet MAC controller output pins have built-in series termination so external termination resistors are not required.

Flash InterfaceAn on-chip, 16-bit external bus interface (EBI) provides the following connectivity options:

• 16-bit NOR or NAND flash memory. BCM4706 supports up to 256 MB.

• Serial Flash (ST-compatible four-pin SPI interface)

The BCM4706 has two Flash chip select pins so it can support up to two Flash devices in any of the combinations in the following list:

• One parallel Flash

• One serial Flash

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SPI/UART/GPIO Interface


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• Two parallel Flash

• Two serial Flash

• One serial Flash + one parallel Flash (either the serial Flash or parallel Flash can be the boot device)

• One serial Flash + NAND Flash (serial Flash must be the boot device to set up the on-chip NAND Flash controller before it is accessed)

The BCM4706 has 16-bit parallel Flash data pins and supports either an 8-bit or 16-bit parallel Flash through strap-pin settings when the parallel Flash is the boot device. However, byte-mode configuration should not be used when 16-bit parallel Flash is used. When the BCM4706 is used in a configuration with two parallel Flash devices, mixing of 8-bit and 16-bit parallel Flash memory is not supported.

SPI/UART/GPIO InterfaceThe BCM4706 supports one dedicated two-wire UART interface (UART_TX and UART_RX pins). It can support one additional UART interface by sharing GPIO pins. The BCM4706 also supports one SPI master. The pin sharing is enabled by software with the following configuration:

• GPIO[3:0] and GPIO[9:8] can be configured as the SPI master interface.

• GPIO[7:6] can be configured as the UART interface.

There are 16 3.3V GPIO pins on the BCM4706. These pins can be used to connect to various external devices. Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.

I8S/TDM InterfaceThe BCM4706 integrates a Voice/Audio TDM subsystem core that provides support for up to two full-duplex voice channel conversations or up to eight audio channels for stereo or multichannel music/sound acquisition or playback applications. The BCM4706 supports various flavors of TDM interface operations to work with external A/D or D/A devices. The following list contains the possible channel combinations:

• Audio/voice output only: one three-wire I8S/TDM interface

• Audio/voice input only: one three-wire I8S/TDM interface

• Full-duplex audio/voice: two three-wire I8S/TDM interfaces or one four-wire TDM interface

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Hardware Signal Descriptions


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Section 2: Hardware Signal Descriptions

The section describes the BCM4706 hardware signals and uses the following conventions:

• I = Input signal

• O = Output signal

• I/O = Bidirectional signal

• IPD = Input Signal with internal pull-down

• IPU = Input Signal with internal pull-up

Table 1: Hardware Signals

Pin Names I/O V Pin Description

DDR SDRAM Interface

DDR_SDRAM_ADDR[14:0] O 1.8V DDR2 address bus

DDR_SDRAM_BA[2:0] O 1.8V DDR2 bank address

DDR_SDRAM_CAS O 1.8V DDR2 column address select

DDR_SDRAM_CKE O 1.8V DDR2 clock enable

DDR_SDRAM_CS_N O 1.8V DDR2 chip select

DDR_SDRAM_ODT O 1.8V DDR2 on-die termination

DDR_SDRAM_RAS O 1.8V DDR2 row address select

DDR_SDRAM_REF I 0.9V 0.9V (DDR_OVDD_1P8 divided by two) DDR2 reference voltage

DDR_SDRAM_WE O 1.8V DDR2 write enable

DDR_SDRAM_ZQ I/O – Output impedance calibration. This pin should be attached to a 240Ω resister to VSS for impedance calibration.

DDR_SDRAM_CK0P/N O 1.8V DDR2 differential clock pair for byte lane 1 and 0

DDR_SDRAM_CK2P/N O 1.8V DDR2 differential clock pair for byte lane 3 and 2

DDR_SDRAM_DM[3:0] O 1.8V DDR2 data mask

DDR_SDRAM_DQSP[3:0] I/O 1.8V DDR2 differential pair data strobe for byte lane 3 to 0

DDR_SDRAM_DQSN[3:0] I/O 1.8V DDR2 differential pair data strobe for byte lane 3 to 0

DDR_SDRAM_DQ[31:0] I/O 1.8V DDR2 data bus

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Parallel Flash Interface/Strap PinsNote: Strap pin values are latched during reset, after reset the pin behaves as a Flash address pin.

FLASH_ADDR[26:0] IPD/O 3.3V When connecting to NAND Flash:• FLASH_ADDR0: NAND Flash CLE (command latch enable)

output.• FLASH_ADDR1: NAND Flash ALE (address latch enable)

output.• FLASH_ADDR2: NAND Flash WP# (write protect) output

(active low).• FLASH_ADDR21: NAND Flash R/B# (ready/not busy) input

with internal pullup.• FLASH_ADDR[4:20], [22:25]: Unused.

FLASH_ADDR6/MIPS_EJTAG_MODE

IPD/O 3.3V MIPS EJTAG mode enable:• 0: General JTAG interface• 1: MIPS EJTAG interface (connect to ICE)

FLASH_ADDR8/GMAC_VSEL

IPD/O 3.3V Ethernet interface voltage level select:• Set this pin low to configure port 0 GMAC interface to

operate in 2.5V RGMII.• Set this pin high for 3.3V MII.

FLASH_ADDR12/PCIe_DIS IPD/O 3.3V PCIe port 1 disable:• 0: PCIe port 1 is enabled.• 1: PCIe port 1 is disabled for power saving.

FLASH_ADDR16/PCIe_REFCLKSEL

IPD/O 3.3V PCIe SerDes reference clock select:• 0: Use internal PLL to generate 100 MHz clock.• 1: Use the external 100 MHz differential clock source,

through PCIe_REFCLKP/N pins.

FLASH_ADDR17/BOOT_FLASH_TYPE

IPD/O 3.3V Boot Flash type, depending on SFLASH_BOOT setting, this pin specifies the parallel Flash or serial Flash boot device type:If (SFLASH_BOOT == 0):• 0: 8-bit parallel Flash• 1: 16-bit parallel FlashIf (SFLASH_BOOT == 1):• 0: ST-compatible serial Flash• 1: Atmel® serial Flash

FLASH_ADDR18/SFLASH_BOOT

IPD/O 3.3V Specifies using parallel Flash or serial Flash as the boot device:• 0: Boot device is a parallel Flash• 1: Boot device is a serial Flash

FLASH_ADDR19/MIPS_ENDIAN

IPD/O 3.3V MIPS endian setting:• 0: Little endian• 1: Big endian

Table 1: Hardware Signals (Cont.)


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FLASH_ADDR22/TX_DELAY_MODE

IPD/O 3.3V GMAC port 0 transmit interface 2 ns delay mode:• 0: No delay• 1: Enable 2 ns delay

FLASH_ADDR23/RX_DELAY_MODE

IPD/O 3.3V GMAC port 0 receive interface 2 ns delay mode:• 0: No delay• 1: Enable 2 ns delay

FLASH_ADDR[25:24]/GMAC_MODE

IPD/O 3.3V GMAC port 0 interface mode:• 2'b01: MII mode• 2'b1x: RGMII mode

FLASH_CS0_N O 3.3V Chip select for the boot Flash (active low). Can be connected to serial or parallel Flash

FLASH_CS1_N O 3.3V Chip select for second Flash (active low). Can be connected to serial, parallel, or NAND Flash

FLASH_DATA[15:0] I/O 3.3V Parallel/NAND Flash data bus. External pull downs are required when unused.

FLASH_OE_N O 3.3V Output enable (active low). NAND Flash RE# (read enable) output (active low)

FLASH_WE_N O 3.3V Write enable (active low). NAND Flash WE# (write enable) output (active low)

Ethernet Interface (RGMII/MII)

Port 0Note: RGMII—10/100/1000 Mbps; MII—10/100 Mbps only

GMAC_COL IPD 2.5V/3.3V Collision detect

GMAC_CRS IPD 2.5V/3.3V Carrier sense

GMAC_RXCLK IPD/O 2.5V/3.3V Receive clock

GMAC_RXD[3:0] IPD 2.5V/3.3V Receive data

GMAC_RXDV IPD 2.5V/3.3V Receive data valid

GMAC_RXER IPD 2.5V/3.3V Receive error

GMAC_TXCLK IPD/O 2.5V/3.3V Transmit clock

GMAC_TXD[3:0] O 2.5V/3.3V Transmit data

GMAC_TXEN O 2.5V/3.3V Transmit enable

GMAC_TXER O 2.5V/3.3V Transmit error

Port 1Note: SGMII—10/100/1000 Mbps

SGMII_TXDP O 1.2V SGMII SerDes transmit data

SGMII_TXDN O 1.2V SGMII SerDes transmit data

SGMII_RXDP I 1.2V SGMII SerDes receive data

SGMII_RXDN I 1.2V SGMII SerDes receive data



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GPIO/SPI/UART Interfaces (internal PU/PD of GPIOs is user-configurable through register setting)

GPIO0/SPI_SCLK I/O 3.3V GPIO bit 0 or SPI master clock output

GPIO1/SPI_SS0 I/O 3.3V GPIO bit 1 or first SPI master select output

GPIO2/SPI_MOSI I/O 3.3V GPIO bit 2 or SPI master data output

GPIO3/SPI_MISO I/O 3.3V GPIO bit 3 or SPI master data input

GPIO4 I/O 3.3V GPIO bit 4

GPIO5/ I/O 3.3V GPIO bit 5

GPIO6/UART_RX2 I/O 3.3V GPIO bit 6 or 2nd UART receive data input

GPIO7/UART_TX2 I/O 3.3V GPIO bit 7 or 2nd UART transmit data output

GPIO8/SPI_SS1 I/O 3.3V GPIO bit 8 or second SPI select

GPIO9/SPI_SS2 I/O 3.3V GPIO bit 9 or third SPI select

GPIO10/FLASH_CS2_N I/O 3.3V GPIO bit 10 or additional chip select

GPIO11/FLASH_CS3_N I/O 3.3V GPIO bit 11 or additional chip select

GPIO[12:15] I/O 3.3V GPIO bits 12 to 15

JTAG Interface

JTCK IPU 3.3V JTAG clock

JTDI IPU 3.3V JTAG data input

JTDO O 3.3V JTAG data output

JTMS IPU 3.3V JTAG mode select

JTRST IPU 3.3V JTAG reset (active low)

MIIM Interface

MDC O 3.3V Management clock

MDIO IPD/O 3.3V Management data

PCIe Interface

PCIe0_RDN I 1.2V Negative leg of the differential pair receive serial data on PCIe port 0

PCIe0_RDP I 1.2V Positive leg of the differential pair receive serial data on PCIe port 0

PCIe0_TDN O 1.2V Negative leg of the differential pair transmit serial data on PCIe port 0

PCIe0_TDP O 1.2V Positive leg of the differential pair transmit serial data on PCIe port 0

PCIe0_RST_N O 1.2V PCIe port 0 reset (active low)

PCIe1_RDN I 1.2V Negative leg of the differential pair receive serial data on PCIe port 1

PCIe1_RDP I 1.2V Positive leg of the differential pair receive serial data on PCIe port 1

PCIe1_TDN O 1.2V Negative leg of the differential pair transmit serial data on PCIe port 1



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PCIe1_TDP O 1.2V Positive leg of the differential pair transmit serial data on PCIe port 1

PCIe1_RST_N O 1.2V PCIe port 1 reset (active low)

PCIe_REFCLKOUTP/N O 1.2V 100 MHz reference clock output differential pair

PCIe_REFCLKP/N I 1.2V 100 MHz reference clock input differential pairThis is used when FLASH_ADDR16/PCIe_REFCLKSEL pin is enabled.

Serial Flash Interface

SFlash_CLK O 3.3V Clock output for serial Flash

SFlash_SO O 3.3V Data output signal driving serial Flash

SFlash_SI IPU 3.3V Data input from serial Flash

I8S/TDM Interface

TDM0_BITCLK IPU/O 3.3V TDM channel 0 bit clock

TDM0_SDIO IPU/O 3.3V TDM channel 0 serial data input/output

TDM0_WS IPU/O 3.3V TDM channel 0 word select

TDM1_BITCLK IPU/O 3.3V TDM channel 1 bit clock

TDM1_SDIO IPU/O 3.3V TDM channel 1 serial data input/output

TDM1_WS IPU/O 3.3V TDM channel 1 word select

UART Interface

UART_RX IPU 3.3V UART receive data

UART_TX O 3.3V UART transmit data

USB Interface

USB_DATA_N/P I/O 1.2V USB differential pair data

USB_RREF I/O 1.2V USB resistance reference. This pin should be connected to an external 4.02 kΩ resistor in parallel with a 100 pF capacitor to ground.

USB_OCD IPU 3.3V USB over-current-detect input pin

Miscellaneous Interface

RESET_N IPU 3.3V Chip reset, active low, Schmitt-triggered

XTALI I 3.3V 25 MHz crystal/oscillator input

XTALO O 3.3V Crystal output

OSC_XTAL_SEL IPD 3.3V 25 MHz oscillator/crystal input clock select, 0V: selects crystal, 3.3V: selects oscillator

NC – – No connect



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Power

CORE_DVDD_1P2 – 1.2V 1.2V digital core power

CORE_PLLAVDD_1P2 – 1.2V 1.2V core PLL analog power

MISC1_PLLAVDD_1P2 – 1.2V 1.2V miscellaneous PLL analog power

MISC2_PLLAVDD_1P2 – 1.2V 1.2V miscellaneous PLL analog power

DDR_OVDD_1P8 – 1.8V 1.8V DDR2 and 1.8V I/O power

INT_OVDD_33 – 3.3V 3.3V interface I/O power, including Flash, I8S/TDM, GPIO, MDC, UART, JTAG interfaces, and global clock/reset pins

GMAC_OVDD_25_33 – 2.5V/3.3V GMAC port 0 power supply, tied to 2.5V for RGMII, 3.3V for MII

PCIe_PLLVDD_1P2 – 1.2V 1.2V PCIe SerDes PLL analog power

PCIe_SDVDD_1P2 – 1.2V 1.2V PCIe SerDes TX/RX analog power

SGMII_PLLAVDD_1P2 – 1.2V 1.2V SGMII SerDes PLL power

SGMII_VDD_1P2 – 1.2V 1.2V SGMII SerDes TX/RX analog power

USB_DVDD_1P2 – 1.2V 1.2V USB PHY PLL digital power

USB_PLLAVDD_1P2 – 1.2V 1.2V USB PHY PLL analog power

USB_AVDD_2P5 – 2.5V 2.5V USB PHY analog power

USB_AVDD_3P3 – 3.3V 3.3V USB PHY analog power

XTAL_PLLAVDD_3P3 – 3.3V 3.3V analog power for XTALI/O

Ground

DVSS – 0V Ground

PCIe_PLLVSS – 0V PCIe SerDes PLL analog ground

PCIe_SDVSS – 0V PCIe SerDes analog TX/RX ground

CORE_PLLAVSS – 0V Core PLL analog ground

MISC1_PLLAVSS – 0V Miscellaneous PLL analog ground

MISC2_PLLAVSS – 0V Miscellaneous PLL analog ground

SGMII_PLLAVSS – 0V SGMII SerDes PLL ground

SGMII_VSS – 0V SGMII SerDes TX/RX ground

USB_AVSS – 0V USB PHY ground



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BCM4706 Pin TablesBCM4706 Advance Data Sheet

BCM4706 Pin TablesTable 2: BCM4706 Sorted by Pin Location

Ball Signal

A1 DDR_OVDD_1P8

A2 DDR_SDRAM_DQ30

A3 DDR_SDRAM_DQ31

A4 JTRST

A5 JTMS

A6 SFlash_SO

A7 FLASH_DATA15

A8 FLASH_DATA11

A9 FLASH_DATA7

A10 FLASH_DATA3

A11 FLASH_ADDR26

A12 FLASH_ADDR22/TX_DELAY_MODE

A13 FLASH_ADDR18/SFLASH_BOOT

A14 FLASH_ADDR14

A15 FLASH_ADDR10

A16 FLASH_ADDR6/MIPS_EJTAG_MODE

A17 FLASH_ADDR2

A18 FLASH_OE_N

A19 UART_RX

A20 MDC

A21 GPIO15

A22 GPIO14

B1 DDR_SDRAM_DQ26

B2 DVSS

B3 DVSS

B4 DVSS

B5 DVSS

B6 FLASH_CS1_N

B7 DVSS

B8 FLASH_DATA10

B9 DVSS

B10 FLASH_DATA2

B11 DVSS

B12 FLASH_ADDR21

B13 DVSS

B14 FLASH_ADDR13

B15 DVSS

B16 FLASH_ADDR5

B17 DVSS

B18 FLASH_WE_N

B19 UART_TX

B20 MDIO

B21 GPIO13

B22 GPIO12

C1 DDR_SDRAM_DQSP3

C2 DDR_SDRAM_DQSN3

C3 DDR_OVDD_1P8

C4 DVSS

C5 JTCK

C6 DVSS

C7 FLASH_DATA14

C8 DVSS

C9 FLASH_DATA6

C10 DVSS

C11 FLASH_ADDR25/GMAC_MODE

C12 DVSS

C13 FLASH_ADDR17/BOOT_FLASH_TYPE

C14 DVSS

C15 FLASH_ADDR9

C16 DVSS

C17 FLASH_ADDR1

C18 FLASH_CS0_N

C19 INT_OVDD_33

C20 DVSS

C21 GPIO11/FLASH_CS3_N

C22 GPIO10/FLASH_CS2_N

D1 DDR_SDRAM_DQ28

D2 DVSS

D3 DDR_SDRAM_DQ29

D4 DVSS

D5 JTDO

D6 SFlash_CLK

D7 FLASH_DATA12

D8 FLASH_DATA9

D9 FLASH_DATA4

Ball Signal

D10 FLASH_DATA1

D11 FLASH_ADDR23/RX_DELAY_MODE

D12 FLASH_ADDR20

D13 FLASH_ADDR15

D14 FLASH_ADDR12/PCIe_DIS

D15 FLASH_ADDR7

D16 FLASH_ADDR4

D17 NC

D18 INT_OVDD_33

D19 RESET_N

D20 USB_OCD

D21 GPIO9/SPI_SS2

D22 INT_OVDD_33

E1 DDR_SDRAM_DQ22

E2 DDR_SDRAM_DQ23

E3 DDR_SDRAM_DQ27

E4 NC

E5 JTDI

E6 SFlash_SI

E7 FLASH_DATA13

E8 FLASH_DATA8

E9 FLASH_DATA5

E10 FLASH_DATA0

E11 FLASH_ADDR24/GMAC_MODE

E12 FLASH_ADDR19/MIPS_ENDIAN

E13 FLASH_ADDR16/PCIe_REFCLKSEL

E14 FLASH_ADDR11

E15 FLASH_ADDR8/GMAC_VSEL

E16 FLASH_ADDR3

E17 FLASH_ADDR0

E18 DVSS

E19 INT_OVDD_33

E20 OSC_XTAL_SEL

E21 DVSS

E22 GPIO6/UART_RX2

Ball Signal

F1 DDR_SDRAM_DQ24

F2 DDR_SDRAM_DQ25

F3 DDR_SDRAM_DM3

F4 DVSS

F5 INT_OVDD_33

F6 DVSS

F7 INT_OVDD_33

F8 DVSS

F9 INT_OVDD_33

F10 DVSS

F11 INT_OVDD_33

F12 DVSS

F13 INT_OVDD_33

F14 DVSS

F15 INT_OVDD_33

F16 DVSS

F17 INT_OVDD_33

F18 DVSS

F19 GPIO5

F20 GPIO8/SPI_SS1

F21 GPIO7/UART_TX2

F22 GPIO2/SPI_MOSI

G1 DDR_OVDD_1P8

G2 DVSS

G3 DDR_OVDD_1P8

G4 DVSS

G5 DVSS

G6 DVSS

G7 DVSS

G8 DVSS

G9 CORE_DVDD_1P2

G10 DVSS

G11 CORE_DVDD_1P2

G12 DVSS

G13 CORE_DVDD_1P2

G14 DVSS

G15 DVSS

G16 DVSS

G17 DVSS

Ball Signal

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G18 INT_OVDD_33

G19 GPIO4

G20 GPIO3/SPI_MISO

G21 GPIO1/SPI_SS0

G22 GPIO0/SPI_SCLK

H1 DDR_SDRAM_DQSP2

H2 DDR_SDRAM_DQSN2

H3 DVSS

H4 DDR_SDRAM_DQ21

H5 DVSS

H6 DVSS

H7 DVSS

H8 DDR_OVDD_1P8

H9 DVSS

H10 CORE_DVDD_1P2

H11 DVSS

H12 CORE_DVDD_1P2

H13 DVSS

H14 CORE_DVDD_1P2

H15 DVSS

H16 DVSS

H17 DVSS

H18 NC

H19 NC

H20 NC

H21 TDM1_WS

H22 TDM0_WS

J1 DDR_SDRAM_CK2P

J2 DDR_SDRAM_CK2N

J3 DDR_OVDD_1P8

J4 DVSS

J5 DVSS

J6 DVSS

J7 CORE_DVDD_1P2

J8 DVSS

J9 DVSS

J10 DVSS

J11 DVSS

J12 DVSS

J13 DVSS

J14 DVSS

J15 DVSS

J16 DVSS

Ball Signal

J17 DVSS

J18 DVSS

J19 NC

J20 TDM1_SDIO

J21 TDM0_SDIO

J22 TDM0_BITCLK

K1 DDR_SDRAM_DQ20

K2 DDR_SDRAM_DQ16

K3 DVSS

K4 DDR_SDRAM_DQ17

K5 DVSS

K6 DVSS

K7 DVSS

K8 DVSS

K9 DVSS

K10 DVSS

K11 DVSS

K12 DVSS

K13 DVSS

K14 CORE_DVDD_1P2

K15 DVSS

K16 PCIe_SDVSS

K17 DVSS

K18 PCIe_PLLVSS

K19 PCIe_SDVDD_1P2

K20 PCIe_SDVSS

K21 PCIe0_RST_N

K22 TDM1_BITCLK

L1 DDR_SDRAM_DQ19

L2 DDR_SDRAM_DQ18

L3 DVSS

L4 DDR_SDRAM_DM2

L5 DVSS

L6 DVSS

L7 CORE_DVDD_1P2

L8 DVSS

L9 CORE_DVDD_1P2

L10 DVSS

L11 DVSS

L12 DVSS

L13 DVSS

L14 DVSS

L15 DVSS

Ball Signal

L16 DVSS

L17 DVSS

L18 PCIe_REFCLKN

L19 PCIe0_RDP

L20 PCIe0_RDN

L21 PCIe_SDVDD_1P2

L22 PCIe1_RST_N

M1 DDR_SDRAM_DQ14

M2 DDR_SDRAM_DQ15

M3 DDR_OVDD_1P8

M4 DVSS

M5 DVSS

M6 DVSS

M7 DVSS

M8 DDR_OVDD_1P8

M9 DVSS

M10 DVSS

M11 DVSS

M12 DVSS

M13 DVSS

M14 CORE_DVDD_1P2

M15 DVSS

M16 DVSS

M17 PCIe_SDVDD_1P2

M18 PCIe_REFCLKP

M19 PCIe_SDVDD_1P2

M20 PCIe_SDVSS

M21 PCIe1_RDP

M22 PCIe1_RDN

N1 DDR_SDRAM_DQSP1

N2 DDR_SDRAM_DQSN1

N3 DVSS

N4 DDR_SDRAM_DQ13

N5 DVSS

N6 DVSS

N7 DVSS

N8 CORE_DVDD_1P2

N9 DVSS

N10 DVSS

N11 DVSS

N12 DVSS

N13 DVSS

N14 DVSS

Ball Signal

N15 DVSS

N16 DVSS

N17 PCIe_SDVSS

N18 PCIe_SDVSS

N19 PCIe0_TDP

N20 PCIe0_TDN

N21 PCIe_REFCLKOUTN

N22 PCIe_REFCLKOUTP

P1 DDR_SDRAM_DQ12

P2 DDR_SDRAM_DQ9

P3 DDR_OVDD_1P8

P4 DDR_SDRAM_DQ8

P5 DVSS

P6 DVSS

P7 DVSS

P8 DVSS

P9 DVSS

P10 DVSS

P11 DVSS

P12 DVSS

P13 DVSS

P14 CORE_DVDD_1P2

P15 DVSS

P16 DVSS

P17 DVSS

P18 DVSS

P19 PCIe_SDVDD_1P2

P20 PCIe_PLLVDD_1P2

P21 PCIe1_TDP

P22 PCIe1_TDN

R1 DDR_SDRAM_DQ11

R2 DDR_SDRAM_DQ10

R3 DVSS

R4 DDR_SDRAM_DM1

R5 DVSS

R6 DVSS

R7 DVSS

R8 CORE_DVDD_1P2

R9 DVSS

R10 DDR_OVDD_1P8

R11 CORE_DVDD_1P2

R12 DVSS

R13 DVSS

Ball Signal

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R14 DVSS

R15 DVSS

R16 DVSS

R17 DVSS

R18 DVSS

R19 DVSS

R20 USB_AVDD_2P5

R21 PCIe_SDVDD_1P2

R22 PCIe_SDVSS

T1 DVSS

T2 DVSS

T3 DVSS

T4 DVSS

T5 DVSS

T6 DVSS

T7 DVSS

T8 DVSS

T9 CORE_DVDD_1P2

T10 DVSS

T11 DVSS

T12 DVSS

T13 DVSS

T14 CORE_DVDD_1P2

T15 DVSS

T16 DVSS

T17 DVSS

T18 DVSS

T19 USB_DVDD_1P2

T20 NC

T21 USB_AVSS

T22 USB_RREF

U1 DDR_SDRAM_DQSN0

U2 DDR_SDRAM_DQSP0

U3 DVSS

U4 DVSS

U5 DVSS

U6 DVSS

U7 DVSS

U8 DVSS

U9 DVSS

U10 DVSS

U11 DVSS

U12 DVSS

Ball Signal

U13 SGMII_PLLAVDD_1P2

U14 SGMII_VDD_1P2

U15 DVSS

U16 DVSS

U17 GMAC_OVDD_25_33

U18 DVSS

U19 USB_AVDD_3P3

U20 USB_AVSS

U21 NC

U22 USB_DATA_N

V1 DDR_OVDD_1P8

V2 DVSS

V3 DVSS

V4 DDR_SDRAM_CKE

V5 DDR_SDRAM_RAS

V6 DDR_OVDD_1P8

V7 DVSS

V8 DVSS

V9 DVSS

V10 DDR_OVDD_1P8

V11 NC

V12 DVSS

V13 NC

V14 SGMII_VSS

V15 DVSS

V16 DVSS

V17 GMAC_OVDD_25_33

V18 DVSS

V19 GMAC_CRS

V20 MISC2_PLLAVSS

V21 USB_PLLAVDD_1P2

V22 USB_DATA_P

W1 DDR_SDRAM_DQ6

W2 DDR_SDRAM_DQ5

W3 DDR_SDRAM_DQ4

W4 DVSS

W5 DDR_SDRAM_CAS

W6 DDR_SDRAM_CS_N

W7 DDR_SDRAM_ADDR3

W8 DDR_OVDD_1P8

W9 DDR_SDRAM_ADDR9

W10 DDR_SDRAM_ADDR12

W11 DDR_SDRAM_ZQ

Ball Signal

W12 SGMII_PLLAVDD_1P2

W13 SGMII_VDD_1P2

W14 SGMII_VDD_1P2

W15 SGMII_VDD_1P2

W16 GMAC_TXD1

W17 GMAC_TXCLK

W18 GMAC_COL

W19 GMAC_RXDV

W20 MISC1_PLLAVSS

W21 MISC2_PLLAVDD_1P2

W22 NC

Y1 DDR_SDRAM_DQ7

Y2 DDR_SDRAM_DQ3

Y3 DDR_SDRAM_DQ0

Y4 DDR_OVDD_1P8

Y5 DVSS

Y6 DDR_SDRAM_BA1

Y7 DDR_SDRAM_ADDR0

Y8 DDR_SDRAM_ADDR4

Y9 DDR_SDRAM_ADDR6

Y10 DDR_SDRAM_ADDR10

Y11 NC

Y12 SGMII_PLLAVSS

Y13 SGMII_VSS

Y14 SGMII_VSS

Y15 SGMII_VSS

Y16 SGMII_VSS

Y17 GMAC_TXEN

Y18 GMAC_TXD3

Y19 GMAC_RXER

Y20 CORE_PLLAVSS

Y21 MISC1_PLLAVDD_1P2

Y22 NC

AA1 DDR_SDRAM_DQ2

AA2 DDR_SDRAM_DQ1

AA3 DDR_SDRAM_DM0

AA4 DDR_SDRAM_REF

AA5 DDR_SDRAM_BA2

AA6 DVSS

AA7 DDR_SDRAM_ADDR1

AA8 DVSS

AA9 DDR_SDRAM_ADDR7

AA10 DDR_SDRAM_ADDR14

Ball Signal

AA11 XTAL_PLLAVDD_3P3

AA12 XTALO

AA13 SGMII_VDD_1P2

AA14 SGMII_TXDN

AA15 SGMII_VDD_1P2

AA16 SGMII_RXDP

AA17 SGMII_VDD_1P2

AA18 GMAC_TXER

AA19 GMAC_RXD3

AA20 GMAC_RXD2

AA21 CORE_PLLAVDD_1P2

AA22 NC

AB1 DDR_SDRAM_CK0P

AB2 DDR_SDRAM_CK0N

AB3 DDR_SDRAM_ODT

AB4 DDR_SDRAM_WE

AB5 DDR_SDRAM_BA0

AB6 DDR_SDRAM_ADDR2

AB7 DDR_SDRAM_ADDR5

AB8 DDR_SDRAM_ADDR8

AB9 DDR_SDRAM_ADDR11

AB10 DDR_SDRAM_ADDR13

AB11 SGMII_PLLAVSS

AB12 XTALI

AB13 SGMII_VSS

AB14 SGMII_TXDP

AB15 SGMII_VSS

AB16 SGMII_RXDN

AB17 SGMII_VSS

AB18 GMAC_TXD0

AB19 GMAC_TXD2

AB20 GMAC_RXCLK

AB21 GMAC_RXD1

AB22 GMAC_RXD0

Ball Signal

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Table 3: BCM4706 Sorted by Signal Name

Signal Ball

CORE_DVDD_1P2 G9

CORE_DVDD_1P2 G11

CORE_DVDD_1P2 G13

CORE_DVDD_1P2 H10

CORE_DVDD_1P2 H12

CORE_DVDD_1P2 H14

CORE_DVDD_1P2 J7

CORE_DVDD_1P2 K14

CORE_DVDD_1P2 L7

CORE_DVDD_1P2 L9

CORE_DVDD_1P2 M14

CORE_DVDD_1P2 N8

CORE_DVDD_1P2 P14

CORE_DVDD_1P2 R8

CORE_DVDD_1P2 R11

CORE_DVDD_1P2 T9

CORE_DVDD_1P2 T14

CORE_PLLAVDD_1P2 AA21

CORE_PLLAVSS Y20

DDR_OVDD_1P8 A1

DDR_OVDD_1P8 C3

DDR_OVDD_1P8 G1

DDR_OVDD_1P8 G3

DDR_OVDD_1P8 H8

DDR_OVDD_1P8 J3

DDR_OVDD_1P8 M3

DDR_OVDD_1P8 M8

DDR_OVDD_1P8 P3

DDR_OVDD_1P8 R10

DDR_OVDD_1P8 V1

DDR_OVDD_1P8 V6

DDR_OVDD_1P8 V10

DDR_OVDD_1P8 W8

DDR_OVDD_1P8 Y4

DDR_SDRAM_ADDR0 Y7

DDR_SDRAM_ADDR1 AA7

DDR_SDRAM_ADDR10 Y10

DDR_SDRAM_ADDR11 AB9

DDR_SDRAM_ADDR12 W10

DDR_SDRAM_ADDR13 AB10

DDR_SDRAM_ADDR14 AA10

DDR_SDRAM_ADDR2 AB6

DDR_SDRAM_ADDR3 W7

DDR_SDRAM_ADDR4 Y8

DDR_SDRAM_ADDR5 AB7

DDR_SDRAM_ADDR6 Y9

DDR_SDRAM_ADDR7 AA9

DDR_SDRAM_ADDR8 AB8

DDR_SDRAM_ADDR9 W9

DDR_SDRAM_BA0 AB5

DDR_SDRAM_BA1 Y6

DDR_SDRAM_BA2 AA5

DDR_SDRAM_CAS W5

DDR_SDRAM_CK0N AB2

DDR_SDRAM_CK0P AB1

DDR_SDRAM_CK2N J2

DDR_SDRAM_CK2P J1

DDR_SDRAM_CKE V4

DDR_SDRAM_CS_N W6

DDR_SDRAM_DM0 AA3

DDR_SDRAM_DM1 R4

DDR_SDRAM_DM2 L4

DDR_SDRAM_DM3 F3

DDR_SDRAM_DQ0 Y3

DDR_SDRAM_DQ1 AA2

DDR_SDRAM_DQ10 R2

DDR_SDRAM_DQ11 R1

DDR_SDRAM_DQ12 P1

DDR_SDRAM_DQ13 N4

DDR_SDRAM_DQ14 M1

DDR_SDRAM_DQ15 M2

DDR_SDRAM_DQ16 K2

DDR_SDRAM_DQ17 K4

DDR_SDRAM_DQ18 L2

DDR_SDRAM_DQ19 L1

DDR_SDRAM_DQ2 AA1

DDR_SDRAM_DQ20 K1

DDR_SDRAM_DQ21 H4

DDR_SDRAM_DQ22 E1

DDR_SDRAM_DQ23 E2

DDR_SDRAM_DQ24 F1

DDR_SDRAM_DQ25 F2

DDR_SDRAM_DQ26 B1

Signal Ball

DDR_SDRAM_DQ27 E3

DDR_SDRAM_DQ28 D1

DDR_SDRAM_DQ29 D3

DDR_SDRAM_DQ3 Y2

DDR_SDRAM_DQ30 A2

DDR_SDRAM_DQ31 A3

DDR_SDRAM_DQ4 W3

DDR_SDRAM_DQ5 W2

DDR_SDRAM_DQ6 W1

DDR_SDRAM_DQ7 Y1

DDR_SDRAM_DQ8 P4

DDR_SDRAM_DQ9 P2

DDR_SDRAM_DQSN0 U1

DDR_SDRAM_DQSN1 N2

DDR_SDRAM_DQSN2 H2

DDR_SDRAM_DQSN3 C2

DDR_SDRAM_DQSP0 U2

DDR_SDRAM_DQSP1 N1

DDR_SDRAM_DQSP2 H1

DDR_SDRAM_DQSP3 C1

DDR_SDRAM_ODT AB3

DDR_SDRAM_RAS V5

DDR_SDRAM_REF AA4

DDR_SDRAM_WE AB4

DDR_SDRAM_ZQ W11

DVSS B2

DVSS B3

DVSS B4

DVSS B5

DVSS B7

DVSS B9

DVSS B11

DVSS B13

DVSS B15

DVSS B17

DVSS C4

DVSS C6

DVSS C8

DVSS C10

DVSS C12

DVSS C14

DVSS C16

Signal Ball

DVSS C20

DVSS D2

DVSS D4

DVSS E18

DVSS E21

DVSS F4

DVSS F6

DVSS F8

DVSS F10

DVSS F12

DVSS F14

DVSS F16

DVSS F18

DVSS G2

DVSS G4

DVSS G5

DVSS G6

DVSS G7

DVSS G8

DVSS G10

DVSS G12

DVSS G14

DVSS G15

DVSS G16

DVSS G17

DVSS H3

DVSS H5

DVSS H6

DVSS H7

DVSS H9

DVSS H11

DVSS H13

DVSS H15

DVSS H16

DVSS H17

DVSS J4

DVSS J5

DVSS J6

DVSS J8

DVSS J9

DVSS J10

DVSS J11

Signal Ball

4/12/2011 DXKOG


®


DVSS J12

DVSS J13

DVSS J14

DVSS J15

DVSS J16

DVSS J17

DVSS J18

DVSS K3

DVSS K5

DVSS K6

DVSS K7

DVSS K8

DVSS K9

DVSS K10

DVSS K11

DVSS K12

DVSS K13

DVSS K15

DVSS K17

DVSS L3

DVSS L5

DVSS L6

DVSS L8

DVSS L10

DVSS L11

DVSS L12

DVSS L13

DVSS L14

DVSS L15

DVSS L16

DVSS L17

DVSS M4

DVSS M5

DVSS M6

DVSS M7

DVSS M9

DVSS M10

DVSS M11

DVSS M12

DVSS M13

DVSS M15

DVSS M16

DVSS N3

Signal Ball

DVSS N5

DVSS N6

DVSS N7

DVSS N9

DVSS N10

DVSS N11

DVSS N12

DVSS N13

DVSS N14

DVSS N15

DVSS N16

DVSS P5

DVSS P6

DVSS P7

DVSS P8

DVSS P9

DVSS P10

DVSS P11

DVSS P12

DVSS P13

DVSS P15

DVSS P16

DVSS P17

DVSS P18

DVSS R3

DVSS R5

DVSS R6

DVSS R7

DVSS R9

DVSS R12

DVSS R13

DVSS R14

DVSS R15

DVSS R16

DVSS R17

DVSS R18

DVSS R19

DVSS T1

DVSS T2

DVSS T3

DVSS T4

DVSS T5

DVSS T6

Signal Ball

DVSS T7

DVSS T8

DVSS T10

DVSS T11

DVSS T12

DVSS T13

DVSS T15

DVSS T16

DVSS T17

DVSS T18

DVSS U3

DVSS U4

DVSS U5

DVSS U6

DVSS U7

DVSS U8

DVSS U9

DVSS U10

DVSS U11

DVSS U12

DVSS U15

DVSS U16

DVSS U18

DVSS V2

DVSS V3

DVSS V7

DVSS V8

DVSS V9

DVSS V12

DVSS V15

DVSS V16

DVSS V18

DVSS W4

DVSS Y5

DVSS AA6

DVSS AA8

FLASH_ADDR0 E17

FLASH_ADDR1 C17

FLASH_ADDR10 A15

FLASH_ADDR11 E14

FLASH_ADDR12/PCIe_DIS

D14

FLASH_ADDR13 B14

Signal Ball

FLASH_ADDR14 A14

FLASH_ADDR15 D13

FLASH_ADDR16/PCIe_REFCLKSEL

E13

FLASH_ADDR17/BOOT_FLASH_TYPE

C13

FLASH_ADDR18/SFLASH_BOOT

A13


E12

FLASH_ADDR2 A17

FLASH_ADDR20 D12

FLASH_ADDR21 B12

FLASH_ADDR22/TX_DELAY_MODE

A12

FLASH_ADDR23/RX_DELAY_MODE

D11

FLASH_ADDR24/GMAC_MODE

E11


C11

FLASH_ADDR26 A11

FLASH_ADDR3 E16

FLASH_ADDR4 D16

FLASH_ADDR5 B16

FLASH_ADDR6/MIPS_EJTAG_MODE

A16

FLASH_ADDR7 D15

FLASH_ADDR8/GMAC_VSEL

E15

FLASH_ADDR9 C15

FLASH_CS0_N C18

FLASH_CS1_N B6

FLASH_DATA0 E10

FLASH_DATA1 D10

FLASH_DATA10 B8

FLASH_DATA11 A8

FLASH_DATA12 D7

FLASH_DATA13 E7

FLASH_DATA14 C7

FLASH_DATA15 A7

FLASH_DATA2 B10

FLASH_DATA3 A10

FLASH_DATA4 D9

FLASH_DATA5 E9

Signal Ball

4/12/2011 DXKOG


®


FLASH_DATA6 C9

FLASH_DATA7 A9

FLASH_DATA8 E8

FLASH_DATA9 D8

FLASH_OE_N A18

FLASH_WE_N B18

GMAC_COL W18

GMAC_CRS V19

GMAC_OVDD_25_33 U17

GMAC_OVDD_25_33 V17

GMAC_RXCLK AB20

GMAC_RXD0 AB22

GMAC_RXD1 AB21

GMAC_RXD2 AA20

GMAC_RXD3 AA19

GMAC_RXDV W19

GMAC_RXER Y19

GMAC_TXCLK W17

GMAC_TXD0 AB18

GMAC_TXD1 W16

GMAC_TXD2 AB19

GMAC_TXD3 Y18

GMAC_TXEN Y17

GMAC_TXER AA18

GPIO0/SPI_SCLK G22

GPIO1/SPI_SS0 G21

GPIO10/FLASH_CS2_N C22

GPIO11/FLASH_CS3_N C21

GPIO12 B22

GPIO13 B21

GPIO14 A22

GPIO15 A21

GPIO2/SPI_MOSI F22

GPIO3/SPI_MISO G20

GPIO4 G19

GPIO5 F19

GPIO6/UART_RX2 E22

GPIO7/UART_TX2 F21

GPIO8/SPI_SS1 F20

GPIO9/SPI_SS2 D21

INT_OVDD_33 C19

INT_OVDD_33 D18

INT_OVDD_33 D22

Signal Ball

INT_OVDD_33 E19

INT_OVDD_33 F5

INT_OVDD_33 F7

INT_OVDD_33 F9

INT_OVDD_33 F11

INT_OVDD_33 F13

INT_OVDD_33 F15

INT_OVDD_33 F17

INT_OVDD_33 G18

JTCK C5

JTDI E5

JTDO D5

JTMS A5

JTRST A4

MDC A20

MDIO B20

MISC1_PLLAVDD_1P2 Y21

MISC1_PLLAVSS W20

MISC2_PLLAVDD_1P2 W21

MISC2_PLLAVSS V20

NC D17

NC E4

NC H18

NC H19

NC H20

NC J19

NC T20

NC U21

NC V11

NC V13

NC W22

NC Y11

NC Y22

NC AA22

OSC_XTAL_SEL E20

PCIe_PLLVDD_1P2 P20

PCIe_PLLVSS K18

PCIe_REFCLKN L18

PCIe_REFCLKOUTN N21

PCIe_REFCLKOUTP N22

PCIe_REFCLKP M18

PCIe_SDVDD_1P2 K19

PCIe_SDVDD_1P2 L21

Signal Ball

PCIe_SDVDD_1P2 M17

PCIe_SDVDD_1P2 M19

PCIe_SDVDD_1P2 P19

PCIe_SDVDD_1P2 R21

PCIe_SDVSS K16

PCIe_SDVSS K20

PCIe_SDVSS M20

PCIe_SDVSS N17

PCIe_SDVSS N18

PCIe_SDVSS R22

PCIe0_RDN L20

PCIe0_RDP L19

PCIe0_RST_N K21

PCIe0_TDN N20

PCIe0_TDP N19

PCIe1_RDN M22

PCIe1_RDP M21

PCIe1_RST_N L22

PCIe1_TDN P22

PCIe1_TDP P21

RESET_N D19

SFlash_CLK D6

SFlash_SI E6

SFlash_SO A6

SGMII_PLLAVDD_1P2 U13

SGMII_PLLAVDD_1P2 W12

SGMII_PLLAVSS Y12

SGMII_PLLAVSS AB11

SGMII_RXDN AB16

SGMII_RXDP AA16

SGMII_TXDN AA14

SGMII_TXDP AB14

SGMII_VDD_1P2 U14

SGMII_VDD_1P2 W13

SGMII_VDD_1P2 W14

SGMII_VDD_1P2 W15

SGMII_VDD_1P2 AA13

SGMII_VDD_1P2 AA15

SGMII_VDD_1P2 AA17

SGMII_VSS V14

SGMII_VSS Y13

SGMII_VSS Y14

SGMII_VSS Y15

Signal Ball

SGMII_VSS Y16

SGMII_VSS AB13

SGMII_VSS AB15

SGMII_VSS AB17

TDM0_BITCLK J22

TDM0_SDIO J21

TDM0_WS H22

TDM1_BITCLK K22

TDM1_SDIO J20

TDM1_WS H21

UART_RX A19

UART_TX B19

USB_AVDD_2P5 R20

USB_AVDD_3P3 U19

USB_AVSS T21

USB_AVSS U20

USB_DATA_N U22

USB_DATA_P V22

USB_DVDD_1P2 T19

USB_OCD D20

USB_PLLAVDD_1P2 V21

USB_RREF T22

XTAL_PLLAVDD_3P3 AA11

XTALI AB12

XTALO AA12

Signal Ball

4/12/2011 DX

KO

G


®

BCM4706 BallmapBCM4706 Advance Data Sheet

BCM4706 Ballmap

Figure 3: BCM4706 Ballmap—Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

A DDR_OVDD_1P8

DDR_SDRAM_DQ30

DDR_SDRAM_DQ31 JTRST JTMS SFlash_SO FLASH_DA

TA15FLASH_DA

TA11FLASH_DA

TA7FLASH_DA

TA3FLASH_AD

DR26

FLASH_ADDR22/TX_DELAY_M

ODE

FLASH_ADDR18/SFLASH_BOO

T

FLASH_ADDR14

FLASH_ADDR10

FLASH_ADDR6/MIPS_EJTAG_M

ODE

FLASH_ADDR2

FLASH_OE_N UART_RX MDC GPIO15 GPIO14

B DDR_SDRAM_DQ26 DVSS DVSS DVSS DVSS FLASH_CS

1_N DVSS FLASH_DATA10 DVSS FLASH_DA

TA2 DVSS FLASH_ADDR21 DVSS FLASH_AD

DR13 DVSS FLASH_ADDR5 DVSS FLASH_W

E_N UART_TX MDIO GPIO13 GPIO12

CDDR_SDRAM_DQSP

3

DDR_SDRAM_DQSN

3

DDR_OVDD_1P8 DVSS JTCK DVSS FLASH_DA

TA14 DVSS FLASH_DATA6 DVSS


DVSS

FLASH_ADDR17/BOOT_FLASH_

TYPE

DVSS FLASH_ADDR9 DVSS FLASH_AD

DR1FLASH_CS

0_NINT_OVDD

_33 DVSSGPIO11/FLASH_CS3_

N

GPIO10/FLASH_CS2_

N

D DDR_SDRAM_DQ28 DVSS DDR_SDR

AM_DQ29 DVSS JTDO SFlash_CLK

FLASH_DATA12

FLASH_DATA9

FLASH_DATA4

FLASH_DATA1

FLASH_ADDR23/RX_DELAY_M

ODE

FLASH_ADDR20

FLASH_ADDR15

FLASH_ADDR12/PCIe

_DIS

FLASH_ADDR7

FLASH_ADDR4 NC INT_OVDD

_33 RESET_N USB_OCD GPIO9/SPI_SS2

INT_OVDD_33

E DDR_SDRAM_DQ22

DDR_SDRAM_DQ23

DDR_SDRAM_DQ27 NC JTDI SFlash_SI FLASH_DA

TA13FLASH_DA

TA8FLASH_DA

TA5FLASH_DA

TA0



FLASH_ADDR16/PCIe_REFCLKS

EL

FLASH_ADDR11

FLASH_ADDR8/GMAC

_VSEL

FLASH_ADDR3

FLASH_ADDR0 DVSS INT_OVDD

_33OSC_XTAL

_SEL DVSSGPIO6/

UART_RX2

F DDR_SDRAM_DQ24

DDR_SDRAM_DQ25

DDR_SDRAM_DM3 DVSS INT_OVDD

_33 DVSS INT_OVDD_33 DVSS INT_OVDD



_33 DVSS GPIO5 GPIO8/SPI

_SS1

GPIO7/UART_TX2 GPIO2/SPI

_MOSI

G DDR_OVDD_1P8 DVSS DDR_OVD

D_1P8 DVSS DVSS DVSS DVSS DVSS CORE_DVDD_1P2 DVSS CORE_DV

DD_1P2 DVSS CORE_DVDD_1P2 DVSS DVSS DVSS DVSS INT_OVDD

_33 GPIO4 GPIO3/SPI_MISO

GPIO1/SPI_SS0

GPIO0/SPI_SCLK

HDDR_SDRAM_DQSP

2

DDR_SDRAM_DQSN

2DVSS DDR_SDR

AM_DQ21 DVSS DVSS DVSS DDR_OVDD_1P8 DVSS CORE_DV

DD_1P2 DVSS CORE_DVDD_1P2 DVSS CORE_DV

DD_1P2 DVSS DVSS DVSS TDM1_WS TDM0_WS

J DDR_SDRAM_CK2P

DDR_SDRAM_CK2N

DDR_OVDD_1P8 DVSS DVSS DVSS CORE_DV

DD_1P2 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS TDM1_SDIO

TDM0_SDIO

TDM0_BITCLK

K DDR_SDRAM_DQ20

DDR_SDRAM_DQ16 DVSS DDR_SDR

AM_DQ17 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS CORE_DVDD_1P2 DVSS PCIe_SDV

SS DVSS PCIe_PLLVSS

PCIe_SDVDD_1P2

PCIe_SDVSS

PCIe0_RST_N

TDM1_BITCLK

L DDR_SDRAM_DQ19


AM_DM2 DVSS DVSS CORE_DVDD_1P2 DVSS CORE_DV

DD_1P2 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PCIe_REFCLKN

PCIe0_RDP

PCIe0_RDN

PCIe_SDVDD_1P2

PCIe1_RST_N

M DDR_SDRAM_DQ14

DDR_SDRAM_DQ15

DDR_OVDD_1P8 DVSS DVSS DVSS DVSS DDR_OVD

D_1P8 DVSS DVSS DVSS DVSS DVSS CORE_DVDD_1P2 DVSS DVSS PCIe_SDV

DD_1P2PCIe_REF

CLKPPCIe_SDVDD_1P2

PCIe_SDVSS

PCIe1_RDP

PCIe1_RDN

NDDR_SDRAM_DQSP

1

DDR_SDRAM_DQSN

1DVSS DDR_SDR

AM_DQ13 DVSS DVSS DVSS CORE_DVDD_1P2 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PCIe_SDV

SSPCIe_SDV

SSPCIe0_TD

PPCIe0_TD

NPCIe_REFCLKOUTN

PCIe_REFCLKOUTP

P DDR_SDRAM_DQ12

DDR_SDRAM_DQ9

DDR_OVDD_1P8

DDR_SDRAM_DQ8 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS CORE_DV

DD_1P2 DVSS DVSS DVSS DVSS PCIe_SDVDD_1P2

PCIe_PLLVDD_1P2

PCIe1_TDP

PCIe1_TDN

R DDR_SDRAM_DQ11


AM_DM1 DVSS DVSS DVSS CORE_DVDD_1P2 DVSS DDR_OVD

D_1P8CORE_DVDD_1P2 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS USB_AVD

D_2P5PCIe_SDVDD_1P2

PCIe_SDVSS

T DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS CORE_DVDD_1P2 DVSS DVSS DVSS DVSS CORE_DV

DD_1P2 DVSS DVSS DVSS DVSS USB_DVDD_1P2 NC USB_AVSS USB_RRE

F

UDDR_SDRAM_DQSN

0

DDR_SDRAM_DQSP

0DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS SGMII_PLL

AVDD_1P2SGMII_VD

D_1P2 DVSS DVSS GMAC_OVDD_25_33 DVSS USB_AVD

D_3P3 USB_AVSS NC USB_DATA_N

V DDR_OVDD_1P8 DVSS DVSS DDR_SDR

AM_CKEDDR_SDRAM_RAS

DDR_OVDD_1P8 DVSS DVSS DVSS DDR_OVD

D_1P8 NC DVSS NC SGMII_VSS DVSS DVSS GMAC_OV

DD_25_33 DVSS GMAC_CRS

MISC2_PLLAVSS

USB_PLLAVDD_1P2

USB_DATA_P

W DDR_SDRAM_DQ6

DDR_SDRAM_DQ5


AM_CASDDR_SDRAM_CS_N

DDR_SDRAM_ADDR

3

DDR_OVDD_1P8

DDR_SDRAM_ADDR

9

DDR_SDRAM_ADDR

12

DDR_SDRAM_ZQ

SGMII_PLLAVDD_1P2

SGMII_VDD_1P2

SGMII_VDD_1P2

SGMII_VDD_1P2

GMAC_TXD1

GMAC_TXCLK

GMAC_COL

GMAC_RXDV

MISC1_PLLAVSS

MISC2_PLLAVDD_1P

2NC

Y DDR_SDRAM_DQ7

DDR_SDRAM_DQ3

DDR_SDRAM_DQ0

DDR_OVDD_1P8 DVSS DDR_SDR

AM_BA1

DDR_SDRAM_ADDR

0

DDR_SDRAM_ADDR

4

DDR_SDRAM_ADDR

6

DDR_SDRAM_ADDR

10NC SGMII_PLL

AVSSSGMII_VS

SSGMII_VS

SSGMII_VS

SSGMII_VS

SGMAC_TX

ENGMAC_TX

D3GMAC_RX

ERCORE_PLL

AVSS

MISC1_PLLAVDD_1P

2NC

AA DDR_SDRAM_DQ2

DDR_SDRAM_DQ1

DDR_SDRAM_DM0

DDR_SDRAM_REF

DDR_SDRAM_BA2 DVSS

DDR_SDRAM_ADDR

1DVSS

DDR_SDRAM_ADDR

7

DDR_SDRAM_ADDR

14

XTAL_PLLAVDD_3P3 XTALO SGMII_VD

D_1P2SGMII_TX

DNSGMII_VD

D_1P2SGMII_RX

DPSGMII_VD

D_1P2GMAC_TX

ERGMAC_RX

D3GMAC_RX

D2CORE_PLLAVDD_1P2 NC

AB DDR_SDRAM_CK0P

DDR_SDRAM_CK0N

DDR_SDRAM_ODT

DDR_SDRAM_WE

DDR_SDRAM_BA0

DDR_SDRAM_ADDR

2

DDR_SDRAM_ADDR

5

DDR_SDRAM_ADDR

8

DDR_SDRAM_ADDR

11

DDR_SDRAM_ADDR

13

SGMII_PLLAVSS XTALI SGMII_VS

SSGMII_TX

DPSGMII_VS

SSGMII_RX

DNSGMII_VS

SGMAC_TX

D0GMAC_TX

D2GMAC_RX

CLKGMAC_RX

D1GMAC_RX

D0

NCNC

NC

NC

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Electrical Characteristics


®


Section 3: Electrical Characteristics

Absolute Maximum Ratings

Table 4: Absolute Maximum Ratingsa

a. These specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at maximum conditions for extended periods may adversely affect long-term reliability of the device.

Parameter Symbol Min Max Units

3.3V Supply Voltage INT_OVDD_33, GMAC_OVDD_25_33, USB_AVDD_3P3, XTAL_PLLAVDD_3P3

–0.5 +3.63 V

2.5V Supply Voltage GMAC_OVDD_25_33, USB_AVDD_2P5 –0.5 +2.75 V

1.2V Supply Voltage CORE_DVDD_1P2, CORE_PLLAVDD_1P2, MISC1_PLLAVDD_1P2, MISC2_PLLAVDD_1P2, PCIe_PLLVDD_1P2, PCIe_SDVDD_1P2, SGMII_PLLAVDD_1P2, SGMII_VDD_1P2, USB_DVDD_1P2, USB_PLLAVDD_1P2

–0.5 +1.32 V

1.8V Supply Voltage DDR_OVDD_1P8 –0.5 +1.98 V

Maximum Junction Temperature

TJ_MAX – +125 oC

Commercial Ambient Temperature (Operating)

TA 0 +70 oC

Industrial Ambient Temperature (Operating)

TA –40 +85 oC

Operating Humidity – – +85 %

Storage Temperature TSTG –40 +125 oC

Storage Humidity – – 60 %

4/12/2011 DXKOG

Recommended Operating Conditions and DC Characteristics


®


Recommended Operating Conditions and DC Characteristics

Table 5: Recommended Operating Conditions

Symbol Nominal Limits Units

CORE_DVDD_1P2 1.2V ±5% V

CORE_PLLAVDD_1P2 1.2V ±5% V

MISC1_PLLAVDD_1P2 1.2V ±5% V

MISC2_PLLAVDD_1P2 1.2V ±5% V

DDR_OVDD_1P8 1.8V ±0.1 V

INT_OVDD_33 3.3V ±5% V

GMAC_OVDD_25_33 2.5V/3.3V ±5% V

PCIe_PLLVDD_1P2 1.2V ±5% V

PCIe_SDVDD_1P2 1.2V ±5% V

SGMII_PLLAVDD_1P2 1.2V ±5% V

SGMII_VDD_1P2 1.2V ±5% V

USB_DVDD_1P2 1.2V ±5% V

USB_PLLAVDD_1P2 1.2V ±5% V

USB_AVDD_2P5 2.5V ±5% V

USB_AVDD_3P3 3.3V ±5% V

XTAL_PLLAVDD_3P3 3.3V ±5% V

Note: See the BCM4706 Hardware Design Guide on docSAFE for more information on power supplies decoupling.

Table 6: Total Power and Supply Current

Supply Voltage BCM4706 Typical Value Units

3.3V 75 mW

2.5V 105 mW

1.8V 840 mW

1.2V 1670 mW

Note: These power consumption numbers were derived under nominal conditions. For example, typical corner silicon, nominal temperature (25°C), and nominal voltages.

4/12/2011 DXKOG

Core and I/O Power Sequencing Requirements


®


Core and I/O Power Sequencing RequirementsThe BCM4706 device requires specific power sequencing between the core and I/O supplies.

• The BCM4706 device power sequence requires I/O power (3.3V; 2.5V; 1.8V) to come up first, followed by the core power (1.2V). The requirement is that the core power (1.2V) should not be on until the I/O power (3.3V, 2.5V, 1.8V) reaches at least 1.0V.

• When core power reaches nominal core voltage (1.2V ±5%), the I/O power should be stable at nominal I/O voltage (3.3V ±5%, 2.5V ±5%, or 1.8V ±5%)

• The maximum ramp-up time for core power 1.2V (from 0V to nominal voltage ±5%) is 2 ms as shown in figure below.

In addition, for successful power-up, Broadcom recommends that the external hardware reset be asserted for at least 50 ms after both I/O and core power are stable as shown in Figure 4.

Figure 4: Power Supply Sequencing

4/12/2011 DXKOG

DDR2 SDRAM Memory Interface DC Characteristics


®


DDR2 SDRAM Memory Interface DC Characteristics

USB Host Interface DC Characteristics

Table 7: DC Characteristics for DDR2 SDRAM Interface

Parameter Symbol Min Max Units Conditions

SSTL Reference Voltage VREF DDR_OVDD_1P8 × 0.49

DDR_OVDD_1P8 × 0.51

V Typically derived from DDR_OVDD_1P8 ÷ 2

DC Input High Voltage VIHDC VREF + 0.125 DDR_OVDD_1P8 + 0.3

V –

DC Input Low Voltage VILDC –0.3 VREF – 0.125 V –

AC Input High Voltage VIHAC VREF + 0.2 – V –

AC Input Low Voltage VILAC – VREF – 0.2 V –

DC Output High Voltage VOH DDR_OVDD_1P8 - 0.35

– V –

DC Output Low Voltage VOL – 0.35 V –

DC Output Source Current IOH 9 – mA –

DC Output Sink Current IOL 9 – mA –

Output Impedance ZOUT 36 44 Ω –

Termination Impedance ZTERM 54108

66132

Ω Strong termination

Ω Weak termination

Table 8: USB Host Interface DC Characteristics

Parameter Symbol Min Typ Max Units Conditions

Receiver – HS mode

Input Common Mode Voltage Range

VHSCM -50 – 500 mV –

Differential Input Voltage Sensitivity

VHSDI 300 – – mV Static | VIDP – VIDN |

Squelch Detection Threshold (differential)

VHSSQ – – 100 mV Squelch detected

150 – – mV No Squelch detected

Disconnect Detection Threshold (differential)

VHSDSC 625 – – mV Disconnect detected

– – 525 mV Disconnect undetected

Transmitter–HS mode

Output High Voltage VHSOH 360 400 440 mV Static condition

Output Low Voltage VHSOL –10 0 10 mV Static condition

4/12/2011 DXKOG

USB Host Interface DC Characteristics


®


Output Impedance RO 40.5 45 49.5 ohm Single-ended

Chirp-J Output Voltage (differential)

VCHIRPJ 700 1100 mV HS Termination disabled RPU connected

Chirp-K Output Voltage (differential)

VCHIRPK -900 -500 mV HS Termination disabled RPU connected

Note: See Section 7 of the USB 2.0 specification (www.usb.org) for more info on the Receiver Eye Diagram Template.

Table 9: USB 1.1 Electrical and Timing Parameters

Parameter Symbol Condition

Value

UnitsMinimum Typical Maximum

Receiver — FS

Differential Input Sensitivity (min)

VDI Static |VIDP – VIDN |

200 – – mV

Differential Common Mode Range (max)

VCM – 0.8 – 2.5 V

Transmitter — FS

Output High Voltage VFSOH Static condition 2.8 – 3.6 V

Output Low Voltage VFSOL Static condition 0.0 – 0.3 V

Output Signal Crossover Voltage

VCRS – 1.3 – 2.0 V

Output Impedance RO Single-ended 28 36 44 Ω

Terminations

Bus Pull-down Resistor on Host Port

RPD – 14.25 – 15.75 kΩ

Input Impedance ZIN – 300 – kΩ

Table 8: USB Host Interface DC Characteristics (Cont.)


4/12/2011 DXKOG

PCIe DC Characteristics


®


PCIe DC CharacteristicsTable 10 shows PCIe DC characteristics.

1G SGMII/SerDes Port SignalsTable 11 shows the 1G SGMII/SerDes port signals. These signals are AC coupled.

Table 10: PCIe DC Characteristics

Parameter Description Min Typ Max Units

Transmitter

ZOUT Transmitter Output Impedance (differential) – 100 – ΩVOD Transmitter Output Voltage (differential peak – to – peak) – – 1200 mVP-P

Receiver

ZIN Receiver Input Impedance (differential) - 100 – ΩVID Receiver Input Voltage (differential peak – to – peak) 175 – 2000 mVP-P

Table 11: 1G SGMII/SerDes Port Signals


VID Receiver Input Voltage, differential peak to peak, AC coupled 100 – 2000 mV

RIN Receiver Input Impedance, differential, integrated on-chip 80 100 120 ΩVOD Transmitter Output Voltage, differential peak-to-peak,

programmable– 700 1100 mV

RO Transmitter Output Impedance (differential) 80 100 120 Ω

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Standard 3.3V Signals


®


Standard 3.3V SignalsThese specifications apply to all 3.3V signals, such as Flash, Serial Flash, MII, I8S/TDM, GPIO, MDC/MDIO, UART, JTAG interfaces, and global clock/reset pins.

Standard 2.5V SignalsThese specifications apply to the RGMII interface.

XTAL Oscillator Interface

Table 12: Standard 3.3V Signals


VIN Input voltage – 0.3 – 3.6 V

VIL Input low voltage – – 0.8 V

VIH Input high voltage 2.0 – – V

VOL Output low voltage – – 0.4 V

VOH Output high voltage 2.4 – – V

CI I/O pin capacitance – – 10 pF

Table 13: Standard 2.5V Signals


VIN Input voltage – 0.3 – 2.75 V

VIL Input low voltage – – 0.8 V

VIH Input high voltage 1.7 – – V

VOL Output low voltage – – 0.4 V

VOH Output high voltage 2.0 – – V

CI I/O pin capacitance – – 10 pF

Table 14: XTAL Oscillator Interface

Parameter Symbol Min Max Units

Input Low Voltage XTALIL –0.3 +0.8 V

Input High Voltage XTALIH 2.0 XTAL_PLLAVDD_3P3 + 0.5 V

4/12/2011 DXKOG

Timing Characteristics


®


Section 4: T iming Characteristics

Reset and Clock Timing

Figure 5: Reset and Clock Timing

Table 15: Reset and Clock Timing

Parameter Description Minimum Typical Maximum Units

t201 XTALI frequency – 25.0000 – MHz

t202 XTALI high time – 20 – ns

t203 XTALI low time – 20 – ns

t204 RESET_N low pulse duration 50 – – ms

t207 Configuration valid setup to RESET_N rising 0 – – μs

t208 Configuration valid hold from RESET_N rising 8.5 – 10 μs

t209 RESET_N deassertion to normal operation – 110 – μs

t210 Reset low hold time after power supplies stabilize

50 – – ms

Voltage Rails

XTAL_IN(25 MHz)

RESET_N

ConfigurationStrap Signals

Valid

t201

t202

t203

t204

t207 t208

t209

t210

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Parallel Flash Timing


®



Parallel Flash READ Timing

Figure 6: Parallel Flash READ Timing Diagram

Table 16: Parallel Flash READ Timing

Parameter Descriptions Min Typ Max Units Comments

t0 Output Enable Assertion Time 1 – 32 Internal reference clock

WaitCount0+1

t1 Chip Select Inactive Time 1 – 32 Internal reference clock

WaitCount1+1

t2 Chip Select Low to Output Enable Low 1 – 32 Internal reference clock

WaitCount2+1

t3 Output Enable High to Chip Select High

1 – 32 Internal reference clock

WaitCount3+1

Note: Each timing parameter can be programmed individually through the corresponding WaitCount field on the FlashWaitCnt register.

Note: The internal reference clock runs at 150 MHz.

Address ValidFLASH_ADDR[26:0]

FLASH_CS[1:0]_Nt2 t1t3

t0FLASH_OE_N

Data ValidFLASH_DATA[15:0]

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®


Parallel Flash WRITE Timing

Figure 7: Parallel Flash WRITE Timing Diagram

Table 17: Parallel Flash WRITE Timing

Parameter Descriptions Min Typ Max Units Comments

t0 Output Enable Assertion Time 1 – 32 Internal reference clock WaitCount0 + 1

t1 Chip Select Inactive Time 1 – 32 Internal reference clock WaitCount1 + 1

t2 Chip Select Low to Write Enable Low

1 – 32 Internal reference clock WaitCount2 + 1

t3 Write Enable High to Chip Select High

1 – 32 Internal reference clock WaitCount3 + 1

Note: Each timing parameter can be programmed individually through the corresponding WaitCount field on the FlashWaitCnt register.

Note: The internal reference clock runs at 150 MHz.

Address ValidFLASH_ADDR[26:0]

FLASH_CS[1:0]_Nt2 t1t3

t0FLASH_WE_N

Data ValidFLASH_DATA[15:0]

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Serial Flash Timing (ST Micro-compatible Device)


®


Serial Flash Timing (ST Micro-compatible Device)

Figure 8: Serial Flash Timing Diagram

Table 18: Serial Flash Timing

Parameter Descriptions Min Typ Max Units

fFREQ SFlash_CLK frequency – – 37.5 MHz

tP Cycle time: SFlash_CLK period 26.67/40 – – ns

t1 Delay time: Flash_CSx_N low to SFlash_CLK rising edge

20 – – ns

t2 Setup time: SFlash_SI valid to SFlash_CLK falling edge

10 – – ns

t3 Hold time: SFlash_CLK falling edge to SFlash_SI invalid

0 – – ns

t4 Output valid time: SFlash_SO valid to SFlash_CLK rising edge

5.5 – – ns

SFlash_CLK

Flash_CSx_N

SFlash_SO

SFlash_SI

tp

t2 t3

t4

t1

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DDR2 SDRAM AC Timing Characteristics


®


DDR2 SDRAM AC Timing CharacteristicsTable 19 shows the AC characteristics for the DDR SDRAM interface.

Table 19: AC Characteristics for DDR SDRAM Interface


tCK(avg) Average clock period (programmable) 3.33 – – ns

tCH(avg) Average clock HIGH pulse width 0.48 0.5 0.52 tCK(avg)

tCL(avg) Average clock LOW pulse width 0.48 0.5 0.52 tCK(avg)

tJIT(per) Clock period jitter –125 – 125 ps

tJIT(cc) Cycle to cycle clock period jitter –250 – 250 ps

tJIT(duty) Duty cycle jitter –125 – 125 ps

tDQSS DQS latching rising transitions to associated clock edges (for write, also related to tDSS, tDSH)

–250 0 250 ps

tDQSH DQS HIGH pulse width (for write) 0.35 0.5 – tCK(avg)

tDQSL DQS LOW pulse width (for write) 0.35 0.5 – tCK(avg)

tWPRE Write preamble, DQS driver turn-on to the first DQS edge

0.35 – – tCK(avg)

tWPST Write postamble, DQS time to high-Z after the last falling DQS edge

0.4 – – tCK(avg)

tCK2AC Delay from clock to address and control signals, VDL adjustable (related to tIS, tIH at DDR2 SDRAM)

– 0.25 – tCK(avg)

tIPW Control and address output pulse width 0.6 – – tCK(avg)

tWDQ2DQS Delay from DQ or DM to DQS, VDL adjustable (for write, related to tDS, tDH at DDR2 SDRAM)

– 0.25 – tCK(avg)

tDIPW DQ and DM output pulse width (for write)

0.35 – – tCK(avg)

tDQSCK DQS delay from clock (for read) –400 – 400 ns

tRDQDQSS DQ to DQS setup time (for read) 0.2-tCK(avg)/4 – – ns

tRDQDQSH DQ hold time after DQS (for read) tCK(avg)/4+0.2 – – ns

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USB Host Interface AC Timing Characteristics


®


USB Host Interface AC Timing Characteristics

Table 20: USB 2.0 Host Interfaces Timing Parameters


Baud Rate BPS – 480 – Mbps –

Units Interval UI – 2083 – ps –

Receiver – HS mode

Receiver Jitter Tolerance Δ THSRX –0.15 – 0.15 UI –

Transmitter–HS mode

Output Rise Time THSR 500 – – ps 10% to 90%

Output Fall Time THSF 500 – – ps 90% to 10%

TX Output Jitter Δ THSTX –0.05 – 0.05 UI –

Table 21: USB 1.1 Timing Parameters

Parameter Symbol Condition

Value

UnitsMin Typ Max

Baud Rate BPS – – 12 – Mbps

Units Interval UI – – 83.33 – ns

RX Jitter Tolerance TJR1 To next transition

–18.5 – 18.5 ns

RX Jitter Tolerance TJR2 For paired transitions

–9 – 9 ns

Output Rise Time TFSR 10 to 90% 4 – 20 ns

Output Fall Time TFSF 10 to 90% 4 – 20 ns

Note: For details, see the USB 1.1 Specification, Section 7.3.2, Tables 7-5 and 7-6.

4/12/2011 DXKOG

PCIe Interface Timing


®



PCIe_REFCLKP/N TimingFigure 9 shows PCIe_REFCLKP/N timing.

Figure 9: PCIe_REFCLKP/N Timing

PCIe[1:0]_RDP/N Timing

Figure 10 shows PCIe[1:0]_RDP/N timing.

Figure 10: PCIe[1:0]_RDP/N Timing

Table 22: PCIe_REFCLKP/N Timing


FREQ Frequency (1/TCYCLE) – 100 – MHz

TOL Tolerance –50 – +50 ppm

VID Differential peak-to-peak amplitude 1.32 – 1.70 VP-P

tR/tF Rise/Fall time – – 1.0 ns

tJ Max RMS (10 kHz to 50 MHz) – – 4.7 ps

PCIe_REFCLKP/N

TCYCLE

TFTR TJ

PCIe[1:0]_RDP/NTJITTER

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®


PCIe[1:0]_TDP/N Timing

Figure 11 shows PCIe[1:0]_TDP/N timing.

Figure 11: PCIe[1:0]_TDP/N Timing

Table 23: PCIe[1:0]_RDP/N Timing


FREQ Baud rate – 2.5 – GBaud

ZIN Input impedance (differential) – 100 – ΩVID Differential peak-to-peak input voltage 175 – 2000 mVP-P

tJ Jitter tolerance (minimum RX EYE width) 0.4 – – UI

Table 24: PCIe[1:0]_TDP/N Timing


FREQ Baud rate – 2.5 – GBaud

ZOUT Output impedance (differential) – 100 – ΩVOD Differential peak-to-peak output voltage – – 1200 mVP-P

TR/TF Output rise/fall time (20% to 80%) 0.125 – – UI

tJ Output jitter (minimum TX EYE width) 0.7 – – UI

PCIe[1:0]_TDP/N

TR TF

TJITTER

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MII Interface Timing


®


MII Interface TimingThis section shows timing information for the MII Interface pins.

MII Input Timing

Figure 12: MII Input Timing

Table 25: MII Input Timing


t401 GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising setup time

10 – – ns

t402 GMAC_RXC clock period (10BASE-T mode) – 400 – ns

GMAC_RXC clock period (100BASE-TX mode) – 40 – ns

t403 GMAC_RXC high/low time (10BASE-T mode) 160 – 240 ns

GMAC_RXC high/low time (100BASE-TX mode) 16 – 24 ns

t404 GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising hold time 10 – – ns

– Duty cycle 40 50 60 %

GMAC_RXCLK

GMAC_RXDV

GMAC_RXD[3:0]

t401

t402

t403 t404

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MII Interface Timing


®


MII Output Timing

Figure 13: MII Output Timing

Table 26: MII Output Timing


t405 GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] valid 0 – 25 ns

t406 GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] invalid (hold)

0 – – ns

GMAC_TXCLK

GMAC_TXEN

GMAC_TXD[3:0]

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RGMII Interface Timing


®


RGMII Interface TimingThe following specifies timing information for the GMAC interface pins when configured in RGMII mode.

RGMII Output Timing (Normal Mode)RGMII output timing defaults to the normal mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled low at power-on reset.

Figure 14: RGMII Output Timing (Normal Mode)

Table 27: RGMII Output Timing (Normal Mode)


– GMAC_TXCLK clock period (1000M mode) 7.2 8.0 8.8 ns

– GMAC_TXCLK clock period (100M mode) 36 40 44 ns


t201 Tskew: Data to clock output skew –500 (1000M) – +500 (1000M) ps

– Duty cycle for 1000M (GE) 45 50 55 %

– Duty cycle for 10/100M (FE) 40 50 60 %

Note: The output timing in 10/100M operation is always as specified in the delayed mode.

GMAC_TXCLK

GMAC_TXD[3:0]

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®


RGMII Output Timing (Delayed Mode)RGMII output timing is set to the delayed mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled high at power-on reset.

Figure 15: RGMII Output Timing (Delayed Mode)

Table 28: RGMII Output Timing (Delayed Mode)


– GMAC_TXCLK clock period (1000M mode) 7.2 8.0 8.8 ns



t201D Tsetup, data valid to clock transition:Available setup time at the output source (delayed mode)

1.2 (all speeds) 2.0 – ns

t202D Thold, clock transition to data valid:Available hold time at the output source (delayed mode)

1.2 2.0 – ns



GMAC_TXCLK (internal)

Delayed GMAC_TXCLK (actual output

at source)

GMAC_TXD[3:0]

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®


RGMII Input Timing (Normal Mode)RGMII Input Timing defaults to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled low at power-on reset. The receive clock will not be delayed with 2 ns internally.

Figure 16: RGMII Input Timing (Normal Mode)

Table 29: RGMII Input Timing (Normal Mode)


– GMAC_RXCLK clock period (1000M mode) 7.2 8.0 8.8 ns

– GMAC_RXCLK clock period (100M mode) 36 40 44 ns

– GMAC_RXCLK clock period (10M mode) 360 400 440 ns

t301 Tsetup, input setup time: valid data to clock 1.0 2.0 – ns

t302 Thold, input hold time: clock to valid data 1.0 2.0 – ns



GMAC_RXD[3:0]

GMAC_RXCLK (actual)

GMAC_RXCLK (internal)

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®


RGMII Input Timing (Delayed Mode)RGMII Input Timing is set to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled high at power-on reset. The receive clock will be delayed with 2 ns internally.

Figure 17: RGMII Input Timing (Delayed Mode)

Table 30: RGMII Input Timing (Delayed Mode)


t301D Tsetup, input setup time (delayed mode) -1.0 (10/100/1000M) – – ns

t302D Thold, input hold time (delayed mode) 3.0 (1000M) – – ns

9.0 (10/100M) – – ns

GMAC_RXCLK (internal)

GMAC_RXD[3:0]

Delayed GMAC_RXCLK (actual output at destination)

4/12/2011 DXKOG

SGMII/SerDes Serial Interface


®


SGMII/SerDes Serial InterfaceThis subsection specifies timing information for the serial interface.

Serial Interface Output Timing

Figure 18: Serial Interface Output Timing

Table 31: Serial Interface Output Timing


t801 Transmit Data Signaling Speed – 1.25 – GBaud

t802 Transmit Data Rise Time (20%-80%) 100 – 200 ps

t803 Transmit Data Fall Time (20%- 80%) 100 – 200 ps

t804 Transmit Data Output Differential Skew – 0 – ps

t805 Transmit Data Total Jitter – – 0.24 UI

SGMII_TXDP

t802

SGMII_TXDN

t803 t805

4/12/2011 DXKOG

SGMII/SerDes Serial Interface


®


Serial Interface Input Timing

Figure 19: Serial Interface Input Timing

Table 32: Serial Interface Input Timing


t806 Receive Data Signaling Speed – 1.25 – GBaud

t808 Receive Data Jitter (peak-to-peak) – – 0.6 UI

SGMII_RXDP

SGMII_RXDN

t808

4/12/2011 DXKOG

I8S/TDM Audio/Video AC Specification


®


I8S/TDM Audio/Video AC Specification

Figure 20: IXS Transmitter Timing

Figure 21: IXS Receiver Timing

ITable 33: IXS Receiver Timing

Parameter Description Min Max Units Conditions

Tcyc TDM[1:0]_BITCLK frequency DC 75 MHz Programmable

Tperiod TDM[1:0]_BITCLK period 13.33 – ns –

Thigh TDM[1:0]_BITCLK high 5.33 8 ns –

Tlow TDM[1:0]_BITCLK low 5.33 8 ns –

Tduty_cyc TDM[1:0]_BITCLK duty cycle 40 60 % –

Tpd TDM[1:0]_BITCLK to TDM[1:0]_WS or TDM[1:0]_SDIO delay

– 3 ns Output mode

Tsetup TDM[1:0]_WS or TDM[1:0]_SDIO setup time 2 – ns Input mode

Thold TDM[1:0]_WS or TDM[1:0]_SDIO hold time 2 – ns Input mode

Tperiod

ThighTlow

Tpd

TDM[1:0]_BITCLK

TDM[1:0]_WS or TDM[1:0]_SDIO

Tperiod

ThighTlow

Tsetup Thold

TDM[1:0]_BITCLK

TDM[1:0]_WS or TDM[1:0]_SDIO

4/12/2011 DXKOG

JTAG Interface


®


JTAG InterfaceJTAG timing is synchronous to the JTCK clock.

Figure 22: JTAG Interface

Table 34: JTAG Interface


TCYCLE JTAG Cycle Time 50 – – ns

TSU Input Setup Time 10 – – ns

TH Input Hold Time 10 – – ns

TOD Output Delay Time Measured from Falling Edge of JTCK – – 22 ns

4/12/2011 DXKOG

MDC/MDIO Master Interface


®


MDC/MDIO Master InterfaceMDIO timing is synchronous to the MDC clock. The BCM4706 is an MDC/MDIO master device that drives the MDC clock.

Figure 23: MDC/MDIO Master Interface

Table 35: MDC/MDIO Master Interface


t1 MDC cycle time, software programmable 40/60a

a. Six internal reference clock cycles, which is 40 ns.

– – ns

t2 MDIO output delay from MDC falling – – 15 ns

t3 MDIO input setup time to MDC rising 20 – – ns

t4 MDIO input hold time to MDC rising 0 – – ns

MDC

MDIO (out)

MDIO (in)

t1

t3 t4

t2

4/12/2011 DXKOG

SPI Master Interface


®


SPI Master InterfaceBCM4706 GPIO pins can be configured as SPI master interfaces to connect up to three SPI slaves. This supports all four combinations of clock phase and polarity.

Timing Parameters for CPHA=0

Figure 24: SPI Master Interface: Timing Parameters for CPHA=0

Table 36: SPI Master Interface


tp SCLK period, software programmable 80 – – ns

t1 Minimum leading time before the first SCLK edge – 1.5 – tp

t2 Minimum trailing time after the last SCLK edge – 0.5 – tp

t3 MOSI output delay from SCLK clock falling/rising (CPOL=0/1)

– – 10 ns

t4 MISO input setup time to SCLK clock rising/falling (CPOL=0/1)

10 – – ns

t5 MISO input hold time to SCLK clock rising/falling (CPOL=0/1) 10 – – ns

SCLK(GPIO0)

tp

t3

t4

t1SS0/1/2(GPIO1/8/9)

MOSI(GPIO2)

MISO(GPIO3)

t2

t5

CPOL=1

CPOL=0

CPOL=1

CPOL=0CPHA=0

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SPI Master Interface


®


Timing Parameters for CPHA=1

Figure 25: SPI Master Interface: Timing Parameters for CPHA=1

Table 37: Timing Parameters for CPHA=1


tp SCLK period, software programmable 80 – – ns

t1 Minimum leading time before the first SCLK edge – 1 – tp

t2 Minimum trailing time after the last SCLK edge – 1 – tp

t3 MOSI output delay from SCLK clock rising/falling (CPOL=0/1)

– – 10 ns

t4 MISO input setup time to SCLK clock falling/rising (CPOL=0/1)

10 – – ns

t5 MISO input hold time to SCLK clock falling/rising (CPOL=0/1)

10 – – ns

SCLK(GPIO0)

tp

t3

t4

t1SS0/1/2(GPIO1/8/9)

MOSI(GPIO2)

MISO(GPIO3)

t2

t5

CPOL=1

CPOL=0

CPOL=1

CPOL=0CPHA=1

4/12/2011 DXKOG

Thermal Specifications


®


Section 5: Thermal Specifications

This section describes the device thermal specifications. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

BCM4706This subsection describes BCM4706 device thermal specifications.

BCM4706 Thermal Specifications Without External Heatsink at 70°CTable 38 and Table 39 show the simulation and thermal performance data on the 2s2p board, without external heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

Table 38: Package for 2s2p Board, TA = 70°C, P = 2.7W from Simulation

Parameter Value

Device power dissipation, P(W) 2.70

Ambient air temperature TA (°C) 70

θJA in still air (°C/W) 21.43

θJB (°C/W) 9.80

θJC (°C/W) 8.81

Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70°C

Air Velocity

TJ_max (°C) TT_ (°C) θJA (°C/W) ΨJT (°C/W) ΨJB (°C/W)m/s ft/min

0 0 127.86 109.20 21.43 6.91 12.25

0.508 100 122.36 103.65 19.39 6.93 12.16

1.016 200 119.63 100.86 18.38 6.95 12.05

2.032 400 116.60 97.73 17.26 6.99 11.89

3.048 600 114.87 95.93 16.62 7.02 11.78

4/12/2011 DXKOG

BCM4706


®


BCM4706 Thermal Specifications with External Heatsink at 70°CTable 40 and Table 41 show the simulation and thermal performance data with the 30x30x25 mm external heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

Table 40: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 70°C, P = 2.7W from Simulation

Parameter Value




θJB (°C/W) 9.80

θJC (°C/W) 8.81

Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70°C

Air Velocity


0 0 111.39 90.63 15.33 7.69 9.77

0.508 100 101.31 79.98 11.59 7.90 9.08

1.016 200 99.42 77.98 10.90 7.94 8.94

2.032 400 98.31 76.83 10.48 7.96 8.87

3.048 600 97.81 76.32 10.30 7.96 8.85

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BCM4706


®


BCM4706 Thermal Specifications Without External Heatsink at 85°CTable 42 and Table 43 show the simulation and thermal performance data on the 2s2p board, without external heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

Table 42: Package for 2s2p Board, TA = 85° C, P = 2.7 W from Simulation

Parameter Value




θJB (°C/W) 9.80

θJC (°C/W) 8.81

Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85°C

Air Velocity


0 0 142.86 124.20 21.43 6.91 12.25

0.508 100 137.36 118.65 19.39 6.93 12.16

1.016 200 134.63 115.86 18.38 6.95 12.05

2.032 400 131.60 112.73 17.26 6.99 11.89

3.048 600 129.87 110.93 16.62 7.02 11.78

4/12/2011 DXKOG

BCM4706


®


BCM4706 Thermal Specifications with External Heatsink at 85°CTable 44 and Table 45 show the simulation and thermal performance data with the 30x30x25 mm external heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.

Table 44: Package with 30x30x25 mm External Heat Sink on 2s2p Board, TA = 85°C, P = 2.7W from Simulation

Parameter Value




θJB (°C/W) 9.80

θJC (°C/W) 8.81

Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85°C

Air Velocity


0 0 126.39 105.63 15.33 7.69 9.77

0.508 100 116.31 94.98 11.59 7.90 9.08

1.016 200 114.42 92.98 10.90 7.94 8.94

2.032 400 113.31 91.83 10.48 7.96 8.87

3.048 600 112.81 91.32 10.30 7.96 8.85

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Mechanical Information


®


Section 6: Mechanical Information

BCM4706

Figure 26: BCM4706 Mechanical Information

4/12/2011 DXKOG

Ordering Information


®


Section 7: Ordering Information

Table 46: Ordering Information

Part Number Package Ambient Temperature

BCM4706KPBG 23 mm x 23 mm 484-pin PBGA (Lead-free) 0° to 70°C

4/12/2011 DXKOG

®

Phone: 949-926-5000Fax: 949-926-5203E-mail: [email protected]: www.broadcom.com

BROADCOM CORPORATION5300 California AvenueIrvine, CA 92617© 2010 by BROADCOM CORPORATION. All rights reserved.

4706-DS00-R June 02, 2010

Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.


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