4.ece301 - lexical conventions of verilog hdl

7/27/2019 4.ECE301 - Lexical Conventions of Verilog HDL

1/25

VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Lexical Conventions of Verilog HDL

Prof.S.Sivanantham

VIT University

Vellore, Tamilnadu. India

E-mail: [email protected]


2/25

Objectives

After completing this lecture, you will be able to:

Explain the rules and regulations for comments, white space and

identifiers

Appropriately and effectively utilize Verilog operators

ECE301 VLSI System Design FALL 2011 S.Sivanantham


3/25

Lexical Conventions

Lexical conventions

Comments

Numbers Strings

Identifier

Operators



4/25

Comments and Spacing

/ / A one- l i ne comment st ar t s wi t h / / and ends wi t h newl i ne char act er/ * A bl ock comment st ar t s anywher e wi t h / *

and ends anywher e wi t h */ Do not clutter your source

modul e muxadd ( a, b, sel , sum, carry, y) ;i nput a, b, sel ; / / modul e i nput sout put / * modul e out put s * / sum, carry, y;. . .

obvious!

/ / Ver i l og i s a f r ee- f or mat l anguage

/ / Whi t e space i s needed onl y t o separat e some l anguage t okensUse addi t i onal whi t e s ace t o enhance r eadabi l i t

assi gn sum = a ^ b;assi gn carry = a & b;

/ / Al so use i ndent at i on 2 s ace i s best t o enhance r eadabi l i t

al ways @( a or b or sel )i f ( sel == 1)

y = b;el se

ECE301 VLSI System Design FALL 2011 S.Sivanantham 1.4

y = a;

. . .


5/25

Lexical Conventions: Identifiers

Identifiers

Names iven to ob ects

Cannot start with a number or dollar sign ($) Can start with alphabetic character or underscore

wire a1; // wire is a keyword, a1 is an identifier,



6/25

Identifier Naming Rules

Identifiers start with a letter or an

underscore (_)

Subsequent characters may be letter,

Not Legal Legal

unit-32 unit 32digit, dollar sign ($) or underscore

Verilog does not restrict name length

Tool or methodology may restrict

_

16_bit_bus bus_16_bits$abc abc$

name engt

Identifiers are case sensitive

ABC, Abc, abc are all different

Escaped

\unit-32ega names \16_bit_bus

\$abc

Keywords are

all lowercase



7/25

Lexical Conventions: Numbers (1)

Sized numbers are represented as

'

number of bits in the number

Le al base formats are decimal 'd or 'D , hexadecimal 'h

or 'H), binary ('b or 'B) and octal ('o or 'O).

Examples` - t nary num er

16`hcdab // 16-bit hexadecimal number

3`d7 // 3-bit decimal number

Unsized numbers 16549 // 32-bit decimal number by default

'


-

`o21 // 32-bit octal number


8/25


x or z values : Verilog has two symbols for unknown and high

impedance values.

x unknown value

z high impedance value

Examples:

` -

significant bits unknown

6'hx // This is a 6-bit hex number 32'bz // This is a 32-bit

high impedance number

Negative numbers

Number with a minus sign before the size of a constant number

-6'd3 // 8-bit negative number stored as 2's complement of 3

4'd-2 // Illegal specification



9/25


Underscore, Question mark

character an where in a number exce t the first_

character 16`b1010_0110_1101

readability 4'b10?? // Equivalent of a 4'b10zz



10/25

Lexical Conventions: Numbers - Examples

Number Decimal E uivalent Actual Binar

4d3 3 00118ha 10 00001010

5b111 7 00111

8b0101_1101 93 010111018bx1101 - xxxx1101

-8d6 -6 11111010

Numbers with MSB ofxorzextended with that value

8`b01??_11?? equivalent to a 8`b01zz_11zz



11/25

Lexical Conventions: Strings

A string is a sequence of characters that are enclosed by

double quotes.

The restriction on a string is that it must be contained on asingle line, that is, without a carriage return. It cannot be on

.

Strings are treated as a sequence of one-byte ASCII values.

Examples:

Verilog HDL Concepts



12/25

Operators

Topics:

Category Symbol(s)

reduction & ~& | ~| ~ ~arithmetic ** * / % + -

shift > >relational < > =

bit-wise ~ & | ~logical ! && | |

conditional ?:concatenation {}replication {{}}



13/25

Unary Reduction Operators

and &

or |

xor ^

modul e r educt i on;l ocal par am [ 3: 0] CONST_A = 4 b0100,

CONST_B = 4 b1111;

nand ~&

nor ~|

xnor ~ ~

r eg va ;

i ni t i albegi n

val = &CONST A ; / / 0

Reduction operators perform a bit-

wise operation on all the bits of a

_val = | CONST_A ; / / 1val = &CONST_B ; / / 1val = | CONST_B ; / / 1

val = CONST_A ; / / 1

single operand

The result is always 1 b0, 1 b1 or1 bX

_ val = ~| CONST_A; / / 0val = ~&CONST_A; / / 1val = CONST_A && &CONST_B; / / 1

end

endmodul e



14/25

Arithmetic Operators

Verilog-1995:

add +

subtract -

modul e ar i t hops;l ocal par am i nt eger CONST_I NT = - 3,

CONST_5 = 5;l ocal par am [ 3: 0] r ega = 3,

multiply *

divide / modulus %

r eg = ,

r egc = 14;

i nt eger val ;r e [ 3: 0] num;

n n eger s s gne

A reg is unsigned

-

i ni t i albegi n

val = CONST_5 * CONST_I NT; / / - 15

power operator **

You can declare a reg signed

You can cast between si ned and

_ val = CONST_5/ CONST_I NT; / / - 1num = r ega + r egb; / / 1101num = r ega + 1; / / 0100num = CONST_I NT; / / 1101

unsigned expressions using $signedand$unsigned

num = r egc % r ega; / / 0010end

endmodul e



15/25

Shift Operators

Verilog-1995:

logical shift >

modul e shi f t ;r eg [ 7: 0] r ega = 8 b10011001;r eg si gned [ 7: 0] r egs = 8 b10011001;r eg [ 7: 0] r egb;

Ignores operand signs

Fills extra bits with 0

Implements division or

i ni t i albegi n

r egb = r ega > 1; / / 01001100

Verilog-2001:

r egb = r egs > 1; / / 11001100r egb = r ega


16/25

Relational Operators

less than

less than or equal to =

The result is:

n t abegi n

r ega = 4 b0011;r egb = 4 b1010;r e c = 4 b0x10;

1 b0 if the relation is false

1 b1 if the relation is true

1 bx if either o erand contains an

val = r egc > r ega ; / / val = Xval = r egb < r ega ; / / val = 0

val = r egb >= r ega; / / val = 1

z or x bits

end

endmodul e



17/25

Logical Equality and Case Equality Operators

logical equality ==

Result can be unknown

. . .a = 2 b1x;b = 2 b1x;

a ==/ / val ues mat ch & do not cont ai n Z or X

el se/ / val ues do not mat ch or cont ai n Z or X/ / above val ues execut e t hi s el se br anch

0 1 0 X X

1 0 1 X XZ X X X X

case equality ===

Result is always known. . .

a = b1x;b = 2 b1x;

i f ( a === b)/ / val ues mat ch exact l

0 1 Z X0 1 0 0 0

/ / above val ues execut e t hi s el se br anchel se

/ / val ues do not mat ch

Z 0 0 1 0X 0 0 0 1


the case statement matches

items this way.


18/25

More about Equality Operators

logical equality ==

logical inequality ! =

case equality ===

modul e equal i t i es;r eg [ 3: 0] r ega, r egb, r egc;r eg val ;

case inequality ! ==

For lo ical e ualities the result is

n t abegi n


always 1 b0, 1 b1 or1 bX

For case equalities, the result is

always 1 b0 or1 b1

val = r ega == r egb; / / val = 0val = r ega ! = r egb; / / val = 1

val = r egb ! = r egc; / / val = X

val = r ega === r egb; / / val = 0val = r ega ! == r egc; / / val = 1val = r egb === r egc; / / val = 0val = r egc === r egc; / / val = 1

end

endmodul e



19/25

Bit-Wise Operators

not ~

and &

or |

modul e bi t wi se;r eg [ 3: 0] r ega, r egb, r egc;r eg [ 3: 0] num;

xor ^

xnor ~

xnor ~

n t abegi n


Bit-wise operators operate on

vectors

num = ~r ega; / / num = 0110num = r ega & 0; / / num = 0000

num = r ega & r egb; / / num = 1000

Operations are performed bit by bit

on individual bits

Unknown bits in an operand do not

num = r egb & r egc; / / num = 10x0num = r egb | r egc; / / num = 1110

end

necessarily lead to unknown bits inthe resultendmodul e



20/25

Logical Operators

not !

and &&

or | |

modul e l ogi cal ;l ocal par am i nt eger FI VE = 5;l ocal par am [ 3: 0] CONST_A = 4 b0011,

CONST_B = 4 b10xz,

Logical operators interpret theiroperands as either true (1 b0) or false

N T_ = z x;r eg ans;

i ni t i albe i n

(1 b1) or unknown (1 bX)

0 if all bits 0

1 if any bit 1

ans = ! CONST_A; / / 0ans = CONST_A && 0; / / 0ans = CONST_A | | 0; / / 1

ans = CONST_A && FI VE; / / 1

X if any bit is Z orX and no bit is 1 _ _

ans = CONST_C | | 0; / / Xend

endmodul e



21/25

Conditional Operator

conditional ?: modul e t r i buf 1 ( a, en, y) ;i nput a, en;out put y;assi gn y = en ? a : 1 bZ;

en mo u e

modul e t r i buf 2 ( a, en, y) ;i nput a, en;

a y

out put r eg y;al ways @( a or en)

y = en ? a : 1 bZ;

endmodul e

en

modul e t r i buf 3 ( a, en, y) ;i nput a, en;out put r eg y;

i f ( en)y = a;

el sey = 1 bZ;

Sometimes the conditional

operator is more readable thanthe i f statement. Sometimes


en mo u e...


22/25

Concatenation Operator

concatenation {}

Can select and join bits from

different vectors to form a new

modul e concat enat i on;r eg [ 7: 0] r ega, r egb, r egc, r egd, new;r eg [ 3: 0] ni b1, ni b2;

i ni t i al

vector

Can reorganize vector bits to form anew vector

begi nr ega = 8 b00000011;r egb = 8 b00000100;r egc = 8 b00011000;r egd = 8 b11100000;

en an swaps

rotate

Can use on either side of an

new = {r egd[ 6: 5] , r egc[ 4: 3] , r egb[ 3: 0] };/ / new = 8 b11_11_0100

new = {2 b11, r egb[ 7: 5] , r ega[ 4: 3] , 1 b1};new = 8 b11 000 00 1 _ _ _

new = {r egd[ 4: 0] , r egd[ 7: 5] };/ / r ot at e r egd r i ght 3 pl aces/ / new = 8 b00000_111

{ni b1, ni b2} = r ega;/ / ni b1 = 4 0000, ni b2 = 4 0011

end

Literals in a concatenation must be


uexplicitly sized so that all the bits gointo the correct position.


23/25

Replication Operator

replication {{}}

Reproduces a concatenation a set

number of times

modul e r epl i cat e;r eg r ega = 1 b1;r eg [ 1: 0] r egb = 2 b11;r eg [ 3: 0] r egc = 4 b1001;r eg [ 7: 0] bus;

Syntax:

{const_expr {sized_expr}}

The constant number of repetitions

i ni t i albegi n

/ / si ngl e bi t r ega r epl i cat ed 8 t i mes

mus no ave or va ues us = r ega ;/ / bus = 11111111

/ / 4x r ega concat enat ed wi t h 2x r egc[ 1: 0]

bus = { {4{r ega}}, {2{r egc[ 1: 0] }} };bus = 1111 01 01 _ _

/ / r egc concat enat ed wi t h 2x regbbus = { r egc, {2{r egb}} };/ / bus = 1001_11_11

/ / r egc concat enat ed wi t h 2x 1 b1/ / and r epl i cat ed 2 t i mesbus = { 2{r egc[ 2: 1] , {2{1 b1}}} };/ / bus = 00_1_1_00_1_1


endmodul e


24/25

Reference: Operator Precedence

Reliance on operator precedence may make your code unreadable use parentheses!

Category Symbol(s)

^ ^ ^nary - ~ & ~& ~ ~ ~

Exponential ** Arithmetic * / % + - ( bi nar y)

Relational < >= Equality == ! = === ! ==

Bit-wise & ( bi nar y)^ ~ ~ nar y

| ( bi nar y) Logical && | |

on ona : Concatenation / Replication { } {{ }}



25/25

Review

How wide is the result of a logical &&operation?

Explain the difference between the &&and&operators.

TRUE or FALSE: You must ex licitl size literals in a concatenation.

Given r egx = 4 b0101; what is the value ofbus = 2 r e x 3: 1 3 1 b0 r e x 0

Assume you have stored a four bit signed number in the unsigned

preserves the sign bit.


4.ece301 - lexical conventions of verilog hdl

Documents