4.test generation comb 2

7/25/2019 4.Test Generation Comb 2

1/46

1

ehrdad Nourani

Dept. of EEUniv. of Texas at Dallas

EEDG/CE 6303: Testing and Testable Design


2/46

2

Test Generation for

Combinational Circuits

Session 04


3/46

3

Fault Analysis System (Review)

Fault Collapsing

TestGeneration

Fault Simulation


4/46

4

Test Generation Techniques

There are two main test vector generationtechniques

1. Non-Structural

Analyzes the gate-level description of a circuit and implicitlyenumerate all possible input combinations to find a testvector for a target fault.

2. Structural

Analyzes the structure of a given circuit to generate a testvector for a given target fault, or declare it untestable.


5/46

5

Structural Test Generation


6/46

6

Test Generation Techniques (Review)

There are two main test vector generationtechniques

1. Non-Structural

Analyzes the gate-level description of a circuit and implicitlyenumerate all possible input combinations to find a testvector for a target fault.

2. Structural

Analyzes the structure of a given circuit to generatea test vector for a given target fault, or declare ituntestable.


7/46

7

Motivation

Consider a 64-bit ripple-carry adder


8/46

8

Motivation (cont.)

Functional (exhaustive) ATPGgenerate complete set

of tests for circuit input-output combinations 129 inputs, 65 outputs:

2129= 680,564,733,841,876,926,926,749,214,863,536,422,912patterns

Using 1 GHz ATE, would take2.15 x 1022

years Structural test:

No redundant adder hardware, 64 bit slices

Each with 27 faults (using fault equivalence)

At most 64 x 27 = 1728 faults (tests)

Takes 0.000001728 son 1 GHz ATE

Designer gives small set of functional testsaugmentwith structural tests to boost coverage to 98+%


9/46

9

Algebra for Structural Test

Represent two machines, which are simulatedsimultaneously by a computer program:

Good circuit machine (1stvalue)

Bad circuit machine (2ndvalue)

Better to represent both in the algebra:

Need only 1 pass of ATPG to solve both

Good machine values that preclude bad machine

values become obvious sooner & vice versa


10/46

10

Circuit Representation

Its more efficient to carry (simulate) fault-freeand faulty values at the same time.

&

&

&

&

x1

x2

c2

c3

c1

c4

c5

c6

c7

c8

c9

z

0

1

1

1

0

11

1

0

1

G1

G2

G3

G4

0

1

SA1

&

&

&

&

x1

x2

c2

c3

c1

c4

c5

c6

c7

c8

c9

z

0

1

1

1

0

11

1

1

0

G1

G2

G3

G4

0

1

SA1

&

&

&

&

x1

x2

c2

c3

c1

c4

c5

c6

c7

c8

c9

z

0/0

1/1

1/1

1/1

0/0

1/11/1

1/1

0/1

1/0

G1

G2

G3

G4

0/0

1/1


11/46

11

Algebra for Structural Test (cont.)

Roths 5-Valued and Muths 9-Valued Algebra

Symbol Meaning Fault-Free(Good)

Faulty(Bad)

0 0/0 0 0

1 1/1 1 1

D 1/0 1 0

D 0/1 0 1

X X/X X X

G0 0/X 0 X

G1 1/X 1 X

F0 X/0 X 0

F1 X/1 X 1

5-Valued 9

-Value

d


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12

Operations in Multi-Valued Logic

Examples (2-input AND and OR gates)

e.g. D+0=1/0+0/0=1/0=D


13/46

13

Path Sensitization

Three key tasks are needed

1. Fault Sensitization (Stimulation)

2. Fault (Effect) Propagation

3. Line Justification

Forward and Backward Implications

Examples of Backward

Implications

Examples ofForward

Implications


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14

Path Sensitization Example

Propagate through top path

1

0

D

D

1

D

D

No Way to

justify this line


15/46

15

Path Sensitization Example (cont.)

Propagate through top and bottom paths

simultaneously

1

D

D

D

D

1

D

No Way to

propagate fault

1


16/46

16

Path Sensitization Example (cont.)

Propagate through the bottom path

simultaneously

1

D

0

D

D

Success

1

D

D

1

D

Test Pattern

Found


17/46

17

History of Algorithms

Algorithm

D-ALG

PODEMFAN

TOPS

SOCRATES

Waicukauski et al.

EST

TRAN

Recursive learning

Tafertshofer et al.

Est. speedup over D-ALG

(normalized to D-ALG time)

1

723

292

1574 ATPG System

2189 ATPG System

8765 ATPG System

3005 ATPG System

485

25057

Year

1966

19811983

1987

1988

1990

1991

1993

1995

1997


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18

Another Look at Value System

In general, 16 distinct sets of four basic values can be

obtained, namely, all subsets of {0, 1, D, }{0, 1, D, D}

{0, 1, D} {0, 1, D} {0, D, D} {1, D, D}

{0, 1} {0, D} {0, D} {1, D} {1, D} {D, D}

{0} {1} {D} {D}

{}


19/46

19

Symbols Used in Value Systems

In the five-valued

system Unique symbols05,

15, D5, and 5are

assigned to each set

denoting a completely-specified value

One single symbolX5denotes all sets with

more than one basicvalue


20/46

20

Symbols Used in Value Systems (cont.)

In the six-valued

system Unique symbols06, 16, D6,

and 6are assigned toeach set denoting acompletely-specified value

One single symbol6denotes the set {0, 1}, i.e.,the only incompletely-specified set that does notcontain Dor

One single symbolX6denotes all sets with morethan one basic value(including {0, 1})


21/46

21

Behavior of Gates Using Multi-Valued System

2-Input NAND2-Input NOR

2-Input XOR A fanout system


22/46

22

6-Valued Cube Cover

A cuberepresents a

combination of inputs. singular cover:cubes with 06

or 16at output (i.e., no faulteffect)

propagation cubes:cubes withD6or at output

cube cover: together, all thecubes

2-Input NAND


23/46

23

Fault Excitation Cubes

For test generation for single stuck-at fault in a

combinational circuit Only fault-free values may appear at the inputs of

faulty circuit element

It is necessary to apply a combination of values atthe inputs of the faulty element that can cause a D

or to appear at its outputs

Fault excitation cubescapture this aspect of afaulty circuit element


24/46

24

Fault Excitation Cubes (cont.)

Two-input NAND with

output SA1Two-input NAND with

output SA0 Two-input NAND withinput ci1SA1

A fanout system with

branch cjlSA1

A fanout system with stem

SA1


25/46

25

More Cube Covers

NANDORAND XOR

Fanout System


26/46

26

More Fault Excitation Cubes

2-Input NAND

2-Input XOR

Fanout System

output SA0output SA1 input ci1SA0input ci1SA1

output SA0output SA1 input ci1SA0input ci1SA1

stem ciSA1 stem ciSA0

branch cjlSA1 branch cjlSA0


27/46

27

Test Generation Basics

Fault effect excitation (FEE)is the process

of creating a fault effect (Dor ) at one ormore outputs of the faulty circuit element

Fault effect propagation (FEP) is the

process of assigning values to circuit lines suchthat a fault-effect propagates from an outputof the faulty circuit element to a primaryoutput

One or more paths must exist between the fault siteand a primary output, such that every line along thepath has D6or 6


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28

Test Generation Example

In our example, only a single path c1c6z

exists for such propagation, i.e., FEP via G6and G8necessary

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA006

06

D6

Fault excitation cube for G1


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29

Test Generation Example (cont.)

To propagate via G6, first use propagation cubes for G6

Next, eliminate rows incompatible with currentlyassigned values

Make one of the remaining assignments

Only one remained in this case

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA00

6

06

D6 Propagation cubes for

G6


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30


Similarly, propagate via G8

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA00

6

06

D6 Propagation cubes for

G8


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31


Justificationis the task of assigning values to primary inputs so as

to imply a desired value at an internal lineValues at c2and c7are notjustified

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x 10

c1

c2

c3

c4

c5

c6

c7

z

G 1

G 2

G 3

G 4

G 5

G7

G6

G 8

SA00

6

06

D6

06

D6

06

D6

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA 00

6

06

D6

06

D6

06

D6

16

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x 10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA00

6

06

D6

06

D6

06

D6

16

06

06

06

06

06

06

16

16

16

Singular cover of G2


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32


Justificationis the task ofassigning values to primaryinputs so as to imply a desiredvalue at an internal line

Values at c2and c7are notjustified

Justify value at c2

Identify all cubes insingular cover of G2

Eliminate cubes notconsistent with currentlyapplied values

+ Two choices remaino Either 16at x3

o Or 16at x4

+ In this fanout-freecircuituse either one

Similarly, justify value at c7

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x 10

c1

c2

c3

c4

c5

c6

c7

z

G 1

G 2

G 3

G 4

G 5

G7

G6

G 8

SA00

6

0 6

D

6

06

D6

06

D6

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA 00

6

0 6

D

6

06

D6

06

D6

16

&

&

&

&

1

1

1

1

x1

x2

x3

x4

x5

x6

x7

x8

x9

x10

c1

c2

c3

c4

c5

c6

c7

z

G1

G2

G3

G4

G5

G7

G6

G8

SA00

6

0 6

D6

06

D6

06

D6

16

06

06

06

06

06

06

16

16

16

Singular cover of G2


33/46

33


Consider a circuit with fanouts for a more general case

Initialization: All lines in fanout of fault site X6, other lines 6

Fault-effect excitation

G1and G4as possible sites for FEP

D-frontieris a set of gates where each gate has

+ D6or 6at one or more inputs, and

+ X6at output

Each gate in D-frontier is a candidate for FEP

Here, D= {G1, G4}

1

G 2

1

G5

&

G1

1

G3

&

G6

G 4

SA0

x1

x 2

x 3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

6

6

X6

X6

X6

X6

X6X6

X6

X6

X6

X6

1

G 2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x 1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

6

6 X6

X6

X6

X6X6

X6

16

D6

D6

X6

X6

Fault excitation cubes for

fanout system with stem

x4with SA0 at x4


34/46

34


Since D= {G1, G4} has more than one gate

Select, only say, G1for FEP Perform FEP via G1

Assign 16at x3

Now the D-frontier D= {G2, G4}

1

G2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x 1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

6

6 X6

X6

X6

X6X6

X6

16

D6

D6

X6

X6

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

6 X6

X6

X6X6

X6

16

D6

D6

X6

X6

16 D6

Propagation cubes for

G1


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35


Since D= {G2, G4}

Select one, say G2 FEP via G2

Assign 06to x2

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

6 X6

X6

X6X6

X6

16

D6

D6

X6

X6

16 D6

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6X6

X6

16

D6

D6

X6

X6

16 D

6

06 D

6

Propagation cubes forG2


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36


Implications of currently assigned values

Only when a unique value can be identified

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6X6

X6

16

D6

D6

X6

X616 D6

06 D

6

Relevant partsof cube

covers of:

Fanout system with stem c4

NOT gate G3

XOR gate G4

OR gate G5

NAND gate G6

1

G2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6X6

X6

16

D6

D6

1 6 D6

06 D

6

D6

D6

1

G 2

1

G5

&

G1

1

G3

&

G6

G 4

SA0

x 1

x 2

x 3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6

X6

16

D6

D6

16 D6

06 D

6

D6

D6

D6

1

G2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x 1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6

16

D6

D6

16 D6

06 D

6

D6

D6

D6

06

1

G 2

1

G5

&

G1

1

G3

&

G6

G 4

SA 0

x 1

x 2

x 3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

16

D6

D6

16 D6

06 D

6

D6

D6

D6

06

16


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37


Current status

D= {G5}

But V(z) = 16, i.e., no possibility of obtaining D6or 6at

output

In other words, proceeding further will notlead to a test

vectorHence we must backtrack, i.e.,

Identify the most recent primary input valueassignment for which an untried alternative exists

+Restore the state to prior to that assignment wasmade

+Make the alternative value assignment


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38

Test generation basics

Identifying the most recent primary input value assignment for

which an untried alternative exists During assignment of 06to x2, alternative 16at x2untried

Executing backtrack

Restore circuit values to before 06was assigned to x2

Assign 16at x2(no more alternatives exist)

Perform implication

1

G 2

1

G5

&

G1

1

G3

&

G6

G 4

SA0

x1

x 2

x 3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

16

D6

D6

16 D

6

06 D

6

D6

D6

D6

06

16

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

X6X6

X6

16

D6

D6

X6

X6

16 D

6

06 D

61

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

6 X6

X6

X6X6

X6

16

D6

D6

X6

X6

16 D6

1

G2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x 1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

16

D6

D6

16 D6

16 1 6

16

16

06

6

D6


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39


Now D= {G6}

Select G6for FEP Objective 16at c9, which can be attained by 16at x1

+Assign 16at x1

Perform implication

1

G2

1

G 5

&

G1

1

G3

&

G6

G4

SA0

x 1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

6

X6

16

D6

D6

16 D6

16 1 6

16

16

06

6

D6

1

G2

1

G5

&

G1

1

G3

&

G6

G4

SA0

x1

x2

x3

x4

c1

c2

c3

c4

c5

c6

c7

c8

c9

z

16

D6

D6

16 D6

16 16

16

16

06

D6

16

16

D 6


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40


Now D6at output and no unjustified lines

Hence test generation complete with vector (16, 16,16, 16)

In reality, need to apply only the value correspondingto fault-free circuit in each of above composite values

That is, apply test (1, 1, 1, 1)


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41

Importance of Implication

Implicationis the process of determining logic values

that appear at circuit lines as a consequence of thevalues assigned to some of its lines

It also

Identifies any inconsistency between the values assigned

Updates D-frontier and list of unjustified lines An implication procedureiteratively uses

implication operation

A direct implicationoperation determines values at inputs oroutputs of a circuit element, given values assigned at theelements inputs and/or outputs

Forwardimplication operation proceeds from lines to those in itsfanout

Backwardimplication proceeds from lines to those in fanin


42/46

42

Importance of Implication (cont.)

Tabular method can be used to record/retrieve

the possibilities

c1

c2

c3

c4

c5

c6

c7

c8

1

G8

G6

G7

&

1


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43

Generic Test Generation Algorithm

1. Read the circuit under test (CUT)

2. Preprocessing

a. Identify static indirect implications

b. Compute testability metrics

3. For each target fault in the fault list

a. Insert the target fault by using the appropriate description of the behavior ofthe faulty element

b. Initialize circuit lines In five-valued system, assign X5to all lines

In six-valued system, assign X6to all lines in transitive fanout of fault siteand 6to all other lines

In sixteen-valued system

+ Assign {0, 1, D, } to all lines in transitive fanout of the fault site

+ Assign {0, 1} to all the other lines+ Perform forward implication starting at each output of the faulty circuit

element


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44

Generic Test Generation Algorithm (cont.)

c. Identify test generation sub-tasks (TGSTs) Analyze values at primary outputs of CUT and outputs of the

faulty circuit element Analyze gates in the D-frontier D Analyze the set of unjustified lines U

Determine, whether+ Test generation is completeprint vector, manage fault list, go to

Step 3 and process next fault

+ Conflict, i.e., not possible to generate a vector for target by furtherspecifying currently assigned vector (values)initiate backtrack+ Continue search by carrying out a TGST

1. FEEfault-effect excitation,2. FEPfault-effect propagation, or3. Justification

d. Identify a value assignment to accomplish the selected TGST

e. Assign selected value Save the state of the test generation: e.g., values at circuit

lines, untried alternatives TGSTs and/or value assignments Assign selected value Perform implications

+ If successful, continue

+ Else, backtrack


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45

Identification of TGSTs

Backtrack

Find the most recent value assignment at which an untried alternative existed

Restore the state of the test generation algorithm to prior to that value assignment

Make an alternative TGST/value assignment and try it, starting at Step 3d or 3e

Assignment of each logic value by test generator followed by implication that

Either returns CONFLICT and initiates backtrack

Else, returns SUCCESS after updating

Values at circuit lines

D-frontier D List of unjustified lines U

Subsequently, values at circuit lines, D, and Uare analyzed to identify TGSTs with followingpossible outcomes

Fault-effect excitation (FEE)

Fault-effect propagation (FEP)

Justification

Backtrack

FEE impossible

FEP impossible

Test generation complete


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Identification of TGSTs

Values at outputsof faulty circuit element

{0}, {1}, or {0, 1} at each output

Backtrack TGST: Fault excitation (necessary)One or more outputwith {D} or {D}

Otherwise

Values at CUT outputs

BacktrackOne or more outputwith {D} or {D}

Otherwise

Check unjustified lines

One or more l ines

NoneTGST: Justification of value at each unjustified line

(each justification task deemed necessary)

Identify fault effectpropagation objectives

TGST: One or more fault effectpropagation subtasks

(necessary if unique or if identifiedvia future uniqueD-drive analysis)

{0}, {1}, or {0, 1} at each output

4.test generation comb 2

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