2015 IMP & HIRFL Annual Report · 251 ·

many kinds of standard level. Therefore, many devices under test (DUTs) can be tested using this test system. At

last, the new test system is verified successfully using the method of fault injection under laboratory conditions.

6) Some NIM moduls, such as eight channel constant fraction discriminator (CFD), fast logic level adapter, etc.

are produced continuously for physics experiments and beam testing system of Cancer therapy equipment.

7) In 2015, six papers have been published in the domestic core journals, Chinese Physics C, Nuclear Science

and Techniques, etc, three papers among them have been included in SCI, and one paper has been included in EI.

Three national patents of invention were authorized. Three PhD students and one Master student have graduated

from group.

5 - 28 A Design of 0.35 µm CMOS Multi-channel

Shaper for PPAC Detector

Qian Yi, Pu Tianlei and Su Hong

Radioactive Ion Beam Line in Lanzhou (RIBLL) is the heavy ion radiation beam equipment on Heavy Ion

Accelerator in Lanzhou, which can provide a variety of Radioactive Ion Beam （RIB）for physical experiments.

In order to improve the efficiency and accuracy of the experiments, we need a high-performance Parallel Plate

Avalanche Counter(PPAC) to monitor the RIB online and to measure the track of the incident particles and

reaction products. To meet the requirements of high performance PPAC, the readout electronics will be high

integration(for 200 read-out strips), high-speed(100 k/s), low noise and low power consumption. So, an application

specific integrated circuit (ASIC) chip which has four-channel CR-RC3 shapers with 50 and 100 ns adjustable

peaking time is designed with Chartered 0.35 µm CMOS process successfully in 2015. The chip can be combined

with existing pre-amplifiers for the signal readout of PPAC detectors. The Block diagram of a single shaper channel

is shown in Fig. 1. Each channel includes a pole-zero cancellation circuit, a low-pass filtering circuit[1] and an output

circuit[2,3].

Fig. 1 Block diagram of a single shaper channel.

The post-simulation results (with extracting parasitic parameters of layout) show that the linearity is achieved

about 0.2% with the dynamic range from -0.8 to +0.8 V shown in Fig. 2 and the -3 dB bandwidth noise is not

higher than 60 µV. The power dissipation of the entire chip is less than 30 mW. Fig. 3 is the 100 ns peak time

output waveform with different input.

Fig. 2 (color online)Output voltage linearity of shaper.

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Fig. 3 (color online) 100 ns peak time output waveform with different input.

The chip area is 2.6 mm× 1.25 mm. It has been fabricated in foundry in Nov. 2015. And we will get the die in

Feb. 2016. Then the packing and testing work will be done.

References

[1] L. He, Z. Deng, Y. Li, et al., CASAGEM: A readout ASIC for MPGDs[C]// Nuclear Science Symposium and Medical ImagingConference (NSS/MIC), IEEE, (2012)797.

[2] R. J. Baker, CMOS: circuit design, layout, and simulation[M]. John Wiley & Sons, (2011).

[3] P. E. Allen, D. R. Holberg, CMOS analog circuit design[M]. Taylor & Francis US, (2002).