5 4 3 2 1 d d tms320tci6614 evm board for...

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DISCLAIMER: THIS CIRCUIT DESIGN IS

PROVIDED AS REFERENCE ONLY,

WITHOUT WARRANTY EXPRESSED OR

IMPLIED. THE USER IS ENCOURAGED

TO PERFORM ALL DUE DILIGENCE WITH

RESPECT TO DESIGN AND ANALYSIS.

Copyright (C) 2010, 2011 Texas Instruments Incorporated.

All rights reserved. This document is proprietary to TI

and is intended solely for use by TI and its customers.

This document is not to be reproduced, distributed, or

disclosed to other parties in its entirety or in part

without the express written consent of TI.

TI Information - Selective DisclosureTexas Instruments12203 SW FreewayStafford, TX 77477USA

NOTE: THESE SCHEMATICS ARE REFERENCE ONLY.FOR COMMITTED PERFORMANCE AND FUNCTIONALITY OF THE TMS320TCI6614 DEVICE, PLEASE REFER TO THE DEVICE DATA MANUAL.

1.0 oz

1.0 oz

1.0 oz

1.0 oz

1.0 oz

1.0 oz

TOP

L2_GND

L3

L4_PWR

L5

L6_GND

L7_GND

L8

L9_PWR

L10

L11_GND

BOT

1.0 oz

1.0 oz

0.5 oz

0.5 oz

0.5 oz

0.5 oz

3mils

4mils

7.7mils

6mils

4.7mils

4mils

4.7mils

6mils

7.7mils

4mils

3mils

p.p

core

core

p.p

p.p

core

p.p

core

core

p.p

p.p

19C2830300

TMS320TCI6614 EVM Board for TI

Project Code :

Rev. A101-1 (Alpha2)

PCB PN :

PCB Thickness : 69 mils(1.75mm)

12 Layers

Title

Size Document Number Rev

Date: Sheet of

Designed for TI by ADVANTECH

TMS320TCI6614 A101

COVER PAGE

C

1 37Tuesday, January 17, 2012

DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

COVER PAGE

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

COVER PAGE

C


DSPM-8303E

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5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TMDXEVM6614LXE Revision TableTMDXEVM6614LXE Rev 1.0 (Alpha1 / PCB-19C2830300)

The UART connector interfers with the XDS560V2 mezzanine card1. Move the COM1 to backside of PCB and use a 90 degree connector on Alpha 1 and Alpha 2 units2. Move the COM1 location to fix the interference on Beta PCB

Item

A

B

Description

C Change the value of R123 to 45.3 ohm

HThe symbol of the GPS chip in the schematics, TC6000G, was not matched as the spec.It will modify the symbol to match the TC6000G specification on Beta version. 27

The GPS_EN was not followed by TC6000G timing requirement. It will modify the EN pin contorlled by the FPGA for a proper timing on Beta version.I 27

TMDXEVM6614LXE Rev 2.0 (Alpha2 / PCB-19C2830300)

Change SOC to Rev 1.1 silicon

Item

A

B

Description

Alll ECNs were implied on Alpha 2 units

Page

DThe power jack was interferred with AMC breakout board and Adpater1. Move the power jack to backside of PCB to avoid the interference with AMC breakout board on Alhpa 1 and Alpha 2 units2. Rotate the power jack to fix this issue on Beta PCB

The footprint pitches of OSC1 (VCTCXO) was incorrect to not fit the assembly of PCB1. The facility fixed this issue by the processes of PCB assembly on Alpha1 and Alpha2 units2. Fix the VCTCXO footprint on Beta PCB

E The SW7 of sliding switch, BM_GPIO_16 was missed to connect the FPGA for the SOC boot configurations1. Take the User_Define bit on SW2 to be the bit of GPIO16 configuration of SOC on Alpha1 and Alpha2 units2. Route the BM_GPIO16 to pin N3 of FPGA on Beta PCB

F

UCD9222 Enable pins were coupled of the noises when VCC1v0 (UCD74106) had over 2 amps loading.1. Parallel a 0.1uF capacitor at R102 and R103 to filter the noise on UCD9222_ENA1 and UCD9222_ENA1 (power enabling pins) on Alpha1 and Alpha 2 units2. Add the locaton C576 and C577 on Beta PCB

G

The CDCE62002 do not have built in 100 ohm terminations at inputs1. Paralle a 100 ohm resistor across the CLK1 sides of the C46 and C51 on Alpha1 and Alpha 22. Add the location R597 on Beta PCB

Page

16

27

14

11

32

22

34

Title


Date: Sheet of


TMS320TCI6614 A101

TMDXEVM6614LE Revision Table

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

5

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3

2

2

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D D

C C

B B

A A

TITLE & TABLE OF CONTENTS

37


COVER PAGE

02

04

03

06

08

07

05

09

10

12

14

13

16

15

11

18

20

19

22

21

17

23

24

25

26

27

28

29

30

01


Page Description

32

34

33

35

Power_VCC1V5

DescriptionPage

31

BLOCK DIAGRAM_AMC

POWER SEQUENCE

POWER CONSUMPTION

POWER DISTRIBUTION

CLOCK DIAGRAM

CLOCK_GEN1

36

Smart-Reflex AVS

Power_VCC5 / VCC3_AUX

Power_1.2V/1.8V/2.5V/0.75V

FPGA_XC3S200AN_C

FPGA_XC3S200AN_B

DDR3_ECC

DDR3

FPGA_XC3S200AN_A

Connectors for MCM & Debug

RJ45

GBE Ethernet PHY

GPS & SIM CARD

CLOCK_GEN2

CLOCK_GEN3

SOC_POWERB

SOC_AIF

SOC_GND

SOC_SRIO_SGMII_PCIE_MCM

SOC_DDR3

SOC_JTAG_EMU_AIF

SOC_MISC

SOC CLOCKs & Smart-Reflex VID

SOC_POWERA

Management Map

AMC GF

MMC

FPGA_BLOCK

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AMC Board

AMC Port mapping

Port mapping

100MHz

SGMII

Port

12

11

Port mappingPort

13

14

15

00

01

02

03

04

05

06

07

08

09

10

17

18

19

20

TCLKA

TCLKB

FCLKA

PCI-E_1

PCI-E_2

SRIO_1

SRIO_2

SRIO_3

SRIO_4TCLKA

TCLKB

N25Q032A11ESF40F

1

+V3.3_MP

UART

MDIO

EMU[2:17] JTAG &

EMU[0:1]

SGMII1 MAC0

PCIEx2

I2C

DDR3

Miscellaneous I/O 100 Pin-conn.

GP

IO[0

:15

](1.8

V)

SO

C_

SP

I(1.8

V) #

3

SO

C_

UA

RT

(3.3

V)

SO

C_

I2C

(1.8

V)

MAX3221EAE

RS232

SOC_SGMII_P1 & MDIO

RJ45

SRIOx4

SGMIIx1

PCIEx2

SRIOx4

EMIF16

SPI

JTAGSBW_MMC1

MMCIPMB-L

AMC_State

#0

AMC_Statefrom MMC

SOC

POWER 12V

PWR CONN

SPI

PowerFPGA

Others

RAMPower Control

PHY

(MSP430)

DDR3 -1600

DDR3-1600

w/ ECC

SOC_SPI#1

MMCJTAG

(XILINX)

SOC_GPIO

XC3S200ANFPGACLK1_SPI

CLK2_SPI

SOC

to FPGA

EEPROM

SequenceControl

SPI FlashNOR 32M-bit

60-Pin EMU CONN.

EMU[18:2]

JTAG & EMU[0:1]

2.54mm

Pin-Header 3x1

CLK#2

CDCE62005

CDCE62005

CLK#3

AIFx6

AIFx2

Hyper Link

HyperLink

50Gbps

iPass+HDHyperLink CONN.

AIF_4

AIF_5

AIF_CLK & FS

Expansion I2C

Power Control

*

NAND FLASH

1Gb 128M X8

SW_GPIO

CLK#1

CDCE62002

CLK3_SPI

RP1/SYNC

SOC_I2C

AIF CLK & FS

I2C

TI_TMS320TCI6614

DDR3(ECC)1. 128M X 8

D1

D2User controlled LED - 4

SYSPG_D1 LED

DEBUG_LED

JTAGFPGA JTAG

DIP SWBM_GPIO(0~16) /

PCIESSEN / User define /

SOC_CORECLKSEL /

FPGA_PACLKSEL

ST_M24M01

128k-byte

1. 128M X 16 / 1GB

NU Resistors

TMS320TCI6614 EVM BLOCK DIAGRAM

JTAG

UCD9222_PMbus

UCD9222

MT29F1G08ABBDAHC:D

SO

C_

EM

IF16

(1.8

V)

80-Pin

AIFx4

USIM

Translator

TXS4555RGTR

ENET PHY88E1111-B2

TO SOC USIM INTERFACE

SFP CONN.

SO

C_

UA

RT

(3.3

V)

(1.8

V)

USIM

GPIOGPIO

TIMER0

GPS

TC6000G

VCTCXO

E4933LF

DAC

DAC7611UB

#2 FROM SOC SPI INTERFACE

BUFFER

TO CLK GEN3CDCLVC1104

TO FPGA

TO FPGA

FROM FPGA FYSNC

FROM SOC TIMEO0

TCLKC / TCLKD

EMU[1:0]

TO MMC UART

(default)(Pin-Header 3x1)

TO SOC PHYSNC

TO SOC RADSYNC

TO AMC RADSYNC

TO AMC PHYSNC

EMIFA07

EMIFA08

EMIFA09

EMIFA11

EMIFA10

EMIFA14

EMIFA13

EMIFA12

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

40

Port mappingPIN

02

04

06

08

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA05

EMIFA04

EMIFA06

EMIFA20

EMIFA21

EMIFA22

EMIFA23

EMIFD0

EMIFD1

EMIFD2

EMIFD3

EMIFD4

EMIFD5

EMIFD6

EMIFD7

EMIFD8

EMIFD9

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFD15

EMIFCE1Z

EMIFCE2Z

EMIFBE0z

EMIFBE1z

EMIFOEz

EMIFWEz

EMIFRnW

EMIFWAIT1

77

SCL

SDA

TIMI0

TIMI1

SSPMISO

SSPMOSI

TIMO1

SSPCS3

SSPCK

TIMO0

39

Port mappingPIN

01

03

05

07

09

11

13

15

17

19

21

23

25

27

29

31

33

35

37

Port mappingPIN

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

79

GND

GND

GND GPIO16

GND

GND

GND

GND

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO06

80

Port mappingPIN

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

GND

GND

GND

GND

GND

UARTTXD

UARTRXD

UARTCTS

UARTRTS

GND

87

81

83

85

89

97

91

93

95

99

GND

GND

GND

GND

GND

90

84

86

88

82

100

94

96

98

92

GND

CLK2_SYNC

CLK3_SYNC

GND

2

100

1

99

Miscellaneous I/O 100 Pin conn. Signal

Title


Date: Sheet of


TMS320TCI6614 A101

BLOCK DIAGRAM_AMC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

BLOCK DIAGRAM_AMC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

BLOCK DIAGRAM_AMC

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

88E1111

SOC TMS320TCI6614 CVDD

When power on

When power down

SOC

TMS320TCI6614VCC1V0 Scaled/(CVDD)VCC1V0 Fixed/(CVDD1)VCC1V8/ (DVDD18)

VCC3V3_MP

Power Sequence

VCC12

VCC_1V0 scaled

XC3S200AN

VCC2V5

SOC

TMS320TCI6614

VCC1V8

DDR3 SDRAM

VCC1V0SOC TMS320TCI6614

DDR3 Vref

SOC TMS320TCI6614

DDR3

DDR3

MMC

VCC_1V0 Fixed

VCC1V8

VCC1V8

VCC_1V0 Fixed VCC_1V0 scaled

Ther is no specific power-up norpower-down sequence.

SOC TMS320TCI6614

SOC TMS320TCI6614

1.5V/(DDR3_IO)0.75V/(DDR3_Vref)


88E1111 (PHY)

2.5V

88E1111

1.2V

Reset Sequence

VCC3V3_MP_AMC

S6

S0

S3

S4

S5

S7

S8

S9

S10

88E1111

PMBUS &

UCD9222_ENA2

VCC1V8_EN

VCC1V5_EN

VCC0V75_EN

VCC2V5_EN

FT2232HOther

S11

S13

S12

S14

S15

S16

VCC3V3_AUX

2.5V/ 1.2V


VCC5_ENS17

S18 XDS560V2 Mazzenine Board VCC5

VCC1V2XC3S200AN

S2

XILINX_XC3S200AN1.2V_AUX (VCCINT)1.8V_AUX (VCC1V8_AUX)

Ther is no specific power-up norpower-down sequence. XILINX_XC3S200AN

VCC1V8_AUXXC3S200AN

S1

0.75V (SOC)

1.0V_scaled

1.0V_fixed

VCC1V8

1.5V (SOC)

3.3V / 1.8V/ 1.2V

REFCLKP&N

DDRCLKP&N

CLK Sequence

3.3V_AUX (VCCAUX)

Power Sequence

VCC0V75

UCD9222_ENA1

VCC1V5

by REFCLK3_PD#

by REFCLK2_PD#

CLOCK2_PLL_LOCK

CLOCK3_PLL_LOCK

by REFCLK1_PD#

CLOCK1_PLL_LOCK

REFCLKP&N

POR#

T=18mS

RESETSTAT#

RESET#

RESETFULL#

T=5mS

T=5mS

includingperipherals.

by SOC chip

PMBUS &

64ms

15.9ms

24.7ms

10.2ms

59ms

50ms

(AUX)

4.18ms

1.37ms

4.9ms

9.9ms

Title


Date: Sheet of


TMS320TCI6614 A101

Power Sequence

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power Sequence

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power Sequence

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER CONSUMPTION

For Power Consumption please refer to TMS320TCI6614 Data Manual

http://www.ti.com/lit/ds/symlink/tms320tci6614.pdf

Title


Date: Sheet of


TMS320TCI6614 A101

POWER CONSUMPTION

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

POWER CONSUMPTION

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

POWER CONSUMPTION

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DC 12V Adapter

POWER DISTRIBUTION

Efficiency=90%

TPS54620

TPS51200

(3.3Control)

VCC1P5_EN

VCC0P75_EN

VCC0P75TBD

VCC1V5TBD

DDR3

0.75V / 0.25A (Vref)

1.5V / 0.24A (VDD)*5 Total:1.2A

*

0.315A

SmartReflex

UCD9222

UCD74110

UCD9222_ENA[1:2]

CVDDTBD

Quad Core SOC

VCC1V0 / 9.75A Scaled/(CVDD)VCC1V0 / 4.52A Fixed/(CVDD1)VCC1V8 / 0.15A (DVDD18)1.5V / 0.47A (DDR3_IO)0.75V/(DDR3_Vref)

1.5 A

AMC Gold Finger

VCC3V3_MP_AMC

@ 165uA

VCC12(3.04A)

3.3V_MP(165uA)

TI_TMS320TCI6614

RS232 3.3V

3.3V / 0.3A

XDS560V2

Mazzenine Board5.0V / 1A

XILINX_XC3S200AN1.2V_AUX/ 0.125A (VCCINT)3.3V_AUX/ 0.024A (VCCAUX)

MicronNAND FLASH

1.8V / 0.02A

EEPROM

3.3V

NOR FLASH

Standyby mode 1.8V/80uA

88E1111 (PHY)2.5V / 0.21A1.2V / 0.25A

Efficiency=90%

VCC1V0TBD

TPS54231

Efficiency=80%

VCC_5V_EN

VCC5@1A

0.49A

[email protected]

Efficiency=90%

TPS54620

TPS73701DCQ

TPS73701DCQ

TPS73701DCQ

VCC1V8TBD

[email protected]

[email protected]

[email protected]

VCC2P5_EN

VCC1P8_EN

0.679A

VCC12

TPS73701DCQ

UCD74106

PWM1

Vsense1

Isense1

Tsense1

PWM2

Vsense2

Isense2

Tsense2

(15A) (6A)

Title


Date: Sheet of


TMS320TCI6614 A101

POWER DISTRIBUTION

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

POWER DISTRIBUTION

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

POWER DISTRIBUTION

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK DIAGRAM

CDCE62005

X'TAL25MHZ

SRIO_SGMII_CLKP/N

PCIe_CLKP/N

MCM_CLKP/N

CORE_CLKP/N

PA_SS_CLKP/N

DDR_CLKP/N

SOC

122.88MHz

122.88MHz

30.72MHz

SYS_CLKP/N

RP1_CLKP/N

CDCE62005X'TAL30.72MHZ

88E1111X'TAL25MHZ

Core Processor

CLK3

CLK2

CDCE6200266.667MHz

100.00MHz

CLK1U0

U0

U1

U2

U3

U0

U1

U2

for PCIe ref.

FCLK[p/n]

AMC Gold Finger

FCLK P/N

TI_TMS320TCI6614

TCLKA[p/n]

TCLKB[p/n]

TCLKC[p/n]

TCLKD[p/n]

TCLKA

TCLKB

TCLKC

TCLKD

FPGA

PRI_REF

U325.00MHz

312.5MHz

312.5MHz

122.8MHz

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

HCSL

30.72MHzLVDS

for AIF

RP1CLK[p/n]

RP1CLK[p/n]

PRIREF+VCTCXO

19.2MHZ

BUFFER 19.2MHz

GPS

TC6000-G

PPS

Timer0_Input

FPGA

Selector

headerFPGA Generated

FSYNC

Timer0_Ouput

AT Timer Sync

CDCLVC1104

PRIREF+TCLKB[P/N]

SECREF+TCLKD[P/N]

Timer1_Input

Timer1_Ouput

FROM FPGA

TO FPGA

(default)SYNCCLK3_SYNC

SYNCCLK2_SYNCfrom expansion head

from expansion head

for PCIe ref.

100.00MHz

IN2

IN1

LVDS

HCSL

LVDSCLK

156.25MHz

SEL (CONTROL BY FPGA)

19.2MHz

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK DIAGRAM

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK DIAGRAM

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK DIAGRAM

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Power Group

TI_MSP430F5435IPN

TI MMC MMC_RESETSTAT#MMC_POR#

MMC_DETECT#

UCD9222

Control

TI_TPS54620RGY

TI_TPS73701DRBT

TI_TPS54231D

x2

x4

x1

Power

Sequences

Control

Boot & Deviceconfigurations

SOC

SOCRESET &

ControlInterrupts

+V3.3

MMC

Control

XILINX_XC3S200AN-4FTG256C

TMS320TCI6614 EVM (AMC)

SPI

SOC

FPGA

JTAGRESET

FPGA_BLOCK

PORzRESETFULLzRESETzPACLKSELLRRESETNMIENzCORESEL[0:2]NMIzLRESETz

AM

C E

dg

e C

on

ne

cto

r(G

old

en

Fin

ge

r)

AIF_RXP/N[0:1]

AIF_TXP/N[0:1]

DSP_PORzDSP_RESETFULLzDSP_RESETzDSP_PACLKSELDSP_LRRESETNMIENzDSP_CORESEL[0..2]#DSP_NMIzDSP_LRESETz

+V1.8

SRIO_RXP/N[1:4]

SRIO_TXP/N[1:4]

PCIe_RXP/N[1:2]

PCIe_TXP/N[1:2]

SGMII_RXP/N[0]

SGMII_TXP/N[0]

DSP_DSPCLKSEL CLKSELEXTFRAMEEVENTDSP_EXTFRAMEEVENT

DSP_HOUTDSP_BOOTCOMPLETE

DSP_SYSCLKOUT SYSCLKOUTHOUTBOOTCOMPLETE

SOCEMIF16

NAND FLASH

SPISCS

SPICLK

SPIDOUT

SPIDIN

Test Connector 80-pin(Female)

expansion I2C DATAexpansion I2C CLK

TI_TMS320TCI6614

MMC_WARM_RST#

VCC3V3_AUX_PGOODVCC5_PGOODVCC1V5_PGOOD

VCC0V75_PGOODVCC2V5_PGOOD

+V3.3

WARM RESET

60-pin emulation

(Female)

+V3.3

+V1.8

TRGRSTZ

FULL RESET

SPI_FPGA_CS1

SPI_FPGA_MISO

SPI_FPGA_MOSISPI_FPGA_SCK

+V3.3

GPIO[4:7] GPIO[12:15]GPIO[8:11]GPIO[0:3]

TIMI0

TIMI[0]

AMC_TDM_CLKA/B[p/n]AMC_TDM_CLKC/D[p/n]

SOCTDM CLK

AMC_TDM_CLKA/B[p/n]AMC_TDM_CLKC/D[p/n]

VCC2V5_ENVCC0V75_ENVCC1V8_EN1VCC5_ENVCC1V5_EN

CLOCKConfigurations (1)

+V3.3SPI_CLK_CS#[1..3]

SPI_CLK_MOSI[1..3]SPI_CLK_MISO[1..3]REFCLK1_PD#[1..3]PLL_LOCK[1..3]

TI_CDCE62002 #1TI_CDCE62005 #2TI_CDCE62005 #3

SPI_CLK_CK[1..3]CLOCK Group

PCIe clk selectMULTIPLEXER

+V3.3FPGA_ICS557_SELFPGA_ICS557_PD#FPGA_ICS557_OE

Function SWITCH

SOC+V1.8

+V1.8DSP_DSPCLKSEL

SW_DSP_GPIO[0 : 16] +V1.8

User SwitchPCIESSEN

FPGA_PACLKSEL

PHYControl 88E1111-B2

MARVELL +V2.5

PHY_INT#

PHY_RST#

BSC_JTAG_TDI

BSC_JTAG_TCKBSC_JTAG_TMSBSC_JTAG_RST#

FPGA_TDI BSC_JTAG_TDO

FPGA_TDO

PHY_TDI PHY_TDO

IDT557-08

PM BUS

PG2ENA2

+V3.3

TI UCD9222ClkControlAlert

Data

PG1UCD9222_PG1UCD9222_ENA1 ENA1

UCD9222_RSTPGUCD9222 PG

RESET

PIN HEADER

UCD9222_PG2UCD9222_ENA2

(UCD74110)

(UCD74106)

CVDD

CVDD1

GPIO[0:15]

GPIO[16]

GPSPPS

SFP

+V1.8

TX_FAULTLOS

SFP CONN ControlRATESELECTTX_DISABLE

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_BLOCK

B


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_BLOCK

B


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_BLOCK

B


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SOC

TMS320TCI6614

I2C

( 0X50h )

FPGA

(XILINX_XC3S200AN)

MDI/O

AMC Gold Finger

IPMB-L

SPI

SPI1

MMC_RESETSTAT#

FP_POR_IN

_AMC#

MMC

(MSP430)

ENET PHY

(88E1111)

EEPROM

I2C

CDCE62005SPI2

Power Sequences ControlGPIO

WARM_RESET_AMC#

AMC_DETECT#

CDCE62005

POR#

RESETFULLZ#

RESETZ#

Management Map

(Pin-Header 3x1)

UART

RS232

MAX3221EAE

NU Resistors

MSP430 (MMC)

(CS1z)

DSP_RESETSTAT#

I2C

MDI/O

JTAG

100-pin Header

JTAG

SBW

RS232

SPI3

MDC

The NU resistors on these connections to the MSP430 are for debug use only

and will be used only with the shunts removed from pins 1 and 2 of CN7

bypass resistors

+V1.8

MDI/O

+V2.5

Level Shifter

PCA9306DCUT

MDI/OMDCMDC

MDC

Level Shifter

PCA9306DCUT

JTAG

DSP_RESETSTAT#

SPI1CDCE62002

MMC_ENABLE_N

MMC_PS_N0MMC_PS_N1

JTAG

PHY (88E1111)

TMS/TRSTn

TDO

TDI TDO TDI TDO

TDI

JTAG

CN10

JTAG

FPGA

XC3S200AN

Boundary ScanJTAG and

(Jumper Option)UART1

JTAG +V1.8

UART+V3.3Le

ve

l Sh

ifter

SN

74

AV

C4

T2

45

TCK

PHY_TCK

FPGA_TCK

(ST M24M01-HRMN6TP)

(128KB)

( 0X51h )

UART2

EMU CONN.

GPS moduleTC6000G

SEL

SWITCH

(TS3L301)

High-SpeedEMU_DET PIN

EMU_DETz

Lev

el

Sh

ifte

rJTAG

+V1.8

JTAG

AMC JTAG

+V3.3

AMCedge connector

+V1.8

Title


Date: Sheet of


TMS320TCI6614 A101

Management Map

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Management Map

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Management Map

C


DSPM-8303E

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Management Power

OVP: ~12.7V+0.6V = ~13.3V DC FAN Connet for SOC

AIF[4:5]

SRIO[1:4]

PCIe[2:1]

AIF CLK & FS

Expansion I2C

external RP1CLK

JTAG

TCLKC_P : output for DSP_TIMI1TCLKC_N : intput for DSP_TIMO1

TCLKD also serves as a 30.72MHz LVDS clock to CLK3

PRI_REF for the AIF synchronization

TCLKCp/n alsp servers as the DSP_TIMI1

and DSP_TIMO1 and 3.3V I/O respectively

TCLKB also serves as a 25.0MHz LVDS clock to

CLK2 PRI_REF for the HyperLink synchronization.

DC jack interference workaround: Move DC jack to PCB backside.

A101-1

MMC_PS_N1

MMC_PS_N1

MMC_PS_N0

P5_PCIe_TX2PP5_PCIe_TX2N

P4_PCIe_TX1PP4_PCIe_TX1N

DSP_SDA_AMCDSP_SCL_AMC

AMC_JTAG_TDIAMC_JTAG_TDOAMC_JTAG_TMSAMC_JTAG_TCK

AMC_JTAG_RST#

AMC_JTAG_TDI

AMC_JTAG_TCKAMC_JTAG_TMS

AMC_JTAG_TDOAMC_JTAG_RST#

VCC12

VCC12

VCC3V3_MP_AMC

VCC12

VCC3V3_AUX

INAMC0_SGMII0_TX_DP(13)INAMC0_SGMII0_TX_DN(13)

OUTSMB_SCL_IPMBL(12)

OUTAMC0_SGMII0_RX_DP(13)OUTAMC0_SGMII0_RX_DN(13)

BISMB_SDA_IPMBL(12)

OUTAMCC_P4_PCIe_RX1P(13)

OUT AMCC_P11_SRIO4_RXP (13)OUT AMCC_P11_SRIO4_RXN (13)

OUTAMCC_P4_PCIe_RX1N(13)

OUTAMCC_P5_PCIe_RX2P(13)OUTAMCC_P5_PCIe_RX2N(13)

OUTMMC_ENABLE_N(12)

INMMC_GA0(12)

INMMC_GA1(12)

INMMC_GA2(12)

IN AMCC_P8_SRIO1_TXP (13)IN AMCC_P8_SRIO1_TXN (13)

IN AMCC_P9_SRIO2_TXN (13)IN AMCC_P9_SRIO2_TXP (13)






IN AMCC_P18_AIF5_TXN (17)IN AMCC_P18_AIF5_TXP (17)

IN AMCC_P17_AIF4_TXP (17)IN AMCC_P17_AIF4_TXN (17)

OUT AMCC_P18_AIF5_RXP (17)OUT AMCC_P18_AIF5_RXN (17)

OUT AMCC_P17_AIF4_RXP (17)OUT AMCC_P17_AIF4_RXN (17)

OUTPCIE_REF_CLK_P(18)OUTPCIE_REF_CLK_N(18)

BI AMC_EXP_SDA (16)IN AMC_EXP_SCL (16)

INAMCC_P4_PCIe_TX1P(13)INAMCC_P4_PCIe_TX1N(13)

INAMCC_P5_PCIe_TX2P(13)INAMCC_P5_PCIe_TX2N(13)

OUT RADSYNC (16,27)OUT PHYSYNC (16,27)

OUTTCLKB_P(23,31)OUTTCLKB_N(23,31)

OUTTCLKA_P(31)OUTTCLKA_N(31)

OUT TCLKD_P (24,31)OUT TCLKD_N (24,31)

OUT TCLKC_P (31)OUT TCLKC_N (31)

OUT AMC_RP1FBN (16)OUT AMC_RP1FBP (16)

OUT AMC_RP1CLKN (18)OUT AMC_RP1CLKP (18)

OUT AMC_JTAG_TMS (15)OUT AMC_JTAG_RST# (15)

OUT AMC_JTAG_TCK (15)

IN AMC_JTAG_TDO (15)OUT AMC_JTAG_TDI (15)

Title


Date: Sheet of


TMS320TCI6614 A101

AMC GF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

AMC GF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

AMC GF

C


DSPM-8303ER593100K

C5621000pF50V

GS D

AO3401-4.2A/-30V

Q5

1

32

C570 1uF25VC569

0.1uF50V

C20310uF16V

C91 0.1uF 16V

R590100K

C2021uF16V

FAN1WB_3V_2.0mm

123D8

BZX84-C1212V

1 2

3

D2ASD500V0.1A

1 2

TP21

R319100K

C2011uF16V

R586 100K

C2220.1uF50V

R354 10K

C107 0.1uF 16V

AMC1

GF-AMC-B

GND_11

GND_27

GND_310

PWR_12V_12

PS13

MP4

GA05

RSRVD66

RSRVD88

PWR_12V_29

Tx0+11

Tx0-12

GND_413

Rx0+14

Rx0-15

GND_516

GA117

PWR_12V_318

GND_619

Tx1+20

Tx1-21

GND_722

Rx1+23

Rx1-24

GND_825

GA226

PWR_12V_427

GND_928

Tx2+29

Tx2-30

GND_1031

Rx2+32

Rx2-33

GND_1134

Tx3+35

Tx3-36

GND_1237

Rx3+38

Rx3-39

GND_1340

ENABLE41

PWR_12V_542

GND_1443

Tx4+44

Tx4-45

GND_1546

Rx4+47

Rx4-48

GND_1649

Tx5+50

Tx5-51

GND_1752

Rx5+53

Rx5-54

GND_1855

SCL_L56

GND_1958

Tx6+59

Tx6-60

GND_2061

Rx6+62

Rx6-63

GND_2164

Tx7+65

Tx7-66

GND_2267

Rx7+68

Rx7-69

GND_2370

SDA_L71

PWR_12V_657

PWR_12V_772

GND_2473

TCLKA+74

TCLKA-75

GND_2576

TCLKB+77

TCLKB-78

GND_2679

FCLKA+80

FCLKA-81

GND_2782

PS083

PWR_12V_884

GND_2885

GND_2986Rx8-87Rx8+88

Tx8+91

Tx8-90

GND_3089

Rx9+94

Rx9-93

GND_3192

Tx9+97

Tx9-96

GND_3295

Rx10+100

Rx10-99

GND_3398

Tx10+103

Tx10-102

GND_34101

Rx11+106

Rx11-105

GND_35104

Tx11+109

Tx11-108

GND_36107

Rx12+112

Rx12-111

GND_37110

Tx12+115

Tx12-114

GND_38113

Rx13+118

Rx13-117

GND_39116

Tx13+121

Tx13-120

GND_40119

Rx14+124

Rx14-123

GND_41122

Tx14+127

Tx14-126

GND_42125

GND_43128

Rx15+130

Rx15-129

GND_44131Tx15-132Tx15+133GND_45134

TCLKC+136

TCLKC-135

TCLKD+139

TCLKD-138

GND_46137

Rx17+142

Rx17-141

GND_47140

Tx17+145

Tx17-144

GND_48143

Tx18+151

Tx18-150

GND_50149

Rx18+148

Rx18-147

GND_49146

Tx19+157

Tx19-156

GND_52155

Rx19+154

Rx19-153

GND_51152

Tx20+163

Tx20-162

GND_54161

Rx20+160

Rx20-159

GND_53158

GND_55164TCK165TMS166TRST167TDO168TDI169GND_56170

R64 0

R5921K1%

C101 0.1uF 16V

R57 0

R355 10K

Q7MMBT3904LT10.2A2

1

3

G

S

D Q62N70020.3A/60V1

32

R360 10K

R594100K

R361 10K

DC_IN1

<Characteristic>JACK_3H

1

23

R368 10K

C112 0.1uF 16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(BLUE LED)

(RED LED)

Power for MSP430

The NU resistors on these connections to the MSP430 are for debug use only

and will be used only with the shunts removed from pins 1 and 2 of CN7

SPI I/F is for Advantech FPGA debugging.

SpyBiWire

MMC_XTAL1

MMC_XTAL2MMC_XTAL1MMC_XTAL2

MMC_LED2

MMC_LED1

MMC_ENABLE_N

MMC_SBWTDIO

MMC_GAPU

MMC_GA2

MMC_GA2MMC_GA1MMC_GA0

SMB_SCL_IPMBLSMB_SDA_IPMBL

SMB_SCL_IPMBL

SMB_SDA_IPMBL

MMC_GAPUMMC_LED1

MMC_LED2

MMC_GA1

MMC_GA0

MMC_MOSIMMC_MISO

MMC_STE

MMC_SCK

MMC_P43

MMC_SBWTCKMMC_SBWTDIO

MMC_SBWTCK

MMC_SBWTDIO

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP VCC3V3_AUX

VCC3V3_MP_AMC

VCC3V3_MP

VCC3V3_MP

IN MMC_ENABLE_N (11)

OUT MMC_POR_IN_AMC# (31)

OUT MMC_DETECT# (31)

OUTMMC_GA0(11)OUTMMC_GA1(11)OUTMMC_GA2(11)

IN MMC_RESETSTAT# (31)IN MMC_BOOTCOMPLETE (31)

OUT MMC_WR_AMC# (31)

OUT UART_FT_RX (16)IN UART_FT_TX (16)

IN SMB_SCL_IPMBL (11)BI SMB_SDA_IPMBL (11)

OUT MMC_SPI_MISO (31)IN MMC_SPI_MOSI (31)IN MMC_SPI_STE (31)

IN MMC_SPI_SCK (31)

Title


Date: Sheet of


TMS320TCI6614 A101

MMC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

MMC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

MMC

C


DSPM-8303E

C550.1uF16V

Y3

<Characteristic>32.768KHz_12.5pF

14

3 2

TP8

R427 NL/0

BD4 19-215SUBC/S280/TR81 2

C3480.1uF16V

C4270.1uF16V

TP9 R250 33K

C1230.1uF16V

G

S

DQ82N70020.3A/60V 1

32

R283 330

D6 RB751V40

0.2A

12

R249 33K

C351

1000pF

50V

C84 0.47uF 10V

TP10

C580.1uF16V

C95 22pF50V

C4090.1uF16V

D7 RB751V40

0.2A12

R429NL/10K

R252 NL/0

R131 NL/0

R233NL/0

MMC1

TI_MSP430F5435IPN

P6.4/A41

P6.5/A52

P6.6/A63

P6.7/A74

P7.4/A125

P7.5/A136

P7.6/A147

P7.7/A158

P5.0/A8/VREF+/VeREF+9

P5.1/A9/VREF-/VeREF-10

AVCC11

AVSS12

P7.0/XIN13

P7.1/XOUT14

DVSS115

DVCC116

P1.0/TA0CLK/ACLK17

P1.1/TA0.018

P1.2/TA0.119

P1.3/TA0.220

P1.4/TA0.3

21

P1.5/TA0.4

22

P1.6/SMCLK

23

P1.7

24

P2.0/TA1CLK/MCLK

25

P2.1/TA1.0

26

P2.2/TA1.1

27

P2.3/TA1.2

28

P2.4/RTCCLK

29

DVSS3

30

DVCC3

31

P2.5

32

P2.6/ACLK

33

P2.7/ADC12CLK/DMAE0

34

P3.0/UCB0STE/UCA0CLK

35

P3.1/UCB0SIMO/UCB0SDA

36

P3.2/UCB0SOMI/UCB0SCL

37

P3.3/UCB0CLK/UCA0STE

38

P3.4/UCA0TXD/UCA0SIMO

39

P3.5/UCA0RXD/UCA0SOMI

40

P3.6/UCB1STE/UCA1CLK41P3.7/UCB1SIMO/UCB1SDA42P4.0/TB0.043P4.1/TB0.144P4.2/TB0.245P4.3/TB0.346P4.4/TB0.447P4.5/TB0.548VCORE49DVSS250DVCC251P4.6/TB0.652P4.7/TB0CLK/SMCLK53P5.4/UCB1SOMI/UCB1SCL54P5.5/UCB1CLK/UCA1STE55P5.6/UCA1TXD/UCA1SIMO56P5.7/UCA1RXD/UCA1SOMI57P7.2/TB0OUTH/SVMOUT58P7.3/TA1.259P8.0/TA0.060

P8.1/TA0.1

61

P8.2/TA0.2

62

P8.3/TA0.3

63

P8.4/TA0.4

64

P8.5/TA1.0

65

P8.6/TA1.1

66

DVCC4

67

DVSS4

68

P5.2/XT2IN

69

P5.3/XT2OUT

70

TEST/SBWTCLK

71

PJ.0/TDO

72

PJ.1/TDI/TCLK

73

PJ.2/TMS

74

PJ.3/TCK

75

RST/NMI/SBWTDIO

76

P6.0/A0

77

P6.1/A1

78

P6.2/A2

79

P6.3/A3

80

C96 22pF50V

R2233.3K

TP11

B7 120_100MHz0.5A

R142 NL/0

C59 0.1uF 16V

R2003.3K

RD3 KP-1608EC

1 2

SBW_MMC1W_4V_2.54mm

1234

R153 NL/0

R1833.3K

R251 NL/0

R282 330

R176NL/0

R4118.2K

R210NL/0

R43010K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SRIO

SGMII

PCIE

HyperLink

Caution!

"Place ALL SERDES DC-blockingcaps on top layer adjacent to the SOC’s RX pins so that there areno additional vias"

“The HyperLink routes musthave a maximum of 2 vias andno via stubs – top layer routingrecommended”

DSP_MDC_1DSP_MDIO_1DSP_MDIO

DSP_MDC

AMCC_P9_SRIO2_RXN_C

AMCC_P10_SRIO3_RXP_C

AMCC_P8_SRIO1_RXP_CAMCC_P8_SRIO1_RXN_C

AMCC_P10_SRIO3_RXN_C

AMCC_P11_SRIO4_RXP_C

AMCC_P9_SRIO2_RXP_C

AMCC_P11_SRIO4_RXN_C

AMC0_SGMII0_RX_DN_C

DSP_SGMII_RXN_CAMC0_SGMII0_RX_DP_C

DSP_SGMII_RXP_C

DSP_MDC

DSP_MDIO

AMCC_P4_PCIe_RX1N_CAMCC_P4_PCIe_RX1P_C

AMCC_P5_PCIe_RX2N_CAMCC_P5_PCIe_RX2P_C

HyperLink_RXN1_C

HyperLink_RXP3_C

HyperLink_RXP2_CHyperLink_RXN2_C

HyperLink_RXN3_C

HyperLink_RXN0_C

HyperLink_RXP1_C

HyperLink_RXP0_C

MCMRXFLCLK_R

MCMTXPMCLK_R

HyperLink_REFCLKOUTPHyperLink_REFCLKOUTN

VCC1V8VCC3V3_AUX

VCC2V5

VCC1V8

BI DSP_MDIO_1 (28)OUT DSP_MDC_1 (28)

OUTAMCC_P11_SRIO4_TXN(11)

OUTAMCC_P9_SRIO2_TXP(11)OUTAMCC_P9_SRIO2_TXN(11)

OUTAMCC_P10_SRIO3_TXP(11)





INAMCC_P9_SRIO2_RXN(11)

INAMCC_P10_SRIO3_RXP(11)

INAMCC_P8_SRIO1_RXP(11)INAMCC_P8_SRIO1_RXN(11)





INAMC0_SGMII0_RX_DN(11)

INDSP_SGMII_RXN(28)INAMC0_SGMII0_RX_DP(11)

INDSP_SGMII_RXP(28)

OUTAMC0_SGMII0_TX_DN(11)

OUTAMC0_SGMII0_TX_DP(11)

OUTDSP_SGMII_TXN(28)

OUTDSP_SGMII_TXP(28)

OUTAMCC_P4_PCIe_TX1N(11)OUTAMCC_P4_PCIe_TX1P(11)

INAMCC_P4_PCIe_RX1N(11)INAMCC_P4_PCIe_RX1P(11)

OUTAMCC_P5_PCIe_TX2N(11)OUTAMCC_P5_PCIe_TX2P(11)

INAMCC_P5_PCIe_RX2N(11)INAMCC_P5_PCIe_RX2P(11)

INHyperLink_RXP0(30)




INHyperLink_RXN0(30)




OUTHyperLink_TXP0(30)




OUTHyperLink_TXN0(30)




OUTHyperLink_RXFLCLK(30)OUTHyperLink_RXFLDAT(30)

INHyperLink_RXPMDAT(30)INHyperLink_RXPMCLK(30)

INHyperLink_TXFLCLK(30)INHyperLink_TXFLDAT(30)

OUTHyperLink_TXPMDAT(30)OUTHyperLink_TXPMCLK(30)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_SERDES_PORTS

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_SERDES_PORTS

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_SERDES_PORTS

C


DSPM-8303E

C495 0.1uF 16V

C178 0.1uF 16V

C69 0.1uF 16V

TP3

C67 0.1uF 16V

R173 2K

C1150.1uF16VC490 0.1uF 16V

DSP1S

<Characteristic>TI_TMS320TCI6614

MCMTXPMDATF27

MCMTXFLDATG27

MCMRXPMCLKE28

MCMRXN2N29

MCMTXN2P27

MCMRXP2P29

MCMRXN3N30

MCMTXP2N27

MCMTXP3N26

MCMRXP3M30

MCMTXN3M26

MCMRXN1K29

MCMTXN1K27

MCMRXP1L29

MCMRXP0K30

MCMTXP1L27

MCMTXN0K26

MCMRXN0J30

MCMTXP0J26

MCMRXFLCLKG28

MCMRXFLDATF29

MCMTXPMCLKF26

MCMTXFLCLKG25

MCMRXPMDATF28

MCMREFCLKOUTNG30

MCMREFCLKOUTPF30

C177 0.1uF 16V

C165 0.1uF 16V

R172 2K

C60 0.1uF 16V

DSP1P


PCIETXN1AH9

PCIETXP1AH8

PCIETXP0AG10 PCIETXN0AG11

PCIERXN1AJ10

PCIERXP1AJ11

PCIERXN0AK9

PCIERXP0AK8

R175 10K

C164 0.1uF 16V

DSP1G


SGMII0RXPAG2

SGMII1RXPAH3

SGMII0RXNAG1

SGMII1RXNAH2

SGMII0TXPAE4

SGMII1TXPAF3

SGMII0TXNAE3

SGMII1TXNAF2

MDCLKAF12

MDIOAD12

C179 0.1uF 16V

C152 0.1uF 16V

DSP1F


RIOTXP1AG8

RIOTXN3AG4

RIOTXP3AG5

RIOTXN1AG7 RIOTXP0AJ7 RIOTXN0AJ8

RIOTXN2AH5

RIOTXP2AH6

RIORXN1AJ5

RIORXN3AJ1

RIORXP3AJ2

RIORXP1AJ4

RIORXP0AK5 RIORXN0AK6

RIORXN2AK2

RIORXP2AK3

C71 0.1uF 16V

C151 0.1uF 16V

C114 0.1uF16V

C481 0.1uF 16V

C176 0.1uF 16V

C149 0.1uF 16V

C74 0.1uF 16V

C132 0.1uF 16V

R196 10K

C488 0.1uF 16V

C80 0.1uF 16V

C133 0.1uF 16V

C150 0.1uF 16V

C73 0.1uF 16V

R94 22

R90 22

TP2

U13

TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

R174

100K

C68 0.1uF 16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place these resistors at theend of the trace.

DDR3 Slew-Rate Setting (DDRSLRATE[1:0]):

0 1

0 0

1 1

1 0

Fastest

Fast

Slow

Slowest

A101-1change component value

DSP0_DDR3_ECS_0#

DSP0_DDR3_EBA_0

DSP0_DDR3_EBA_1

DSP0_DDR3_EBA_2

DSP0_DDR3_EODT_0

DSP0_DDR3_EWE#

DSP0_DDR3_ERAS#

DSP0_DDR3_ECAS#

DSP0_DDR3_ECKE_0

DSP0_DDR3_EA14

DSP0_DDR3_EA15

DSP0_DDR3_EA0

DSP0_DDR3_EA1

DSP0_DDR3_EA2

DSP0_DDR3_EA3

DSP0_DDR3_EA4

DSP0_DDR3_EA5

DSP0_DDR3_EA6

DSP0_DDR3_EA7

DSP0_DDR3_EA8

DSP0_DDR3_EA9

DSP0_DDR3_EA10

DSP0_DDR3_EA11

DSP0_DDR3_EA12

DSP0_DDR3_EA13

DSP0_DDR3_ECKP_0

DSP0_DDR3_ECKN_0

U1_DDRSLRATE1U1_DDRSLRATE0

DSP0_DDR3_EODT_0U1_DDRSLRATE1U1_DDRSLRATE0

DSP0_DDR3_ECKN_0DSP0_DDR3_ECKP_0

DSP0_DDR3_ERAS#DSP0_DDR3_ECAS#

PTV15

DSP0_DDR3_ECKE_0

DSP0_DDR3_ECS_0#DSP0_DDR3_EWE#

DSP0_DDR3_EA14

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12DSP0_DDR3_EA13

DSP0_DDR3_EA15

DSP0_DDR3_ECC7DSP0_DDR3_ECC6DSP0_DDR3_ECC5DSP0_DDR3_ECC4DSP0_DDR3_ECC3DSP0_DDR3_ECC2DSP0_DDR3_ECC1DSP0_DDR3_ECC0

DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2

DSP0_DDR3_EBA_0

DSP0_DDR3_EDQ7DSP0_DDR3_EDQ6DSP0_DDR3_EDQ5DSP0_DDR3_EDQ4DSP0_DDR3_EDQ3DSP0_DDR3_EDQ2DSP0_DDR3_EDQ1DSP0_DDR3_EDQ0







DSP0_DDR3_EDQ52DSP0_DDR3_EDQ53DSP0_DDR3_EDQ54DSP0_DDR3_EDQ55

DSP0_DDR3_EDQ48DSP0_DDR3_EDQ49DSP0_DDR3_EDQ50DSP0_DDR3_EDQ51

VCC0V75VCC0V75

VCC1V5

VCC1V5VCC1V5

VCC0V75OUT DSP0_DDR3_ECS_0# (25,26)

OUT DSP0_DDR3_ECKE_0 (25,26)

OUTDSP0_DDR3_ECKN_0(25,26)OUTDSP0_DDR3_ECKP_0(25,26)

OUTDSP0_DDR3_EODT_0(25,26)

OUTDSP0_DDR3_ERAS#(25,26)OUTDSP0_DDR3_ECAS#(25,26)

OUTDSP0_DDR3_EMRESETN(25,26)

OUTDSP0_DDR3_EWE#(25,26)

OUTDSP0_DDR3_EDQSN_1(25)

OUTDSP0_DDR3_EDQSP_6(25)















OUT DSP0_DDR3_EA[0..15] (25,26)

BI DSP0_DDR3_ECC[0..7] (26)

OUTDSP0_DDR3_EBA_0(25,26)OUTDSP0_DDR3_EBA_1(25,26)OUTDSP0_DDR3_EBA_2(25,26)

BIDSP0_DDR3_EDQ[0..7](25)


OUT DSP0_DDR3_EDM_0 (25)OUT DSP0_DDR3_EDM_1 (25)OUT DSP0_DDR3_EDM_2 (25)OUT DSP0_DDR3_EDM_3 (25)OUT DSP0_DDR3_EDM_4 (25)OUT DSP0_DDR3_EDM_5 (25)

OUT DSP0_DDR3_EDM_8 (26)OUT DSP0_DDR3_EDM_7 (25)OUT DSP0_DDR3_EDM_6 (25)



BI DSP0_DDR3_EDQ[48..55] (25)


BI DSP0_DDR3_EDQ[40..47] (25)

BI DSP0_DDR3_EDQ[56..63] (25)

OUTDSP0_DDR3_EDQSP_2(25)OUTDSP0_DDR3_EDQSP_1(25)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_DDR3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_DDR3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_DDR3

C


DSPM-8303E

R15 39.2 1%

C18 0.01uF 16V R29 39.2 1%

R336 39.2 1%

R333 39.2 1%

C11 0.01uF 16V

R329 39.2 1%

C17 0.1uF 16V

C1 0.1uF 16V

R37 39.2 1%R19 39.2 1%

R44 39.2 1%

DSP1K


DDRDQS8NA13

DDRDQS3PA10 DDRDQS2PB8 DDRDQS1PB5

DDRDQS6NC25 DDRDQS5NB24

DDRDQS4PA21

DDRDQS8PB13

DDRDQS3NB10 DDRDQS2NC8 DDRDQS1NC5

DDRDQS6PB25 DDRDQS5PA24

DDRDQS4NB21

DDRDQS7NB30

DDRDQS0NA3

DDRDQS0PB3

DDRDQS7PC30

DDRA00D17

DDRA04E17

DDRA01B16

DDRA06A15DDRA05B15

DDRA13F17

DDRA15F14

DDRA07A16

DDRA11D15

DDRA14E14

DDRA09E16

DDRA10C15

DDRA12F16

DDRA03B17DDRA02C17

DDRA08D16

DDRCB07A11DDRCB06B11

DDRCB00E13

DDRCB03D13

DDRCB04C12

DDRCB01F13

DDRCB02F12

DDRCB05B12

DDRBA0A18

DDRBA1A19

DDRBA2B18

R346 39.2 1% C2 0.1uF 16V

R348 39.2 1%

R107NL/10K

R331 39.2 1%

C5 0.01uF 16V

R369 39.2 1%

R337 39.2 1%

C3 0.1uF 16V

R10810K

R16 39.2 1%

R362 39.2 1%

C7 0.01uF 16V

R326 39.2 1%

R357 39.2 1%

C14 0.1uF 16V

R9 39.2 1%

R7 39.2 1%

C13 0.01uF 16V

R34 39.2 1%

R23 39.2 1%

R11510K

R50 39.2 1%

C265 0.1uF 16V

R12345.31%

R324 39.2 1%

DSP1J


DDRRASD19

DDRCE0F19

DDRCE1F18

DDRCKE0D20

DDRCASE19

DDRODT0C18

DDRRESETC20

DDRWEB19

DDRODT1D18

DDRSLRATE1D1DDRSLRATE0E1

DDRCLKOUTP0A20

DDRCLKOUTP1C14

DDRCLKOUTN0B20

DDRCLKOUTN1B14

PTV15K4

DDRCKE1D14

R350 39.2 1%

R117NL/10K

R328 39.2 1%

C12 0.01uF 16V

R1 4.7K

DSP1L


DDRD15D6 DDRD14C6

DDRD05B4

DDRD13B6

DDRDQM1D5

DDRD11F7

DDRD12A6

DDRD04D3 DDRD03E4

DDRD01B2

DDRD09F6

DDRD10G6

DDRD06A4

DDRD02F5

DDRD00C3

DDRDQM0A2

DDRD08E5 DDRD07D4

DDRDQM4E21

DDRDQM5A23

DDRD40B23

DDRD34B22

DDRD44E24

DDRD38E22

DDRD47E25

DDRD43C23

DDRD37F22

DDRD33D21

DDRD46F24

DDRD42D24

DDRD35C22

DDRD32F20

DDRD45F23

DDRD41D23

DDRD39F21

DDRD36D22

DDRDQM3F10

DDRD20B7

DDRDQM2E7

DDRD30C11

DDRD21A9

DDRD29E11

DDRD31D11

DDRD22A7

DDRD28C9

DDRD26E10

DDRD18D8

DDRD25D10

DDRD23B9

DDRD19E8

DDRD24F9

DDRD27D9

DDRD17F8 DDRD16D7

DDRDQM8D12

DDRDQM6A27

DDRD53D25

DDRDQM7A28

DDRD49A26

DDRD51C27

DDRD59B28

DDRD55E26DDRD54D26

DDRD48B26

DDRD57B29

DDRD52C26

DDRD62D30

DDRD58C28

DDRD50B27

DDRD63D28

DDRD60D27

DDRD61D29

DDRD56A29

R32 39.2 1%

R343 39.2 1%

C15 0.1uF 16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SOC EMIF & EMU & JTAG

NAND FLASH

EMU CONN.

1.8V signal

1.8V to DSP

1.8V signal

3.3V control

Switch for JTAG emulation

EXT_EMU_DET = 0 --> External / Mezzanine Emulator

EXT_EMU_DET = 1 --> On board emulation

Power Supply for Daughter Board

60

-pin

He

ad

er

EMU_TCK_R

DSP_TCK_R

EMU_TCKR155

R450

SOC

DSP_EMU_03_R DSP_EMU_03DSP_EMU_04_R DSP_EMU_04DSP_EMU_06_R DSP_EMU_06DSP_EMU_08_R DSP_EMU_08DSP_EMU_10_R DSP_EMU_10

DSP_EMU_11_R DSP_EMU_11DSP_EMU_13_R DSP_EMU_13DSP_EMU_15_R DSP_EMU_15DSP_EMU_16_R DSP_EMU_16

DSP_EMU_18_R DSP_EMU_18

DSP_EMU_05_RDSP_EMU_05DSP_EMU_07_RDSP_EMU_07DSP_EMU_09_RDSP_EMU_09

DSP_EMU_12_RDSP_EMU_12DSP_EMU_14_RDSP_EMU_14

DSP_EMU_17_RDSP_EMU_17

DSP_EMU_02 DSP_EMU_02_R

DSP_EMU_01_R

EMU_EMU_00_R

DSP_TVD

EMU_TRST#_R

EMU_TCK_R

EMU_TDO_R

EMU_TDI_R

EMU_TMS_R

DSP_TCK_R

EMU_EMU_01

EMU_TRST#

EMU_TCK

EMU_EMU_00

EMU_EMU_00

EMU_EMU_01

EMU_TRST#_R

EMU_TCK_R

DSP_EMIFWEZ

DSP_EMIFWAIT0

DSP_EMIFD0DSP_EMIFD1DSP_EMIFD2DSP_EMIFD3DSP_EMIFD4DSP_EMIFD5DSP_EMIFD6DSP_EMIFD7

DSP_EMIFOEZDSP_EMIFWAIT0

DSP_EMIFCE0ZDSP_EMIFA12

DSP_EMIFA11

DSP_EMIFWAIT1

DSP_TRST#

DSP_TCK

DSP_TDI

DSP_TMS

DSP_TDO

EMU_TMS

EMU_TDI

EMU_TDO

DSP_EMIFCE0ZDSP_EMIFCE0Z_RDSP_EMIFCE1Z_R

DSP_EMIFWAIT0DSP_EMIFWAIT1

DSP_TCK

DSP_TMSDSP_TDIDSP_TDO

DSP_TRST#

DSP_EMU_03DSP_EMU_02

DSP_EMU_05


DSP_EMU_04

DSP_EMU_09


DSP_EMU_13


DSP_EMU_12

DSP_EMU_08

DSP_EMU_16



EMU_TRST#

EXT_EMU_DET0

EMU_EMU_00

EMU_TDO

EMU_EMU_01

EMU_TMS

EMU_TDIEMU_TCK

DSP_EMU_01DSP_EMU_00DSP_TRST#

DSP_TDIDSP_TDO

DSP_TCK

DSP_TMS

EXT_EMU_DET0

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC3V3_AUX

VCC1V8

VCC1V8_AUXVCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC5

VCC3V3_AUX

VCC1V8

OUTTRGRSTZ(31)

INNAND_WP#(31)

OUT DSP_EMIFA00 (30)OUT DSP_EMIFA01 (30)OUT DSP_EMIFA02 (30)OUT DSP_EMIFA03 (30)OUT DSP_EMIFA04 (30)OUT DSP_EMIFA05 (30)OUT DSP_EMIFA06 (30)OUT DSP_EMIFA07 (30)OUT DSP_EMIFA08 (30)OUT DSP_EMIFA09 (30)OUT DSP_EMIFA10 (30)OUT DSP_EMIFA11 (30)OUT DSP_EMIFA12 (30)OUT DSP_EMIFA13 (30)OUT DSP_EMIFA14 (30)OUT DSP_EMIFA15 (30)OUT DSP_EMIFA16 (30)OUT DSP_EMIFA17 (30)OUT DSP_EMIFA18 (30)OUT DSP_EMIFA19 (30)OUT DSP_EMIFA20 (30)OUT DSP_EMIFA21 (30)OUT DSP_EMIFA22 (30)OUT DSP_EMIFA23 (30)

BI DSP_EMIFD0 (30)BI DSP_EMIFD1 (30)BI DSP_EMIFD2 (30)BI DSP_EMIFD3 (30)BI DSP_EMIFD4 (30)BI DSP_EMIFD5 (30)BI DSP_EMIFD6 (30)BI DSP_EMIFD7 (30)BI DSP_EMIFD8 (30)BI DSP_EMIFD9 (30)BI DSP_EMIFD10 (30)BI DSP_EMIFD11 (30)BI DSP_EMIFD12 (30)BI DSP_EMIFD13 (30)BI DSP_EMIFD14 (30)BI DSP_EMIFD15 (30)

OUT DSP_EMIFCE1Z (30)

OUT DSP_EMIFBE0Z (30)OUT DSP_EMIFBE1Z (30)

OUT DSP_EMIFOEZ (30)

OUT DSP_EMIFWEZ (30)

OUT DSP_EMIFRNW (30)

IN DSP_EMIFWAIT1 (30)

INAMC_JTAG_TMS(11)

INAMC_JTAG_TDI(11)INAMC_JTAG_TCK(11)

INXDS560_IL(31)

INAMC_JTAG_RST#(11)

OUTAMC_JTAG_TDO(11)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_JTAG_EMU_AIF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_JTAG_EMU_AIF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_JTAG_EMU_AIF

C


DSPM-8303E

R112 10

R215 10

560V2_PWR1

PH_4x2V_2.54mm

2468

1357

C2890.1uF16V

R163 10

R548 4.7K

R168 10

NAND1

MICRON_MT29F1G08ABBDAHC:D

ALEC4

CEC6

CLED5

DNU1G3

DNU2G8

IO0H4

IO1J4

IO2K4

IO3K5

IO4K6

IO5J7

IO6K7

IO7J8

NC18F4

NC19F5

NC20F6

NC21F8

NC22G5

NC23G6

NC24G7

NC25H3

NC26H5

NC27H6

NC28H7

NC29J3

NC30J5

NC31L1

NC32L10

NC33L2

NC34L9

NC35M1

NC36M10

NC37M2

NC38M9

R/BC8 RED4

VSS4C5 VSS3K3 VSS2K8 VSS1F7

WEC7

WPC3

NC1A1

NC2A10

NC3A2

NC4A9

NC5B1

NC6B10

NC7B9

NC8D6

NC9D7

NC10D8

NC11E3

NC12E4

NC13E5

NC14E6

NC15E7

NC16E8

NC17F3

VCC1G4

VCC2D3

VCC3H8

VCC4J6

R513 4.75K 1%

R239 4.7K

C4080.1uF16V

R146 10

R403 4.7K

C476 8.2pF 50V

C2230.1uF16V

R497 4.75K 1%

R110 10

R133 4.7K

C13610uF16V

C2930.1uF16V

R471 49.9 1%

R483 4.75K 1%

A1B1

C1D1

PTH

PTH

EMU1

BB_30x2V_S1.27mm

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15

D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15

H1

H2

R228 10

R468 4.75K

C5540.1uF16V

C1440.1uF16V

R179 10R451 4.7K

R101 10

R124 10

R216 10

R462 4.7K

R204 10

R162 NL/10K

R372 4.7K

TP23

C1450.1uF16V

R195 10

R188 10

DSP1O


EMU00AF28

EMU01AG28

EMU02AH29

EMU03AF27

EMU04AG27

EMU05AH28

EMU06AJ29

EMU07AK29

EMU08AJ28

EMU09AH26

EMU10AK28

EMU11AG26

EMU12AJ27

EMU13AK27

EMU14AJ26

EMU15AK26

EMU16AK25

EMU17AK24

EMU18AJ24

TMSAE26

TDIAF26

TDOAD26

TCKAE28

TRSTAE27

EMIFA00L1

EMIFA01W5

EMIFA02M2

EMIFA03N3

EMIFA04P3

EMIFA05T4

EMIFA06U4

EMIFA07R4

EMIFA08R3

EMIFA09W4

EMIFA10Y5

EMIFA11P2

EMIFA12N1

EMIFA13P1

EMIFA14R2

EMIFA15T2

EMIFA16U3

EMIFA17V3

EMIFA18Y4

EMIFA19T1

EMIFA20W3

EMIFA21V2

EMIFA22AA5

EMIFA23U1

EMIFBE0ZK1

EMIFBE1ZL2

EMIFCE0ZR5

EMIFCE1ZP5

EMIFCE2ZN5

EMIFCE3ZV5

EMIFD00V1

EMIFD01AA4

EMIFD02Y2

EMIFD03W2

EMIFD04AA3

EMIFD06AB1

EMIFD07AA1

EMIFD08AB2

EMIFD09AB3

EMIFD10AC2

EMIFD11AD1

EMIFD12AB4

EMIFD13AD2

EMIFD14AC3

EMIFD15AC4

EMIFOEZL3

EMIFRNWU5

EMIFWAIT0N4

EMIFWAIT1M3

EMIFWEZT5

EMIFD05Y1

R225 4.75K

R181 10

R118 10

R517 4.7K

R154 100

R463 NL/4.75K 1%

C13710uF6.3V

R132 10

U29

TI_TXS0108EPWR

A11V

CCA

2

A23

A34

A45

A56

A67

A78

A89

OE10

B120 V

CCB

19

B218

B317

B416

B515

B614

B713

B812

GND

11

R169 10

U28

TI_TS3L301DGG

3B238

3B141

SEL24

GND818

2B239

2B142

GND716GND17

46GND6

13

A723

GND511

GND1643

A621A517

GND1540

A415A310

1B244

A281B1

47A1

4A02

VDD536

GND49GND37GND25

0B245

0B148

GND13

GND1437

GND1333

7B225

GND1230

7B128

VDD26

6B226

6B129

VDD11

5B231

5B134

GND1127

NC14

GND1022GND920

VDD419

4B232

4B135

VDD312

R147 4.7K

R120 10

R156 22

R229 10

R157 10R150 10

C5080.1uF16V

R148 22

C29210uF6.3V

R203 10

R135 10

C10610uF6.3V

R127 10

R455 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

4M SPI NOR Flash

GPIO & RSV

Core Control

SCL/SDA

JP-UART(3-5) & (4-6) : UART over 3-Pin Header J5

0x50h/0x51h1M-bit I2C EEPROM

I2C, TIMER0,1, SPI, UART

UART interference with xds560v2, workaround: Move UART connector to PCB backside and adopt 90D type.

A101-1

DSP_SCLDSP_SDA

RS232_TXRS232_RX

RS232_RX

RS232_TX

UART_MAX_RX

DSP_UARTTXD

DSP_UARTRXD_V1P8

DSP_UARTTXD_V1P8DSP_UARTCTS_V1P8

DSP_UARTRTS_V1P8

DSP_GPIO_R08DSP_GPIO_R09DSP_GPIO_R10DSP_GPIO_R11DSP_GPIO_R12DSP_GPIO_R13DSP_GPIO_R14DSP_GPIO_R15

DSP_GPIO_R05

DSP_GPIO_R07DSP_GPIO_R06

DSP_GPIO_R00

DSP_GPIO_R04DSP_GPIO_R03DSP_GPIO_R02DSP_GPIO_R01

NOR_SSPCK

NOR_SSPCS

DSP_SSPMOSI

DSP_SSPMISO

RP1FBNRP1FBP

PHYSYNCRADSYNC

NOR_WP#

EEPROM_WP

DSP_SDADSP_SCL

PH_SSPCK_RFPGA_SSPCK_R

NOR_SSPCK NOR_SSPCK_RDSP_SSPCK

UART_MAX_TXDSP_UARTTXDUART_FT_TX

DSP_UARTRXDUART_MAX_RX

UART_FT_RX

DSP_UARTRXD

UART_MAX_TX

DAC_SSPCK_RDSP_SSPCK

NOR_HD#

RADSYNC

RP1FBNRP1FBP

PHYSYNC

DSP_SDADSP_SCL

EXTFRAMEEVENT

DSP_GPIO25DSP_GPIO26DSP_GPIO27DSP_GPIO28DSP_GPIO29DSP_GPIO30DSP_GPIO31

DSP_GPIO21

DSP_GPIO23DSP_GPIO22

DSP_GPIO_R16

DSP_GPIO20

DSP_GPIO18DSP_GPIO17

DSP_GPIO24

NOR_SSPCS_RFPGA_SSPCS1_RDAC_SSPCS2_RDSP_SSPCS3_R

NOR_SSPCS

NOR_SSPMOSI_R

DSP_SSPCK_RDSP_SSPCK

UART1CTS_R

DSP_UARTRTS_V1P8UARTCTS_R

UART1TXD_R

DSP_UARTRXD_V1P8

DSP_UARTCTS_V1P8

DSP_UARTTXD_V1P8UARTTXD_R

DSP_TIMO0_RDSP_TIMO1_R

RSV01RSV03_RRSV04_RRSV05_RRSV06_R

RSV08_RRSV09_RRSV10_RRSV11_RRSV12_RRSV13_R

RSV07_R

DSP_GPIO_R09DSP_GPIO_R10DSP_GPIO_R11

DSP_GPIO_R00

DSP_GPIO_R12DSP_GPIO_R13DSP_GPIO_R14DSP_GPIO_R15

DSP_GPIO_R01DSP_GPIO_R02DSP_GPIO_R03DSP_GPIO_R04DSP_GPIO_R05DSP_GPIO_R06DSP_GPIO_R07DSP_GPIO_R08

RSV22_RRSV24_RRSV25_RRSV26_RRSV27_R

RSV15_RRSV16_RRSV17_RRSV20_RRSV21_R

RSV14_R

DSP_GPIO_R16

VCC1V8

VCC3V3_AUX

VCC3V3_AUXVCC1V8

VCC1V8

VCC1V8 VCC3V3_AUX

VCC3V3_AUX

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

IN DSP_UARTCTS (30)IN DSP_UARTRXD (30)

OUT DSP_UARTRTS (30)OUT DSP_UARTTXD (30)

BI AMC_EXP_SDA (11)OUT AMC_EXP_SCL (11)

INNOR_WP#(31)IN EEPROM_WP (31)

OUTPH_SSPCK(30)OUT FPGA_SSPCK (31)

OUTUART_FT_TX(12) IN UART_FT_RX (12)

OUT DAC_SSPCK (27)

INDSP_CORESEL0(31)INDSP_CORESEL1(31)INDSP_CORESEL2(31)

INRADSYNC(11,27)INPHYSYNC(11,27)

INAMC_RP1FBN(11)INAMC_RP1FBP(11)

BI DSP_SDA (30)

OUT DSP_SCL (30)

IN DSP_NMIZ (31)

OUT DSP_HOUT (31)

OUT DSP_BOOTCOMPLETE (31)

OUT FPGA_EXTFRAMEEVENT (31)

OUTFPGA_SSPCS1(31)OUTDAC_SSPCS2(27)OUTMISC_SSPCS3(30)

OUTDSP_SSPMOSI(27,30,31)

INDSP_SSPMISO(30,31) IN GPS_UARTRXD (27)OUT GPS_UARTTXD (27)

OUT DSP_SIM CLK (27)OUT DSP_SIM_RST (27)

BI DSP_SIM_IO (27)

OUTDSP_TIMO0(27,30,31)

INDSP_TIMI0(27,30,32)

OUTDSP_TIMO1(30,31)

INDSP_TIMI1(30,32)

BIDSP_GPIO_00(30,32)BIDSP_GPIO_01(30,32)BIDSP_GPIO_02(30,32)BIDSP_GPIO_03(30,32)BIDSP_GPIO_04(30,32)BIDSP_GPIO_05(30,32)BIDSP_GPIO_06(30,32)BIDSP_GPIO_07(30,32)BIDSP_GPIO_08(30,32)BIDSP_GPIO_09(30,32)BIDSP_GPIO_10(30,32)BIDSP_GPIO_11(30,32)BIDSP_GPIO_12(30,32)BIDSP_GPIO_13(30,32)BIDSP_GPIO_14(30,32)BIDSP_GPIO_15(30,32)BIDSP_GPIO_16(30,32)

INPPS_INTERRUPT(31)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_MISC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_MISC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_MISC

C


DSPM-8303E

R501 4.7K

TP25

R504 4.7K

C25 0.1uF 16V

TP40

C166 0.1uF 16V

U9

TI_MAX3221ECPWR

EN1

C1+2

V+3

C1-4

C2+5

C2-6

V-7

RIN8

FORCEOFF16

VCC15

GND14

DOUT13

FORCEON12

DIN11

INVALID10

ROUT9

R253 4.7K

COM_SEL1(4-6)MINIJUMPER_2_2.54mm

R505 NL/0

R25 4.7K

R507 NL/0

R470 10K

R263 10

R205 10K

R28 2K

C167 0.1uF 16V

R496 10

R39NL/0

R446 331%

R274 4.7K

U1

TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

TP28

R254 10

R17 10

R27 10K

R434 NL/0

R31 2KR490 10

C2530.1uF16V

R278 4.7K

C29 0.1uF 16V

R467 10

R227 10

DSP1N


BOOTCOMPLETEF2

EXTFRAMEEVENTAE13

NMIJ2

HOUTG4

SDAAE17

SCLAF17

CORESEL0G3

CORESEL1J4

CORESEL2H3

RP1FBNAH30

RP1FBPAG30

PHYSYNCAJ30

RADSYNCAF29

R238 10

R426 NL/0

TP29

R218 NL/0

R236 4.7K

C2970.1uF16V

R461 331%

C2520.1uF16V

R478 10

U27

TI_SN74ALVC125PWR

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y83A93OE104Y114A124OE13VCC14

R459 NL/0

TP39

R226 4.7K

R288 10

DSP1I


GPIO02AG19

GPIO11AK22

GPIO15AH20

GPIO05AJ19

GPIO03AH19

GPIO12AJ21

GPIO09AG18

GPIO04AK19

GPIO13AG20

GPIO01AF19

GPIO10AF18

GPIO06AK18

GPIO07AJ18

GPIO14AK21

GPIO08AH18

GPIO00AJ20

GPIO16AG23

GPIO18AF21

GPIO20AH23

GPIO21AE19

GPIO19AG21

GPIO17AH24

GPIO22AH22

GPIO23AJ23

GPIO24AJ22

GPIO25AF20

GPIO26AH21

GPIO27AE20

GPIO28AF23

GPIO29AF22

GPIO30AG24

GPIO31AF24

RSV07E2

RSV27R25

RSV21H5

RSV17AD4

RSV22AD6

RSV12H25RSV11AC7

RSV13J24

RSV06D2

RSV15AE1

RSV08H2

RSV24AH12

RSV20AE23

RSV05AD24RSV04AE24RSV03J1

RSV26V25RSV25AH11

RSV01AE21

RSV09F1

RSV16AD5

RSV10AD7

RSV14L25

R289 4.7K

TP38

R511 10

B372200pF 0.7A

1

2

3

R256 4.7K

R469 10K

R3744.7K

C90.1uF16V

TP31

R237 4.7K

R477 10

R442 10

R494 10

R177 NL/0

R435 NL/0

R264 4.7K

R530 NL/10K

R409 NL/0

R18 4.7K

TP30

R259 4.7K

R285 4.7K

R399 0

TP37

R508 NL/0

R448 NL/0

R389 NL/0

R241 4.7K


R380

R512 10

R258 4.7K

TP27

R515 10

R484 10

R475 10

R381 NL/0

R439 NL/0

R400 NL/0

TP26

R373 4.7K

R498 10

R243 4.7K

TP34

R21 10K

R262 4.7K

U26

TI_SN74AVC4T245PWR

VCCA1

1DIR2

2DIR3

1A14

1A25

2A16

2A27

GND18

GND29 2B210 2B111 1B212 1B113 2OE14 1OE15 VCCB16

R479 10

EEPROM1

ST_M24M01-HRMN6TP

DU1

E12

E23

VSS4

SDA5SCL6WC7VCC8

R395 NL/0

R40NL/0

R525 NL/10K

R502 NL/0

R393 NL/0

R485 10

C2981uF6.3V

R529 10K

R410

R458 331%

R275 4.7K

R271 4.7K

R488 10

R526 10K

R3754.7K

COM1

W_3V_2.54mm

21

3

R487 10

COM_SEL1

PH_3x2V_2.54mm

135

246

R22100K

R500 10

R3254.7K

R495 10

R276 4.7K

R26 4.7K

C10 0.1uF16V

U8

NUMONYX_N25Q032A11ESE40F

VCC8

HOLD/DQ37S

1

C6

DQ05

DQ12

W/Vpp/DQ23

VSS4

TP36

C2550.1uF16V

R167 NL/0

R466 331%

R270 10

TP35

R272 10

C16

0.1uF16V

C296 0.1uF 16V

R413 NL/0

R266 4.7K

TP33

R476 10

C21 0.1uF 16V

R204.7K

R506 NL/0

TP32

DSP1R


SPICLKAH14

SPISCS0AG15

SPISCS3AJ15 SPISCS2AK15 SPISCS1AF15

TIMO1AF25

TIMI1AE25

TIMO0AH25

TIMI0AJ25

UART0RXDAG17UART0RTSAK17UART0CTSAJ17

UART0TXDAH16

SPISCS4AH15

SPIDINAG14 SPIDOUTAF14 UART1CTS

AK16

UART1RTSAJ16

UART1RXDAF16

UART1TXDAG16

USIMCLKAH13USIMIOAF13

USIMRSTAG13

R396 NL/0

R510 10

R35

4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SOC AIF SFP CONN

TX_FAULT

High(2.0V - VCCT)

Low(< 0.8V)

Output indicates a laser fault of same kind

Normal Operation

Strip pin TX_DISABLE

High(2.0V - 3.465V)

Low (< 0.8V)

Transmitter off

Transmitter on

Strip pin

RATESELECT

High(2.0V - 3.465V)

Low (< 0.8V)/ OPEN

Full Bandwidth

Reduced Bandwidth

Strip pinLOS

High(2.0V - VCCT)

Low (< 0.8V)

thisoutput indicates the received optical power is below the worst-case receiver sensitivity (asdefined by the standard in use)

Strip pin

Normal Operation

NOTE :MOD_DEF0 is grounded by the module to indicate that the module is present

AIF4_RXN_CAIF4_RXP_C

AIF5_RXN_CAIF5_RXP_C

SFP_AIF0_TXNSFP_AIF0_TXP

SFP_AIF0_RXPSFP_AIF0_RXN





LOS_1RATESELECT_1

MOD1_SDAMOD1_SCKMOD1_DEF0

MOD1_SDAMOD1_SCK

MOD1_DEF0

MOD2_SDAMOD2_SCK

MOD2_DEF0

MOD3_SDAMOD3_SCK

MOD3_DEF0

MOD4_SDAMOD4_SCK

MOD4_DEF0

TX_DISABLE1

TX_DISABLE1TX_DISABLE2TX_DISABLE3TX_DISABLE4

TX_FAULT1

TX_FAULT1TX_FAULT2TX_FAULT3TX_FAULT4

LOS_2RATESELECT_2


TX_DISABLE2TX_FAULT2




TX_FAULT3TX_DISABLE3

RATESELECT_3LOS_3


TX_FAULT4TX_DISABLE4

RATESELECT_4LOS_4

LOS_1LOS_2LOS_3LOS_4

RATESELECT_1RATESELECT_2RATESELECT_3RATESELECT_4

SFP_AIF3_RXNSFP_AIF3_RXPSFP_AIF2_RXNSFP_AIF2_RXPSFP_AIF1_RXNSFP_AIF1_RXPSFP_AIF0_RXNSFP_AIF0_RXP

SFP_AIF3_TXN

SFP_AIF1_TXP

SFP_AIF2_TXN

SFP_AIF1_TXN

SFP_AIF0_TXPSFP_AIF0_TXN

SFP_AIF3_TXP

SFP_AIF2_TXP

VCCT1VCCR1

VCCT3VCCR3

VCCT4VCCR4

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUXVCC3V3_AUX

VCCT2VCCR2

VCC3V3_AUX VCCT1

VCCR1

VCCT4

VCCR4

VCCT2

VCCR2

VCCT3

VCCR3

OUT AMCC_P17_AIF4_TXN (11)OUT AMCC_P17_AIF4_TXP (11)

IN AMCC_P18_AIF5_RXN (11)IN AMCC_P18_AIF5_RXP (11)IN AMCC_P17_AIF4_RXN (11)IN AMCC_P17_AIF4_RXP (11)

OUT AMCC_P18_AIF5_TXN (11)OUT AMCC_P18_AIF5_TXP (11)

OUTLOS_1(32)OUTLOS_2(32)OUTLOS_3(32)OUTLOS_4(32)

OUTTX_FAULT2(32)OUTTX_FAULT3(32)OUTTX_FAULT4(32)

OUTTX_FAULT1(32)

BIMOD1_SDA(31)BIMOD1_SCK(31)

BIMOD2_SDA(32)BIMOD2_SCK(32)

BI MOD3_SDA (31)BI MOD3_SCK (31)

BI MOD4_SDA (31)BI MOD4_SCK (31)

INTX_DISABLE(32)

INRATESELECT(32)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_AIF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_AIF

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_AIF

C


DSPM-8303E

C174 10uF6.3V

R222 4.7K

R242 4.7K

L6 1.5uH 0.7A

R260 4.7K

R209 4.7K

L5 1.5uH 0.7A

R519 0

C450 0.1uF16V

C432 0.1uF16V

R261 4.7K

R257 4.7K

R232 4.7K

R509 4.7K

C559 10uF6.3V

C102 0.1uF 16V

R465 4.7K

L13 1.5uH 0.7A

R489 0

R265 4.7K

C5410.1uF16V

R520 0

C175 10uF6.3V

R220 4.7K

R481 4.7K

C433 0.1uF16V

R472 4.7K

R499 0

R286 4.7K

C453 0.1uF16V

C5420.1uF16V

R231 4.7K

R279 4.7K

C103 0.1uF 16V

R456 0

R267 4.7K

R230 33K

L14 1.5uH 0.7A

C418 10uF6.3V

C551 0.1uF16V

R208 4.7K

DSP1M


AIFRXN5AB29

AIFRXP5AC29

AIFRXN4AA30

AIFRXP4AB30

AIFRXN3W30

AIFRXP3V30

AIFRXN2Y29

AIFRXP2W29

AIFRXN1R30

AIFRXP1T30

AIFRXN0T29

AIFRXP0U29

AIFTXN5AB27

AIFTXP5AC27

AIFTXN4AB28

AIFTXP4AA28

AIFTXN3W28

AIFTXP3V28

AIFTXN2Y27

AIFTXP2W27

AIFTXN1T28

AIFTXP1R28

AIFTXN0T27

AIFTXP0U27

R290 0

C163 0.1uF16V

SFP1

SFP_80H

A1A1

A2A2

A3A3

A4A4

A5A5

A6A6

A7A7

A8A8

A9A9

A10A10

A11A11

A12A12

A13A13

A14A14

A15A15

A16A16

A17A17

A18A18

A19A19

A20A20

B1B1

B2B2

B3B3

B4B4

B5B5

B6B6

B7B7

B8B8

B9B9

B10B10

B11B11

B12B12

B13B13

B14B14

B15B15

B16B16

B17B17

B18B18

B19B19

B20B20

C1C1

C2C2

C3C3

C4C4

C5C5

C6C6

C7C7

C8C8

C9C9

C10C10

C11C11

C12C12

C13C13

C14C14

C15C15

C16C16

C17C17

C18C18

C19C19

C20C20

D1D1

D2D2

D3D3

D4D4

D5D5

D6D6

D7D7

D8D8

D9D9

D10D10

D11D11

D12D12

D13D13

D14D14

D15D15

D16D16

D17D17

D18D18

D19D19

D20D20

NPTH_1H1

NPTH_2H2

NPTH_3H3

NPTH_4H4

PTH_1H5

PTH_2H6

PTH_3H7

PTH_4H8

PTH_5H9

PTH_6H10

PTH_7H11

PTH_8H12

PTH_9H13

PTH_10H14

PTH_11H15

PTH_12H16

PTH_13H17

PTH_14H18

PTH_15H19

PTH_16H20

PTH_17H21

PTH_18H22PTH_19H23PTH_20H24PTH_21H25PTH_22H26PTH_23H27PTH_24H28PTH_25H29PTH_26H30PTH_27H31

C407 10uF6.3V

R516 33K

C431 10uF6.3V

R277 4.7K

R521 0

C93 0.1uF 16V

C4520.1uF16V

C3690.1uF16V

C550 0.1uF16V

C92 0.1uF 16V

C168 0.1uF16V

C4510.1uF16V

R457 33K

C37210uF6.3V

R493 4.7K

L16 1.5uH 0.7A

R273 4.7K

C4540.1uF16V

R244 4.7K

L15 1.5uH 0.7A

C406 10uF6.3V

C4390.1uF16V

R247 4.7K

C1690.1uF16V

R284 33K

L11 1.5uH 0.7A

C558 10uF6.3V

R518 0

R217 4.7K

L12 1.5uH 0.7A

C1620.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

(HCSL)

(LVDS)

All blocking capacitors should be placed near SOC to keep

connecting routes short and minimize vias

Layout From Clock Device

REF_CLK output

Default: IN2/CDCE62005

SOC CLOCK / RESET

Smart Reflex DISABLE THIS FUNCTION

note: keep the signal of RP1CLKP/N_C stubs very short

DSP_PORZ

DSP_RESETFULLZ

DSP_RESETZ

FPGA_ICS557_SEL

DSP_PCIECLKP

PCIECLKP_ICS557PCIECLKN_ICS557

DSP_PCIECLKPDSP_PCIECLKN

DSP_PCIECLKN

FPGA_ICS557_PD#

FPGA_ICS557_OE

RP1CLKP_CRP1CLKN_C

PCIECLKN_R

PCIECLKP_R PCIECLKP_RPCIECLKN_R

DSP_VIDADSP_VIDB

DSP_VIDCDSP_VIDS

UCD9222_VIDBUCD9222_VIDA

UCD9222_VIDCUCD9222_VIDS

VID_OE#

VID_OE#

CORECLKN_CCORECLKP_C

DDRCLKN_CDDRCLKP_C

MCMCLKN_CMCMCLKP_C

RP1CLKP_CRP1CLKN_C

SYSCLKP_CSYSCLKN_C

SRIOSGMIICLKN_CSRIOSGMIICLKP_C

DSP_PCIECLKNDSP_PCIECLKP

PCIECLKN_CPCIECLKN_CPCIECLKP_CPCIECLKP_C

PASSCLKN_CPASSCLKP_C

DSP_PORZ

DSP_RESETZ

DSP_RESETFULLZ

DSPCLKSEL_R

RSV_VD_RRSV_VCL_R

DSP_VD DSP_VDDSP_VCL DSP_VCL DSP_VCL_1

DSP_VD_1

RP1CLKN_CRP1CLKP_C

VCC3V3_AUX VCC3V3_AUX_ICS557

VCC3V3_AUX_ICS557

VCC3V3_AUX

VCC3V3_AUX_ICS557

VCC3V3_AUXVCC1V8 VCC3V3_AUX

VCC1V8

VCC3V3_AUX

VCC1V8

VCC3V3_AUXVCC1V8

VCC1V8

INPCIECLKN(23)INPCIECLKP(23)

INFPGA_ICS557_PD#(31)

INFPGA_ICS557_OE(31)

INFPGA_ICS557_SEL(31)

INPCIE_REF_CLK_N(11)

INPCIE_REF_CLK_P(11)

INAMC_RP1CLKP(11)INAMC_RP1CLKN(11)

OUT UCD9222_VIDA (34)OUT UCD9222_VIDB (34)OUT UCD9222_VIDC (34)OUT UCD9222_VIDS (34)

INVID_OE#(32)

INCORECLKP(24)INCORECLKN(24)

INDDRCLKN(22)INDDRCLKP(22)

INMCMCLKN(23)INMCMCLKP(23)

INRP1CLKP(24)INRP1CLKN(24)

INSYSCLKP(24)INSYSCLKN(24)

INSRIOSGMIICLKN(23)INSRIOSGMIICLKP(23)

INPASSCLKN(24)INPASSCLKP(24)

OUT DSP_SYSCLKOUT (31)

IN DSP_PORZ (31)

IN DSP_RESETZ (31)

IN DSP_LRESETZ (31)

IN DSP_RESETFULLZ (31)

OUT DSP_RESETSTAT# (31)

IN DSP_LRESETNMIENZ (31)

IN DSP_DSPCLKSEL (31,32)

IN DSP_PACLKSEL (31)

BI DSP_VD_1 (31)OUT DSP_VCL_1 (31)

IN PCA9306_EN (31)

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_CLOCK & Smart-Reflex VID

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

R394 4.7K

R221 1K

C111 NL/0.1uF 16V

C155 0.1uF 16V

R61NL/100K

R587 0

C40.1uF16V

C113 0.1uF 16V

R322 475 1%

C110 NL/0.1uF 16V

C1990.01uF16V

C43 NL/0.1uF16V

R565 100

R453 NL/1K

C23410uF6.3V

R1110K

C108 0.1uF 16V

C50 0.1uF 16V

R589NL/1K

C156 0.1uF 16V

C135 0.1uF 16V

U7TI_SN74AVC4T245PWR

<Characteristic>

VCCA1

1DIR2

2DIR3

1A14

1A25

2A16

2A27

GND18


U24

IDT_ICS557GI-08LFT

VDD_1

1

IN12

IN13

PD4

IN25

IN26

OE7

GND_1

8

IREF9

VDD_2

10

VDD_3

11

GND_2

12

GND_3

13

CLK14CLK15

SEL16

R566 0R561 150 1%

R63 NL/10K

R397 4.7K

R314 10K

C53 0.1uF 16V

C153 0.1uF 16V

C134 0.1uF 16VR452 1K

C478 0.1uF 16V

R588 NL/100

R4710K

R71 NL/0

C477 0.1uF 16V C52 0.1uF 16V

C154 0.1uF 16V

DSP1Q


VCNTL2G29

VCNTL3H29

VCNTL1G26VCNTL0H28

VCLJ28

VDH27

C23 NL/0.1uF16V

U10NL/TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

R4610K

R563 10K

C56 0.1uF 16V

R234 NL/1K

R155 0

R1210K

C2370.01uF16V

R92 NL/0

R553 150 1%

C475 0.1uF 16V

R73 NL/10K

R554 100

R1310K

R10 33 1%

R4810K

C23510uF6.3V

C479 0.1uF 16V

R552 33 1%

C190.1uF16V

TP24

R562NL/1K

C2360.01uF16V

R8 10K

R4510K

R321 10K

R315 NL/10K

R62 NL/10K

R556 33 1%

R1410K

B40

2200pF700mA

1

2

3

R88 NL/10K

R503 4.7K

DSP1H


SYSCLKOUTAD28

RP1CLKNAE29

ALTCORECLKNAD25

ALTCORECLKPAC25

SYSCLKNAD30

SYSCLKPAE30

SRIOSGMIICLKPAK12

PCIECLKPAK13 PCIECLKNAJ13

DDRCLKPB1 DDRCLKNC1

MCMCLKPE29 MCMCLKNE30

RP1CLKPAF30

PORAE22

LRESETNMIENH1

RESETG2

RESETSTATH4

LRESETF3

RESETFULLG1

SRIOSGMIICLKNAK11

PASSCLKNAK14

PASSCLKPAJ14

CORECLKSELAC26

PACLKSELK3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.8V / 1.5VPlace near to SOC

Place near to SOC

Place near to SOC pins

Place near to SOC pins Place near to SOC pins


VDDR_MCM

VDDR_PCI

VDDR_SGMII

VDDR_SRIO

VDDR_AIF2VDDR_AIF1 VDDA18V3

VDDA18V2VDDA18V1

VCC1V5

VCC1V8

VCC1V5

VCC1V5

VCC1V5

VCC1V8

VCC1V8

VCC1V5

VCC1V5 VCC1V5

VCC1V5

VCC1V5

VCC1V8

VCC1V5

VCC1V5

VCC1V8

VCC1V5

VCC_VREFSSTL

VCC1V0

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_POWERA

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_POWERA

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_POWERA

C


DSPM-8303E

C437560pF50V

C5300.1uF16V

C4830.01uF16V

B102200pF0.7A

1

2

3

C35560pF50V

C318560pF50V

C3660.1uF16V

C3250.01uF16V

C323560pF50V

B112200pF0.7A

1

2

3

C4380.01uF16V

C5090.1uF16V

C360.1uF16V

C34560pF50V

C4691000pF50V

C3520.01uF16V

C388560pF50V

C391560pF50V

C5534.7uF6.3V

C1414.7uF6.3V

C4561000pF50V

C362560pF50V

C344560pF50V

C3550.1uF16V

B242200pF0.7A

1

2

3

B232200pF0.7A

1

2

3

C4930.01uF16V

C3260.01uF16V

C3920.01uF16V

C5270.1uF16V

C448560pF50V

C3564.7uF6.3V

C5280.01uF16V

C4701000pF50V

C4710.01uF16V

C3380.01uF16V

C435560pF50V

C3280.01uF16V

C3350.01uF16V

C55210uF6.3V

C4360.1uF16V

B192200pF0.7A

1

2

3

C4034.7uF6.3V

C346560pF50V

C72100uF6.3V

C4721000pF50V

C353560pF50V

B132200pF0.7A

1

2

3

B222200pF0.7A

1

2

3

C3901000pF50V

C4280.1uF16V

C7510uF6.3V

C3540.1uF16V

C526560pF50V

C4921000pF50V

C482560pF50V

C5291000pF50V

C380.1uF16V

C442560pF50V

C4680.1uF16V

C531560pF50V

C4460.1uF16V

C364560pF50V

B182200pF0.7A

1

2

3

C3210.01uF16V

C415560pF50V

C3240.1uF16V

DSP1D


VDDS18_1_2H22

VDDS18_1_3G23

VDDS18_3_4J9

VDDS18_3_5K6

VDDS18_3_6L7

VDDS18_3_7M6

VDDS18_3_8N7

VDDS18_3_9P6

VDDS18_3_10R7

VDDS18_3_11T6

VDDS18_3_2AA7

VDDS18_3_3W7

VDDS18_1_0J23

VDDS18_2_0AB22

VDDS18_2_1AC13

VDDS18_2_2AC15

VDDS18_2_3AC23

VDDS18_2_4AD16

VDDS18_2_5AD18

VDDS18_2_6AD20

VDDS18_2_7AD22

VDDS18_2_8AE15

VDDS18_2_9AC17

VDDS18_2_10AC19

VDDS18_2_11AC21

VDDS15_0H20

VDDS15_1J17

VDDS15_10H10

VDDS15_11H12

VDDS15_12H14

VDDS15_13H16

VDDS15_14H18

VDDS15_15G15

VDDS15_16G11

VDDS15_17G13

VDDS15_18G19

VDDS15_19G17

VDDS15_2J19

VDDS15_3H8

VDDS15_4J11

VDDS15_5J13

VDDS15_6J15

VDDS15_7G21

VDDS15_8G7

VDDS15_9G9

VDDS18_3_12U7

VDDS18_3_13Y6

VDDS18_3_14J7

VDDS18_3_15V6

VDDS18_3_1L5VDDS18_3_0AB6

VDDS18_1_1H24

VDDS15_20J21

VREFHSTLF15

C361560pF50V

C3764.7uF6.3V

C171560pF50V

C4980.1uF16V

R751K1%

C5120.01uF16V

C1700.01uF16V

C3600.1uF16V

C3650.1uF16V

C341560pF50V

C4170.01uF16V

C363560pF50V

DSP1B


VDDARR_5W21

VDDARR_6Y10

VDDARR_7L21

VDDARR_8L9

VDDR_AIF1AA24

VDDR_MCMN24

AVDDA1AB25

VDDARR_1N9

AVDDA3AD14

VDDARR_10M20

VDDARR_3V20

VDDARR_9AA9

VDDARR_11M10

VPP2J6VDDR_PCIE

AF9VPP1

H6

AVDDA2J5

VDDARR_0N21

VDDARR_2AB10

VDDARR_4Y20

VDDR_AIF2U24

VDDR_SGMIIAC5

VDDR_SRIOAE5

C4650.1uF16V

C343560pF50V

R761K1%

C405560pF50V

C3270.01uF16V

C4141000pF50V

C322560pF50V

C83100uF6.3V

C4801000pF50V

C3190.01uF16V

C215100uF6.3V

C370.1uF16V

C466560pF50V

B142200pF0.7A

1

2

3

C4670.1uF16V

C320560pF50V

C4940.1uF16V

C4160.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

0.85V - 1.05V (CVDD) (Smart Reflex)


Fix_1.0V(VCC1P0)


Place near to SOC



CVDD

CVDD

VDDT VDDT2

VDDT2

VDDT

VCC1V0

VCC1V0

CVDD

CVDDCVDD

CVDD

Title


Date: Sheet of


TMS320TCI6614 A101

Title = SOC_POWERB

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Title = SOC_POWERB

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Title = SOC_POWERB

C


DSPM-8303E

C4260.01uF16V

C4250.01uF16V

C370560pF50V

C50747uF6.3V

C473560pF50V

C447560pF50V

C3970.01uF16V

C499100uF6.3V

C462100uF6.3V

B172200pF0.7A

1

2

3

C45710uF6.3V

C367560pF50V

C389560pF50V

C4850.1uF16V

C854.7uF6.3V

C347560pF50V

C422560pF50V

C404560pF50V

C4440.01uF16V

DSP1A


VDD_0P18

VDD_1P20

VDD_2M14

VDD_3M18

VDD_4L17

VDD_5M12

VDD_6L15

VDD_7L19

VDD_8M16

VDD_9K16

VDD_10K20

VDD_11L13

VDD_12K8

VDD_13K22

VDD_14K14

VDD_15K18

VDD_16L11

VDD_17R17

VDD_18U9

VDD_19V10

VDD_20V16

VDD_21V18

VDD_22U19

VDD_23U21

VDD_24V12

VDD_25V14

VDD_26R9

VDD_27Y12

VDD_28W9

VDD_29Y14

VDD_30W17

VDD_31AA11

VDD_32W19

VDD_33M22

VDD_34T10

VDD_35T14

VDD_36N19

VDD_37N17

VDD_38AB18

VDD_43T22

VDD_44T16

VDD_45T12

VDD_46AB20

VDD_47P12

VDD_48P10

VDD_49U13

VDD_50U11

VDD_51AB8

VDD_52M8

VDD_53AB16

VDD_54N11

VDD_55N15

VDD_56P14

VDD_57P16

VDD_58U15

VDD_59U17

VDD_60R13

VDD_61R11

VDD_62P22

VDD_63P8

VDD_64N13

VDD_65Y8

VDD_66Y18

VDD_67Y16

VDD_68AB14

VDD_69AB12

VDD_70AA21

VDD_71AA15

VDD_72AA19

VDD_73AA13

VDD_74AA17

VDD_75R19

VDD_76W13

VDD_77V8

VDD_78K12

VDD_79K10

VDD_80AC9

VDD_39T20

VDD_40T18

VDD_41T8

VDD_81W11

VDD_82W15

VDD_83R15

VDD_84R21

VDD_42V22

VDD_85Y22

C3990.1uF16V

C373560pF50V

C3930.1uF16V

C401560pF50V

C4740.01uF16V

C3820.01uF16V

C1054.7uF6.3V

C4000.1uF16V

C441560pF50V

C395560pF50V

C358560pF50V

C4230.01uF16V

C50210uF6.3V

C384560pF50V

C4450.1uF16V

C501560pF50V

C3980.01uF16V

C4210.01uF16V

C463100uF6.3V

C3800.01uF16V

C4400.01uF16V

C381560pF50V

C4020.01uF16V

C4200.1uF16V

C357560pF50V

C3960.01uF16V

C50447uF6.3V

C443560pF50V

C4550.1uF16V

C500100uF6.3V

C359560pF50V

C387560pF50V

C486560pF50V

C45947uF6.3V

C3830.1uF16V

C385560pF50V

DSP1C


VDDT_0T23

VDDT_1AB23

VDDT_2K23

VDDT_3K25

VDDT_4L24

VDDT_5M23

VDDT_6N25

VDDT_7P23

VDDT_8R24

VDDT_9R26

VDDT_10U26

VDDT_11V23

VDDT_12W24

VDDT_13W26

VDDT_14Y23

VDDT_15Y25

VDDT2_0AC11

VDDT2_1AD10

VDDT2_2AF6

VDDT2_3AF8

VDDT2_4AD8

VDDT2_5AE9

VDDT2_6AF10

VDDT_16T25

VDDT2_7AE11

VDDT2_8AE7

VDDT_17AA26

C386560pF50V

C4290.1uF16V

B122200pF0.7A

1

2

3

C424560pF50V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_GND

B


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_GND

B


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

SOC_GND

B


DSPM-8303E

DSP1E


VSS_0AE8

VSS_1K5

VSS_2L26

VSS_3M17

VSS_4M9

VSS_5N6

VSS_6P28

VSS_7R20

VSS_8A14

VSS_10AB13

VSS_11AC1

VSS_13AD3

VSS_14AG6

VSS_15AJ9

VSS_16C21

VSS_17E3

VSS_18G20

VSS_20J25

VSS_21K2

VSS_22K28

VSS_23K7

VSS_24L10

VSS_25L12

VSS_26L14

VSS_27L16

VSS_28L18

VSS_29L20

VSS_31L23

VSS_32L28

VSS_33L30

VSS_35L6

VSS_36L8

VSS_37M1

VSS_38M11

VSS_39M13

VSS_40M15

VSS_42M21

VSS_43M24

VSS_44M27

VSS_45M28

VSS_46M29

VSS_47M4

VSS_48M5

VSS_49M7

VSS_50N10

VSS_51N12

VSS_53N16

VSS_54N2

VSS_55N20

VSS_56N22

VSS_57N23

VSS_58N28

VSS_59N8

VSS_60P11

VSS_61P13

VSS_62P15

VSS_64P21

VSS_65P24

VSS_66P25

VSS_67P26

VSS_68P30

VSS_69P4

VSS_70P7

VSS_71P9

VSS_72R1

VSS_73R10

VSS_75R16

VSS_76R18

VSS_77R22

VSS_78R23

VSS_79R27

VSS_80R29

VSS_81R6

VSS_82R8

VSS_83T11

VSS_84T13

VSS_85T17

VSS_87A12

VSS_88A17

VSS_89A22

VSS_90A25

VSS_91A30

VSS_92A5

VSS_93A8

VSS_94AF1

VSS_95K9

VSS_96L4

VSS_98N18

VSS_99P19

VSS_100R14

VSS_101T15

VSS_102AB17

VSS_103AB19

VSS_104AB21

VSS_105AB24

VSS_106AB26

VSS_109AB7

VSS_110AB9

VSS_111AC12

VSS_112AC14

VSS_113AC16

VSS_114AC18

VSS_115AC20

VSS_116AC22

VSS_117AC24

VSS_118AC28

VSS_120AC6

VSS_121AD11

VSS_122AD13

VSS_123AD15

VSS_124AD17

VSS_125AD19

VSS_126AD21

VSS_127AD23

VSS_128AD29

VSS_129AD9

VSS_131AE14

VSS_132AE16

VSS_133AE18

VSS_134AE2

VSS_135AE12

VSS_136AD27

VSS_137AF11

VSS_138AG22

VSS_139AF4

VSS_140AF7

VSS_141AG12

VSS_142AH27

VSS_143AK20

VSS_144AG25

VSS_9AA18

VSS_19H26

VSS_30L22

VSS_41M19

VSS_52N14

VSS_63P17

VSS_74R12

VSS_86A1

VSS_97M25

VSS_108AB5

VSS_119AC30

VSS_145AG3

VSS_130AE6

VSS_12AF5

VSS_34AG29

VSS_107G24

DSP1T


VSS_168E12 VSS_167C7

VSS_165C29 VSS_164C24 VSS_163C2 VSS_162C19 VSS_161C13 VSS_160C10 VSS_159AK7 VSS_158AK4 VSS_157AK30 VSS_156AK10

VSS_154AJ6 VSS_153AJ3 VSS_152AJ12 VSS_151AH4 VSS_150AK23 VSS_149AH17 VSS_148AH10 VSS_221

J29

VSS_222J3

VSS_224K11

VSS_166C4

VSS_155AK1

VSS_223J8

VSS_225K13

VSS_226K15

VSS_227K17

VSS_228K19

VSS_229K21

VSS_230K24

VSS_231AA20

VSS_232AA2

VSS_233AA16

VSS_234AA14

VSS_235AA12

VSS_236AA10

VSS_237T19

VSS_238T21

VSS_239T24

VSS_240T26

VSS_241T3

VSS_242T7

VSS_243T9

VSS_244U10

VSS_245U12

VSS_246U14

VSS_247U16

VSS_248U18

VSS_249U2

VSS_250U20

VSS_251U22

VSS_252U23

VSS_253U25

VSS_182AB15 VSS_181AB11 VSS_180AA8 VSS_179AA6 VSS_178AA29 VSS_177AA27 VSS_176AA25 VSS_175AA23 VSS_174AA22 VSS_173AE10 VSS_172E27 VSS_171E20 VSS_170E18 VSS_169E15

VSS_254U28

VSS_255U30

VSS_256U6

VSS_257U8

VSS_258V11

VSS_259V13

VSS_260V15

VSS_261V17

VSS_262V19

VSS_263V21

VSS_264V24

VSS_265V26

VSS_266V27

VSS_267V29

VSS_268V4

VSS_198G16 VSS_197G14 VSS_196G12 VSS_195G10 VSS_194F4 VSS_193F25 VSS_192F11 VSS_191E9 VSS_190E6 VSS_189E23 VSS_188C16 VSS_187AH7

VSS_184AC8 VSS_183AC10

VSS_291Y28

VSS_292Y3

VSS_293Y30

VSS_185Y7

VSS_186Y9

VSS_220J27

VSS_219J22 VSS_218J20 VSS_217J18 VSS_216J16 VSS_215J14 VSS_214J12 VSS_213J10 VSS_212H9 VSS_211H7 VSS_210H30 VSS_209H23 VSS_208H21 VSS_207H19 VSS_206H17 VSS_205H15 VSS_204H13 VSS_203H11 VSS_202G8 VSS_201G5 VSS_200G22 VSS_199G18

VSS_269V7

VSS_270V9

VSS_271W1

VSS_272W10

VSS_273W12

VSS_274W14

VSS_275W16

VSS_276W18

VSS_277W20

VSS_278W22

VSS_279W23

VSS_280W25

VSS_281W6

VSS_282W8

VSS_283Y11

VSS_284Y13

VSS_285Y15

VSS_286Y17

VSS_287Y19

VSS_288Y21

VSS_289Y24

VSS_146AG9

VSS_147AH1

VSS_290Y26

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK GEN1 ( DDR3)

66.67MHz Output

A101-1Add a 100 ohm between C46 and C51 for DDR3 referce clock termination resistor needed

REFCLK1_PD# REFCLK1_PD#

CLOCK1_SSPCKCLOCK1_SSPCS1

CLOCK1_SSPSOCLOCK1_SSPSI

VCC3V3_AUX VCCPLLD1

VCC3V3_AUX

VCC3V3_AUX VCCPLLA1

VCC_VCO1

VCC3V3_AUX

VCCPLLD1

VCC_VCO1

VCC3V3_AUX

VCCPLLA1

INCLOCK1_SSPCS1(32)INCLOCK1_SSPCK(32)INCLOCK1_SSPSI(32)OUTCLOCK1_SSPSO(32)

INREFCLK1_PD#(32)

OUT DDRCLKP (18)OUT DDRCLKN (18)

OUT CLOCK1_PLL_LOCK (32)

INREFCK_N(23)INREFCK_P(23)

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN1

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN1

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN1

C


DSPM-8303E

C30 10uF 6.3V

C281uF6.3V

R113 10K

C401uF6.3V

CLK1

TI_CDCE62002RHBT

VCC_AUX

1

AUX_IN2

VBB

3

VCC_PLLD

4

PD6

SPI_MISO7 SPI_MOSI8

VCC_OUT0_1

9

VCC_OUT0_2

12

VCC_OUT1_1

13

VCC_OUT1_2

16

SPI_CLK17 SPI_LE18

TESTSYNC19

GND_PLLDIV21

VCC_PLLDIV

22

VCC_VCO

24

EXT_LFP25

EXT_LFN26

VCC_PLLA

28

REF+29

REF-30

VCC_IN

31

PLL_LOCK32

EPAD33

U0N10U0P11

U1N14U1P15

REG_CAP15

REG_CAP227

REG_CAP320

REG_CAP423

Thermal_VIA134

Thermal_VIA235

Thermal_VIA336

Thermal_VIA437

Thermal_VIA538

Thermal_VIA639

Thermal_VIA740

Thermal_VIA841

Thermal_VIA942

C301 10uF 6.3V

C271uF6.3V

C540.1uF16V

C470.1uF16V

Rework 100

C51 0.1uF 16V

C440.1uF16V

C46 0.1uF 16V

C320.1uF16V

B22200pF0.7A

1

2

3

C410.1uF16V

B52200pF0.7A

1

2

3

C61 1uF 6.3V

C310.1uF16V

C313 10uF 6.3V

B12200pF0.7A

1

2

3

C620.1uF16V

C303 10uF 6.3V

C490.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK GEN2

312.5MHz Output

312.5MHz Output

156.25MHz Output

25MHz Output

REFCLK2_XTALIN

VCC3V3_AUX

VCC3V3_AUX

VCCPLLA2A

VCC3V3_AUX VCC_VCO2A

VCCPLLA2A

VCC3V3_AUX VCC_VCO2B

VCC3V3_AUX

VCC_VCO2A

VCC3V3_AUX

VCCPLLA2B

VCC_VCO2B

VCCPLLA2C

VCCPLLA2B

VCCPLLA2CVCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

INREFCLK2_PD#(32)

INCLOCK2_SSPCS1(32)INCLOCK2_SSPCK(32)INCLOCK2_SSPSI(32)OUTCLOCK2_SSPSO(32)

OUT PCIECLKP (18)OUT PCIECLKN (18)

OUT MCMCLKP (18)OUT MCMCLKN (18)

OUT SRIOSGMIICLKP (18)OUT SRIOSGMIICLKN (18)


OUT REFCK_P (22)OUT REFCK_N (22)

INTCLKB_P(11,31)INTCLKB_N(11,31)

INCLK2_SYNC(30)

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN2

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN2

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN2

C


DSPM-8303E

C191 1uF 6.3V

B212200pF0.7A

1

2

3

C231 0.1uF 16V

TP47

R304 10K

C5600.1uF16V

C5570.1uF16V

C5480.1uF16V

B262200pF0.7A

1

2

3

C5350.1uF16V

C2160.1uF16V

C1841uF6.3V

C2061uF6.3V

C205 1uF 6.3V

C5430.1uF16V

C1590.1uF16V

R301 1K

B322200pF0.7A

1

2

3

C5250.1uF16V

TP44

CLK2

TI_CDCE62005RGZT

AUXIN43AUXOUT13

EPAD

49

EXT_LFN41 EXT_LFP40

GND_VCO

36

PLL_LOCK37

Power_Down12

PRIREF-46 PRIREF+45

REF_SEL31

REG_CAP14

REG_CAP238

SECREF-2 SECREF+3

SPI_CLK24 SPI_LE25

SPI_MISO22 SPI_MOSI23

SYNC14

TEST_MODE33

TESTOUTA30

Thermal_VIA1

50

Thermal_VIA2

51

Thermal_VIA20

69

Thermal_VIA21

70

Thermal_VIA22

71

U0N28U0P27

U1N20U1P19

U2N17U2P16

U3N10U3P9

U4N7U4P6

VBB

48

VCC_AUXIN

44

VCC_AUXOUT

15

VCC_IN_PRI

47

VCC_IN_SEC

1

VCC_OUT1

8

VCC_OUT2

11

VCC_OUT3

18

VCC_OUT4

21

VCC_OUT5

26

VCC_OUT6

29

VCC_OUT7

32

VCC_VCO1

34

VCC_VCO2

35

VCC1_PLL1

5

VCC1_PLL2

39

VCC1_PLL3

42

Thermal_VIA10

59

Thermal_VIA11

60

Thermal_VIA12

61

Thermal_VIA13

62

Thermal_VIA14

63

Thermal_VIA15

64

Thermal_VIA16

65

Thermal_VIA17

66

Thermal_VIA18

67

Thermal_VIA19

68

Thermal_VIA3

52

Thermal_VIA4

53

Thermal_VIA5

54

Thermal_VIA6

55

Thermal_VIA7

56

Thermal_VIA8

57

Thermal_VIA9

58

Thermal_VIA23

72

Thermal_VIA24

73

Thermal_VIA25

74

Y5 25MHz_20pF

C1960.1uF16VC204 1uF

6.3V

C2081uF6.3V

TP45

C1420.1uF16V

C211 NL/47pF50V

B332200pF0.7A

1

2

3

TP13

C5560.1uF16V

C1470.1uF16V

C1981uF6.3V

C5400.1uF16V

C2170.1uF16V

TP46

R303 NL/10K

C230 0.1uF 16V

B272200pF0.7A

1

2

3

C1430.1uF16V

R297 10K

C5370.1uF16V

C1881uF6.3V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK GEN3

122.88MHz Output

122.88MHz Output

122.88MHz Output

30.72MHz Output

REFCLK3_XTALIN

BUFFER_CLK_R

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCCPLLA3A

VCC3V3_AUX VCC_VCO3A

VCCPLLA3A

VCC3V3_AUX VCC_VCO3B

VCC3V3_AUX

VCC_VCO3A

VCC3V3_AUX

VCCPLLA3B

VCC_VCO3B

VCCPLLA3C

VCCPLLA3B

VCCPLLA3CVCC3V3_AUX

VCC3V3_AUX

OUTCLOCK3_SSPSO(32)

INCLOCK3_SSPCK(32)INCLOCK3_SSPSI(32)

INCLOCK3_SSPCS1(32)

OUT CORECLKP (18)OUT CORECLKN (18)

OUT PASSCLKP (18)OUT PASSCLKN (18)

OUT RP1CLKP (18)OUT RP1CLKN (18)

OUT SYSCLKP (18)OUT SYSCLKN (18)


INBUFFER_CLK(27)

INTCLKD_P(11,31)INTCLKD_N(11,31)

INREFCLK3_PD#(32)

INCLK3_SYNC(30)

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

CLOCK GEN3

C


DSPM-8303E

C5220.1uF16V

C5140.1uF16V

C5391uF6.3V

C1800.1uF16V

CLK3

TI_CDCE62005RGZT

AUXIN43AUXOUT13

EPAD

49

EXT_LFN41 EXT_LFP40

GND_VCO

36

PLL_LOCK37

Power_Down12

PRIREF-46 PRIREF+45

REF_SEL31

REG_CAP14

REG_CAP238

SECREF-2 SECREF+3

SPI_CLK24 SPI_LE25

SPI_MISO22 SPI_MOSI23

SYNC14

TEST_MODE33

TESTOUTA30

Thermal_VIA1

50

Thermal_VIA2

51

Thermal_VIA20

69

Thermal_VIA21

70

Thermal_VIA22

71

U0N28U0P27

U1N20U1P19

U2N17U2P16

U3N10U3P9

U4N7U4P6

VBB

48

VCC_AUXIN

44

VCC_AUXOUT

15

VCC_IN_PRI

47

VCC_IN_SEC

1

VCC_OUT1

8

VCC_OUT2

11

VCC_OUT3

18

VCC_OUT4

21

VCC_OUT5

26

VCC_OUT6

29

VCC_OUT7

32

VCC_VCO1

34

VCC_VCO2

35

VCC1_PLL1

5

VCC1_PLL2

39

VCC1_PLL3

42

Thermal_VIA10

59

Thermal_VIA11

60

Thermal_VIA12

61

Thermal_VIA13

62

Thermal_VIA14

63

Thermal_VIA15

64

Thermal_VIA16

65

Thermal_VIA17

66

Thermal_VIA18

67

Thermal_VIA19

68

Thermal_VIA3

52

Thermal_VIA4

53

Thermal_VIA5

54

Thermal_VIA6

55

Thermal_VIA7

56

Thermal_VIA8

57

Thermal_VIA9

58

Thermal_VIA23

72

Thermal_VIA24

73

Thermal_VIA25

74

Y4 30.72MHz_20pF1 3

42

R298 1K

C1810.1uF16V

C212 1uF 6.3V

C5320.1uF16V

C2130.1uF16V

C1570.1uF16V

B292200pF0.7A

1

2

3

C5681uF6.3V

C5360.1uF16VC200 1uF

6.3V

C5150.1uF16V

B282200pF0.7A

1

2

3

C2141uF6.3V

R302 NL/10K

C5550.1uF16V

TP48

C229 0.1uF 16V

B202200pF0.7A

1

2

3

C1971uF6.3V

TP49

C2100.1uF16V

C5661uF6.3V

B302200pF0.7A

1

2

3

C5670.1uF16V

R317 0

R305 10K

C5490.1uF16V

C228 0.1uF 16V

C5650.1uF16V

C1920.1uF16V

B312200pF0.7A

1

2

3

C547 1uF 6.3V

R292 10K

C5160.1uF16V

TP12

C209 NL/47pF50V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Trace need 20 mil.

* Data bits can be swapped within

the byte lane to ease routing.

* Address/Command/Control/Clock

routing must be Fly-By in byte order

0, 1, 2, 3 ECC, 4, 5, 6, 7.

Trace need 20 mil.

Trace need 20 mil. Trace need 20 mil.

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12

DSP0_DDR3_EDQ15

DSP0_DDR3_EDQ8DSP0_DDR3_EDQ9DSP0_DDR3_EDQ10DSP0_DDR3_EDQ11DSP0_DDR3_EDQ12DSP0_DDR3_EDQ13DSP0_DDR3_EDQ14

DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6

DSP0_DDR3_EDQ30DSP0_DDR3_EDQ31

DSP0_DDR3_EDQ24DSP0_DDR3_EDQ25DSP0_DDR3_EDQ26DSP0_DDR3_EDQ27DSP0_DDR3_EDQ28DSP0_DDR3_EDQ29





DSP0_DDR3_EDQ47

DSP0_DDR3_EDQ40DSP0_DDR3_EDQ41DSP0_DDR3_EDQ42DSP0_DDR3_EDQ43DSP0_DDR3_EDQ44DSP0_DDR3_EDQ45DSP0_DDR3_EDQ46

DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6






DSP0_DDR3_EA14

DSP0_DDR3_EBA_0DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2

DSP0_DDR3_EWE#DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#

DSP0_DDR3_EDQSP_1DSP0_DDR3_EDQSN_1


DSP0_DDR3_EDM_0DSP0_DDR3_EDM_1

DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0DSP0_DDR3_ECKE_0

DSP0_DDR3_EODT_0

DSP0_DDR3_EMRESETN







DSP0_DDR3_EODT_0

DSP0_DDR3_EMRESETN



DSP0_DDR3_EDQSP_2DSP0_DDR3_EDQSN_2DSP0_DDR3_EDQSP_3DSP0_DDR3_EDQSN_3


DSP0_DDR3_ECKE_0

DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0

DSP0_DDR3_EODT_0

DSP0_DDR3_EMRESETN DSP0_DDR3_EMRESETN

DSP0_DDR3_EODT_0



DSP0_DDR3_EDQSP_6DSP0_DDR3_EDQSN_6DSP0_DDR3_EDQSP_7DSP0_DDR3_EDQSN_7



DSP0_DDR3_EA15

DSP0_DDR3_EA15 DSP0_DDR3_EA15

DSP0_DDR3_EA14DSP0_DDR3_EA15

DSP0_DDR3_EA14 DSP0_DDR3_EA14

DSP0_DDR3_EA13

DSP0_DDR3_EA13

DSP0_DDR3_EA13

DSP0_DDR3_EA13

VCC1V5

VCC1V5

VCC1V5

VCC1V5

VCC_VREFSSTL VCC_VREFSSTL

VCC_VREFSSTL VCC_VREFSSTL

INDSP0_DDR3_EA[0..15](14,25,26)

BI DSP0_DDR3_EDQ[8..15] (14)

INDSP0_DDR3_EA[0..15](14,25,26)

BI DSP0_DDR3_EDQ[24..31] (14)

BI DSP0_DDR3_EDQ[0..7] (14)

BI DSP0_DDR3_EDQ[16..23] (14)

INDSP0_DDR3_EA[0..15](14,25,26)

BI DSP0_DDR3_EDQ[40..47] (14)

INDSP0_DDR3_EA[0..15](14,25,26)

BI DSP0_DDR3_EDQ[56..63] (14)

BI DSP0_DDR3_EDQ[32..39] (14)

BI DSP0_DDR3_EDQ[48..55] (14)

INDSP0_DDR3_EA[0..15](14,25,26)

INDSP0_DDR3_EA[0..15](14,25,26)INDSP0_DDR3_EA[0..15](14,25,26)

INDSP0_DDR3_EBA_0(14,25,26)INDSP0_DDR3_EBA_1(14,25,26)INDSP0_DDR3_EBA_2(14,25,26)

INDSP0_DDR3_EWE#(14,25,26)INDSP0_DDR3_ECAS#(14,25,26)INDSP0_DDR3_ERAS#(14,25,26)INDSP0_DDR3_ECS_0#(14,25,26)

INDSP0_DDR3_EDQSP_1(14)INDSP0_DDR3_EDQSN_1(14)


INDSP0_DDR3_EDM_1(14)INDSP0_DDR3_EDM_0(14)

INDSP0_DDR3_ECKP_0(14,25,26)INDSP0_DDR3_ECKN_0(14,25,26)INDSP0_DDR3_ECKE_0(14,25,26)

INDSP0_DDR3_EODT_0(14,25,26)

INDSP0_DDR3_EMRESETN(14,25,26)


INDSP0_DDR3_EWE#(14,25,26)INDSP0_DDR3_ECAS#(14,25,26)INDSP0_DDR3_ERAS#(14,25,26)INDSP0_DDR3_ECS_0#(14,25,26)






INDSP0_DDR3_EMRESETN(14,25,26)


INDSP0_DDR3_ERAS#(14,25,26)INDSP0_DDR3_ECS_0#(14,25,26)

INDSP0_DDR3_EWE#(14,25,26)INDSP0_DDR3_ECAS#(14,25,26)

INDSP0_DDR3_EDQSP_2(14)INDSP0_DDR3_EDQSN_2(14)INDSP0_DDR3_EDQSP_3(14)INDSP0_DDR3_EDQSN_3(14)


INDSP0_DDR3_ECKE_0(14,25,26)

INDSP0_DDR3_ECKP_0(14,25,26)INDSP0_DDR3_ECKN_0(14,25,26)


INDSP0_DDR3_EMRESETN(14,25,26) INDSP0_DDR3_EMRESETN(14,25,26)




INDSP0_DDR3_EDQSP_6(14)INDSP0_DDR3_EDQSN_6(14)INDSP0_DDR3_EDQSP_7(14)INDSP0_DDR3_EDQSN_7(14)

INDSP0_DDR3_ERAS#(14,25,26)INDSP0_DDR3_ECS_0#(14,25,26)

INDSP0_DDR3_EWE#(14,25,26)INDSP0_DDR3_ECAS#(14,25,26)


INDSP0_DDR3_EA[0..15](14,25,26)

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3

C


DSPM-8303E

C2870.1uF16V

C2610.1uF16V

C2560.1uF16V

C25022uF6.3V

C24422uF6.3V

C2850.1uF16V

U3

<Characteristic>SAMSUNG_K4B2G1646C-HCK0

VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C2670.1uF16V

U5


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C2860.1uF16V

C264

0.1uF

16V

C2790.1uF16V

R3 240 1%

C254

0.1uF

16V

C24722uF6.3V

R6 240 1%

C2720.1uF16V

C2740.1uF16V

C266

0.1uF

16V

C2700.1uF16V

C2590.1uF16V

R5 240 1%

C2022uF6.3V

U6


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C2770.1uF16V

R2 240 1%

C2830.1uF16V

C2630.1uF16V

C262

0.1uF

16V

C2840.1uF16V

C2730.1uF16V

U2


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C2750.1uF16V

C2800.1uF16V

C2710.1uF16V

C2810.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Trace need 10 mil.

FOR ECC USE


DSP0_DDR3_EA15


DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#

DSP0_DDR3_EWE#


DSP0_DDR3_EDM_8

DSP0_DDR3_EODT_0

ECC_ZQ

DSP0_DDR3_EMRESETN


DSP0_DDR3_ECC2DSP0_DDR3_ECC3




ECC_NU

DSP0_DDR3_EA14

DSP0_DDR3_EA13

VCC1V5

VCC1V5

VCC_VREFSSTL

INDSP0_DDR3_EA[0..15](14,25,26)

INDSP0_DDR3_EBA_0(14,25)INDSP0_DDR3_EBA_1(14,25)INDSP0_DDR3_EBA_2(14,25)

INDSP0_DDR3_ECAS#(14,25)INDSP0_DDR3_ERAS#(14,25)INDSP0_DDR3_ECS_0#(14,25)

INDSP0_DDR3_EWE#(14,25)


INDSP0_DDR3_EDM_8(14)

INDSP0_DDR3_EODT_0(14,25)

INDSP0_DDR3_EMRESETN(14,25)

INDSP0_DDR3_ECKP_0(14,25)INDSP0_DDR3_ECKN_0(14,25)INDSP0_DDR3_ECKE_0(14,25)

BI DSP0_DDR3_ECC[0..7] (14)

INDSP0_DDR3_EA[0..15](14,25,26)

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3_ECC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3_ECC

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

DDR3_ECC

C


DSPM-8303E

R367 4.7K

R4 240 1%

C2820.1uF16V

U4


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C2690.1uF16V

R351 4.7K

R356 4.7K

C260

0.1uF

16V

R358 4.7K

R359 4.7K

R352 4.7K

C2680.1uF16V

R364 4.7K

C2570.1uF16V

R366 4.7KR353 4.7K

R363 4.7K

C24522uF6.3V

C2780.1uF16V

R349 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SIM_SEL

High Low (Default)

VCC_SIM Value = 1.8VVCC_SIM Value = 2.95V

USIM GPS

NOTE:Do not set a jumper! GPS PPS output

FOR ANTENA CIRCUIRFOR PPS SELECT

TCVCXO (OSC1) footprint issue.

A101-1

SIM_CLK

SIM_RST

SIM_SELSIM_EN

SIM_IO

SIM_VCC

GPS_RF

GPS_RTC_CLK

DAC_SSPCK_3.3VDSP_SSPMOSI_3.3V

DAC_SSPCS2_3.3V

GPS_UARTRXD_R

GPS_RF

SIM_RST

SIM_CLKSIM_IO

DAC_SSPCK_3.3VDSP_SSPMOSI_3.3V

DAC_SSPCS2_3.3VGPS_PPS

SIM_EN

GPS_RTC_CLK

SIM_SEL

SIM_VCC

VCC3V3_AUX

VCC1V8

VCC1V8

DAC_VOUT

VCC3V3_AUX

VCC3V3_AUXVCC1V8

VCC3V3_AUX

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

DAC_VOUT

VCC3V3_AUX

VCC3V3_AUX

VCC5

BIDSP_SIM_IO(16)INDSP_SIM_RST(16)INDSP_SIM CLK(16)

OUTDSP_TIMI0(16,30,32)

INDSP_SSPMOSI(16,30,31)INDAC_SSPCK(16)INDAC_SSPCS2(16) INGPS_UARTTXD(16)

OUTGPS_UARTRXD(16)

OUT BUFFER_CLK (24)

IN DAC_CLR# (32)IN DAC_LD# (32)

OUT BUFCLK_FPGA (32)

IN DSP_TIMO0 (16,30,31)

IN FPGA_FSYNC (31)

OUT PHYSYNC (11,16)

OUTFPGA_TIMI0(31)

OUTRADSYNC(11,16)

Title


Date: Sheet of


TMS320TCI6614 A101

GPS & SIM CARD

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

GPS & SIM CARD

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

GPS & SIM CARD

C


DSPM-8303E

L8

0.082uH

0.3A

R310 0


OSC1

19.2MHz_15pF3.3V

Vs4

OUT3

GND2

Vc1

TP16

OSC2

<Characteristic>32.768KHz

VCC4

OUT3

GND2

OE1

U20

TI_SN74AVC4T245PWR

VCCA1

1DIR2

2DIR3

1A14

1A25

2A16

2A27

GND18


TP41TP15

B252200pF0.7A

1

2

3

TP18

TP42

CN2

RF_5H

GND_12

GND_23 R

F_IN

1

GND_34

GND_45

R299 22

R291 22

C491 1uF6.3V

R312 10K

L93.6nH0.3A

C5210.1uF16V

C1940.1uF16V

U22

<Characteristic>TI_CDCLVC1104PW

CLKIN1

1G2

Y03

GND4

Y25VDD6Y37Y18

C1480.1uF16VR296

NL/10K

CN1

PH_3x2V_2.54mm

135

246

C1240.1uF16V

C225NL/1.5pF50V


C1730.1uF16V

B422200pF0.7A

1

2

3 R293 22

C1821uF6.3V

PowerManagement

Clock

GPS

BT

FM

Shared UART

GPS-/FM-/BT-Module

GPS1

GNS_TC6000G

VDDE1

VDD_IOF1

GPS_ENABLEC4

BT_ENABLEF5

GND_2F2 GND_1E2

TCXO_CLKC2

RTC_CLKC5

GPS_RFB1

GPS_TXC3

GPS_RXB3

GPS_PPSC1

GPS_GND_1A1

GPS_GND_2A2

GPS_GND_3B2

BT_RFF6

BT_AUD_CLKD1

BT_AUD_FSYNCD2

BT_AUD_IND3

BT_AUD_OUTD4

GND_BTE6

FM_TX_RFA5

FM_RX_RFA6

FM_AUD_R_OUTA3

FM_AUD_L_OUTA4

FM_I2S_FSYNCB6

FM_I2S_INC6

FM_I2S_CLKD6

GND_FMB4

GND_FMB5

RXE4

TXF3

RTSE5

CTSE3

NC2F4 NC1D5

C53310uF6.3V

L7 27nH 0.3A


C1391uF6.3V

R524

1K

R295

1K

C5450.1uF16V

C2181.5pF50V

C2071000pF50V

C5240.1uF16V

C1600.1uF16V

C519

0.1uF16V

R551 10

DAC1

TI_DAC7611UB

VDD1

CS2

CLK3

SDI4

LD5CLR6GND7VOUT8

C1271uF6.3V

B412200pF0.7A

1

2

3

C5110.1uF16V

CN3

PH_3x1V_2.54mm

123

R300 22R29410K

C1830.1uF16V

C1380.1uF16V

R52810K

C575100pF50V

C1290.1uF16V

SMDFIX

SIM CARD

SMDFIX

SIM1

SIM_8H

SW2SW1C7C3C6C2C5C1

H2

H1

ExposedThermal Pad

U19

<Characteristic>TI_TXS4555RGTR

EN1

SEL2

VCC3

NC14

VBATT

5

NC2

6

VSIM

7

SIM_I/O

8

SIM_RST9GND10SIM_CLK11NC312

CLK

13

RST

14

I/O

15

NC4

16

EPAD

17

R555 10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

001

000

111

110

100

011

Bit[1] Bit[0]

PHYADR[1]PHYADR[4]ANEG[2]ENA_XCHWCFG_MODE[1]DIS_SLEEPINT_POL

PHYADR[0]PHYADR[3]ANEG[1]DIS_125HWCFG_MODE[0]HWCFG_MODE[3]75/50 OHM

88E1111 Device Pin to Configuration Bit Mapping

Pin

CONFIG0CONFIG1CONFIG2CONFIG3CONFIG4CONFIG5CONFIG6

PHYADR[2]ENA_PAUSEANEG[3]ANEG[0]HWCFG_MODE[2]DIS_FCSEL_TWSI

Bit[2]

Pin to Constant Mapping

Pin Bit[2:0]

VDDOLED_LINK10LED_LINK100LED_LINK1000LED_DUPLEXLED_RXLED_TXVSS

111110101100011010001000

PHY ConfigurationHardwareConfigurationBit Setting

PHY Address bit[2:0] 001

Enable Pause ,PHY Address bit[4:3] = 00

Auto-Neg advertise all capabilities ,prefer Master

CONFIG Pin Connection

Enable MDI crossover, disable 125CLK

Pin

CONFIG0CONFIG1CONFIG2CONFIG3CONFIG4CONFIG5CONFIG6

001100111011

SGMII without Clock with SGMII Auto-Neg to copper

Disable fiber /copper Auto-detect, Disable sleep

Select MDIO interface, INT signal active high, 50 ohm SERDES

LED PinConnection

PHY Address = 0x01

100110000

LED_TXLED_LINK1000VDDOLED_DUPLEX

LED_LINK1000LED_LINK10VSS

100

1

MDI0_NMDI0_PMDI1_NMDI1_PMDI2_NMDI2_PMDI3_NMDI3_P

TXD6

TXD0TXD1TXD2TXD3TXD4TXD5

TXD7

TX_ER

GTX_CLK

TX_ENTX_CLK

P1_RSET

PHY_RST#

PHY_P1_XTAL2

PHY_P1_XTAL1_R PHY_P1_XTAL1

R_P1_LAN_RST#

PHY_P1_XTAL1PHY_P1_XTAL2

P1_COL_PD

LED_LINK1000LED_LINK100

DSP_SGMII_TXP_CDSP_SGMII_TXN_C

DSP_SGMII_TXPDSP_SGMII_TXN

DSP_SGMII_RXPDSP_SGMII_RXN

P1_CONFIG1P1_CONFIG2P1_CONFIG3P1_CONFIG4

P1_CONFIG0

P1_CONFIG5P1_CONFIG6P1_CLKSEL

LED_LINK1000

LED_LINK10

P1_CONFIG0

P1_CONFIG2

P1_CONFIG5

P1_CONFIG1

P1_CONFIG4

P1_CONFIG6

P1_CONFIG3 LED_DUPLEX

LED_TX

P1_CLKSEL

LED_DUPLEX

LED_LINK10

LED_TXLED_RX

PHY_RST#

FPGA_JTAG_TDO BSC_JTAG_TDI

VCC1V2VCC2V5 AVCC2V5

VCC2V5AVCC2V5

VCC1V2

VCC2V5

VCC2V5

VCC2V5

IN PHY_RST# (31)

INDSP_MDC_1(13)BIDSP_MDIO_1(13)

OUT LED_LINK1000 (29)OUT LED_LINK100 (29)

IN DSP_SGMII_TXP (13)

IN DSP_SGMII_TXN (13)

OUT DSP_SGMII_RXN (13)OUT DSP_SGMII_RXP (13)

INPHY_INT#(31)

BI MDI3_P (29)

BI MDI3_N (29)

BI MDI2_P (29)

BI MDI2_N (29)

BI MDI1_P (29)

BI MDI1_N (29)

BI MDI0_P (29)

BI MDI0_N (29)

OUT LED_RX (29)

IN BSC_PHY_TCK (33)

IN FPGA_JTAG_TDO (33)IN BSC_JTAG_TMS (33)

IN BSC_JTAG_RST# (33)OUT BSC_JTAG_TDI (33)

Title


Date: Sheet of


TMS320TCI6614 A101

Gigabit Ethernet PHY

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

R140 0

5%

R145 0

R67 4.7K

R144 0

C3390.1uF16V

C3000.01uF16V

R77 4.99K 1%

R159 0

C3160.1uF16V

R139 NL/22

R109 4.99K 1%

R380 4.7K

C3050.1uF16V

R160 0

C3174.7uF6.3V

R122 NL/0

R377 NL/4.7K

C424.7uF6.3V

R54 4.7K

C3080.01uF16V

C2994.7uF6.3V

R60 0

C3024.7uF6.3V

C3154.7uF6.3V

R378 4.7K

R53 4.7K

Y125MHz_20pF

C3400.1uF16V

R98 4.99K 1%

R100 4.7K

R80 4.7K

R79 4.7K

R379 4.7K

C45 0.1uF 16V

R524.99K1%

R66 4.7K

88E1111-BAB

PHY1

MARVELL_88E1111-B2-BAB1C000

DVDD_6

F3

RXD0B2

RX_DVB1

VDDO_1

B4

DVDD_5

E7

RX_CLKC1

RX_ERD2

TX_CLKD1

VDDO_2

C2

DVDD_4

E3

TX_ERF2

GTX_CLKE2

TX_ENE1

DVDD_3

D7

TXD0F1

TXD1G2

TXD2G3

DVDD_2

C7

TXD3H2

TXD4H1

TXD5H3

DVDD_1

C6

TXD6J1

TXD7J2

VDDO_3

K1

125CLKK2

INTL1 MDIOM1

VDDOX_2

L2

MDCL3

RESETK3

COMAL4

RSETM2

MDI0+N1

MDI0-N2

AVDD_6

B7

MDI1+N3

MDI1-N4

AVDD_5

N5

NC_1G1

AVDD_4

M8

HSDAC+M5

HSDAC-M6

MDI2+N6

MDI2-N7

AVDD_3

M7

MDI3+N8

MDI3-N9

AVDD_2

M4

VSS_1

D4

TDIL7

TRSTM9

TMSL8

TCKL9

VDDOX_1

K9

TDOK8

VDDOH_2

F7

VSSC

H7

XTAL2J9XTAL1H9

SEL_FREQH8 CONFIG6G8 CONFIG5G9 CONFIG4F9 CONFIG3G7 CONFIG2F8 CONFIG1E9 CONFIG0D8

VDDOH_3

J8

LED_TXD9LED_RXC9LED_DUPLEXE8

VDDOH_1

B9

LED_LINK1000A9LED_LINK100B8LED_LINK10C8

AVDD_1

M3

S_OUT-A8S_OUT+A7

S_CLK-A6S_CLK+A5

S_IN-A4S_IN+A3

COLB6 CRSB5

DVDD_8

J7

DVDD_7

J3

RXD7C5 RXD6A2 RXD5A1 RXD4C4 RXD3B3 RXD2C3 RXD1D3

VSS_2

G6

VSS_3

J5

VSS_4

J6

VSS_5

K4

VSS_6

K5

VSS_7

K6

VSS_8

L5

VSS_9

L6

VSS_10

D5

VSS_11

D6

VSS_12

E4

VSS_13

E5

VSS_14

E6

VSS_15

F4

VSS_16

F5

VSS_17

F6

VSS_18

G4

VSS_19

G5

VSS_20

H4

VSS_21

H5

VSS_22

H6

VSS_23

J4

NC_2K7

R152 0

R143 0

TP1

C48 0.1uF 16V

C7727pF50V

R78 4.7K

R407 10K

C3070.1uF16V

R404 0

B34120_100MHz

0.5A

R376 10K

R65 4.7K

C7627pF50V

R406 NL/10K

C3060.01uF16V

R405 0

C3120.01uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FOR EMI

Heatsink Holes

RJ-45

On board

(Bottom Side 3mm) Placed Capacitors

AMC Hole

LED_LINK1000

MDI0_N

MDI1_N

MDI0_P

MDI3_P

MDI2_N

P1_RC_P01

P1_RC_P02

P1_RC_P00

MDI2_P

MDI1_P

P1_RC_P03

MDI3_N

LED_LINK100

LAN_ACTLED_RX

VCC2V5

VCC2V5

P1_TCT

VCC2V5

P1_TCT

P1_TCT

P1_TCT

P1_TCT

GND_LAN

GND_LAN

INLED_LINK100(28)INLED_LINK1000(28)

BIMDI3_P(28)

BIMDI3_N(28)

BIMDI2_P(28)

BIMDI2_N(28)

BIMDI1_P(28)

BIMDI1_N(28)

BIMDI0_P(28)

BIMDI0_N(28)

INLED_RX(28)

Title


Date: Sheet of


TMS320TCI6614 A101

RJ45

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

RJ45

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

RJ45

C


DSPM-8303E

C260.1uF16V

H5

H35-NPTH

1

R3649.91%

BRK1

<Characteristic>SOCKET900_ CSBGA900

H1 H2

H3 H4

H5 H6

H7 H8

H9

H10

C390.1uF16V

R5549.91%

C240.1uF16V

H4

H35-NPTH

1

G

SHIELD GND

1000pF 2kV

75RO

4

7

6

2

8

3

1

5

TX1-

TX2-

TX2+

TX1+

TX3+

TX3-

TX4+

TX4-

G

LAN1

RJ45_W/XFMR&LED

14

13

1

2

3

4

5

6

7

8

9

10

11

12

15

16

17 H3H4

H1H2

R3349.91%

H2

H35-NPTH

1

C60.1uF16V

R4349.91%

C2760.1uF16V

C290 470pF50V

B4120_100MHz

0.5A

H1

H27P35-MTH

1

R5149.91%

R3049.91%

R345 100

C2910.1uF16V

R72 0

R365 100

C2880.1uF16V

FM2

Fiducial

FM1

Fiducial

R4949.91%

C2580.1uF16V

FM4

Fiducial

C80.1uF16V

R344 100

FM3

Fiducial

R2449.91%

H3

H35-NPTH

1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

100-pin Expansion Header

IPASS+HD for HyperLink Bus connection

the interfaces on the 100-pin header are all

1.8V LVCMOS except for the UART which is

3.3V LVCMOS

GPIO

SPI

SOC_UART(3.3V)UART

EMIF

I2C

EMIF

EMIF

TIMI

CLK SYNC

HyperLink_TXFLDATHyperLink_RXPMDAT

HyperLink_RXFLDATHyperLink_RXPMCLK

HyperLink_TXP0HyperLink_TXN0


HyperLink_RXN2HyperLink_RXP2

HyperLink_RXP0HyperLink_RXN0

HyperLink_TXFLCLKHyperLink_RXFLCLK

HyperLink_TXPMCLKHyperLink_TXPMDAT


HyperLink_TXN1HyperLink_TXP1

HyperLink_RXP3HyperLink_RXN3

HyperLink_RXN1HyperLink_RXP1

DSP_SSPMISO_R

CLK2_SYNCCLK3_SYNC

CLK2_SYNCCLK3_SYNC

VCC3V3_AUX

OUTHyperLink_TXFLDAT(13)OUTHyperLink_RXPMDAT(13)

OUTHyperLink_RXPMCLK(13)INHyperLink_RXFLDAT(13)

INHyperLink_TXP2(13)INHyperLink_TXN2(13)

INHyperLink_TXP0(13)INHyperLink_TXN0(13)

OUTHyperLink_RXP0(13)OUTHyperLink_RXN0(13)

OUTHyperLink_RXP2(13)OUTHyperLink_RXN2(13)

IN HyperLink_RXFLCLK (13)OUT HyperLink_TXFLCLK (13)

IN HyperLink_TXPMDAT (13)IN HyperLink_TXPMCLK (13)

IN HyperLink_TXP3 (13)IN HyperLink_TXN3 (13)

IN HyperLink_TXP1 (13)IN HyperLink_TXN1 (13)

OUT HyperLink_RXP3 (13)OUT HyperLink_RXN3 (13)

OUT HyperLink_RXP1 (13)OUT HyperLink_RXN1 (13)

INDSP_GPIO_00(16,32)
















IN PH_SSPCK (16)

IN DSP_SSPMOSI (16,27,31)OUT DSP_SSPMISO (16,31)

IN MISC_SSPCS3 (16)

IN DSP_UARTRTS (16)OUT DSP_UARTRXD (16)

IN DSP_UARTTXD (16)

OUT DSP_UARTCTS (16)

BI DSP_EMIFD1 (15)

BI DSP_EMIFD2 (15)

BI DSP_EMIFD3 (15)

BI DSP_EMIFD0 (15)

BI DSP_SDA (16)

IN DSP_SCL (16)

INDSP_EMIFA06(15)INDSP_EMIFA05(15)

INDSP_EMIFA07(15)INDSP_EMIFA08(15)INDSP_EMIFA09(15)

INDSP_EMIFA21(15)


INDSP_EMIFA00(15)INDSP_EMIFA01(15)INDSP_EMIFA02(15)


IN DSP_EMIFOEZ (15)IN DSP_EMIFWEZ (15)IN DSP_EMIFRNW (15)

IN DSP_EMIFBE0Z (15)IN DSP_EMIFBE1Z (15)

OUT DSP_EMIFWAIT1 (15)

IN DSP_GPIO_16 (16,32)IN DSP_EMIFCE1Z (15)

BI DSP_EMIFD12 (15)

BI DSP_EMIFD13 (15)

BI DSP_EMIFD14 (15)

BI DSP_EMIFD15 (15)

BI DSP_EMIFD8 (15)

BI DSP_EMIFD9 (15)

BI DSP_EMIFD10 (15)

BI DSP_EMIFD4 (15)

BI DSP_EMIFD5 (15)

BI DSP_EMIFD6 (15)

BI DSP_EMIFD7 (15)

BI DSP_EMIFD11 (15)

INDSP_EMIFA10(15)



INDSP_EMIFA15(15)INDSP_EMIFA16(15)INDSP_EMIFA17(15)INDSP_EMIFA18(15)

INDSP_EMIFA20(15)

INDSP_EMIFA19(15)

OUT DSP_TIMI1 (16,32)IN DSP_TIMO1 (16,31)

IN DSP_TIMO0 (16,27,31)OUT DSP_TIMI0 (16,27,32)

OUTCLK2_SYNC(23)OUTCLK3_SYNC(24)

Title


Date: Sheet of


TMS320TCI6614 A101

Connectors for HyperLink & Debug

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303ER59610K

iPass Plus HD 1x1 Assy

HYPERLINK1

IPASS+HD_36H

sideband5D1

sideband6D2

GND_D3D3

Txp0D4

Txn0D5

GND_D6D6

Txp2D7

Txn2D8

GND_D9D9

sideband3B1

sideband1B2

GND_B3B3

Rxp0B4

Rxn0B5

GND_B6B6

Rxp2B7

Rxn2B8

GND_B9B9

sideband4C1

sideband2C2

GND_C3C3

Txp1C4

Txn1C5

GND_C6C6

Txp3C7

Txn3C8

GND_C9C9

sideband7A1

sideband0A2

GND_A3A3

Rxp1A4

Rxn1A5

GND_A6A6

Rxp3A7

Rxn3A8

GND_A9A9

NPTH1

H1

NPTH2

H2

R334 10

TEST_PH1

BH_50x2H_S1.27mm

1234567891011121314151617181920212223242526272829303132333435363738394041424344

464850 49

4547

51525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100

101

102

R59510K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

High activePUDC:User I/O Pull-Up Control. WhenLow during configuration, enablespull-up resistors in all I/O pins torespective I/O bank VCCO input.0: Pull-ups during configuration1: No pull-ups

SOC

MMC

SOC SPI

POWER SEQUENCE

Switches RESET

SOC RESETS

WARM_RESET FULL_RESET

POWER UCD9222

SOC

EEPROMNOR FLASH

60 PIN Header

MMC

PHY 88E1111

AMC TCLOCK

Place near to FPGA

PCIE CLOCK CONTROL

PCIE CLOCK CONTROLPCIE CLOCK CONTROL

POWER SEQUENCE

PHY 88E1111

A101

BID1 BID0

00

BOARD ID

TCLKC_P : output for DSP_TIMI1TCLKC_N : intput for DSP_TIMO1

TCLKCp/n alsp servers as the DSP_TIMI1

and DSP_TIMO1 and 3.3V I/O respectively

NOTE

PPS INTERRUPT

FPGA FSYNC

SOC TIMER

SFP CONTROL

TCLKC_[N/P]

FPGA_PUDC

SYS_PGOOD

MMC_DETECT#_R

FPGA_PUDC

WARM_RESETSW7-P1

MMC_RESETSTAT#_RMMC_POR_IN_AMC#_RMMC_WR_AMC#_R

FPGA_DSPCLKSEL

WARM_RESET

VCC1P8_PGOOD

FULL_RESETSW8-P1

FULL_RESET

SYS_PGOOD

FPGA_SSPMISO

FPGA_TCLKD_P FPGA_TCLKD_NFPGA_TCLKC_P FPGA_TCLKC_N

FPGA_TCLKB_NTCLKA_N

FPGA_TCLKB_PTCLKA_P

VCC1V5_EN_R

VCC1V8_EN1_RVCC0V75_EN_RVCC2V5_EN_RVCC_5V_EN_R

UCD9222_ENA1_R

UCD9222_ENA2_R

MOD4_SCK_R

MOD3_SCK_R

PACLKSEL

BID0BID1

BID0

BID1

DSP_VCL_FPGA

DSP_VD_FPGA

MOD1_SCK_R

FPGA_TCLKD_NFPGA_TCLKD_P

FPGA_TCLKB_NFPGA_TCLKB_P

FPGA_TCLKC_NFPGA_TCLKC_P

VCC1V8_AUX

VCC3V3_FPGA

VCC1V8_AUX

VCC3V3_FPGA

VCC3V3_FPGA

VCC1V8

VCC3V3_FPGA

VCC1V8_AUX

INMMC_POR_IN_AMC#(12)INMMC_RESETSTAT#(12)INMMC_DETECT#(12)

IN FPGA_SSPCS1 (16)

IN DSP_SSPMOSI (16,27,30)

INVCC3_AUX_PGOOD(36)

INMMC_WR_AMC#(12)

OUT DSP_CORESEL0 (16)OUT DSP_CORESEL1 (16)OUT DSP_CORESEL2 (16)OUT DSP_DSPCLKSEL (18,32)OUT DSP_NMIZ (16)OUT DSP_LRESETZ (18)

IN DSP_SYSCLKOUT (18)

OUTVCC1P5_EN(37)

OUTVCC1P8_EN1(35)

OUTVCC2P5_EN(35)OUTVCC0P75_EN(35)

OUTVCC_5V_EN(36)

INVCC2P5_PGOOD(35)INVCC5_PGOOD(36)

OUT DSP_SSPMISO (16,30)

OUT XDS560_IL (15)

OUT DSP_RESETZ (18)

OUT DSP_PORZ (18)OUT DSP_RESETFULLZ (18)

OUT NAND_WP# (15)

INPGUCD9222(34)OUTUCD9222_ENA1(34)INUCD9222_PG1(34)

OUTUCD9222_RST#(34)

OUTMMC_BOOTCOMPLETE(12)

OUT EEPROM_WP (16)OUT NOR_WP# (16)

IN TRGRSTZ (15)IN DSP_RESETSTAT# (18)

IN FPGA_SSPCK (16)

INMMC_SPI_MISO(12)OUTMMC_SPI_MOSI(12)

OUTMMC_SPI_STE(12)OUTMMC_SPI_SCK(12)

IN FPGA_EXTFRAMEEVENT (16)

OUT DSP_LRESETNMIENZ (18)

INPHY_INT#(28)

INTCLKD_N(11,24)INTCLKD_P(11,24)

INTCLKA_P(11)INTCLKA_N(11)

INTCLKB_P(11,23)INTCLKB_N(11,23)

OUTFPGA_ICS557_SEL(18)

OUTFPGA_ICS557_PD#(18)

OUTPHY_RST#(28)

OUTFPGA_ICS557_OE(18)

INUCD9222_PG2(34)OUTUCD9222_ENA2(34)

BIMOD3_SDA(17)

BIMOD4_SDA(17)

OUT DSP_PACLKSEL (18)

OUTPCA9306_EN(18)

OUTMOD3_SCK(17)

OUTMOD4_SCK(17)

OUT FPGA_FSYNC (27)

IN DSP_HOUT (16)

IN DSP_BOOTCOMPLETE (16)

IN FPGA_TIMI0 (27)

INDSP_VCL_1(18)

BIDSP_VD_1(18)

OUTMOD1_SCK(17)BIMOD1_SDA(17)

OUT PPS_INTERRUPT (16)

IN DSP_TIMO0 (16,27,30)IN DSP_TIMO1 (16,30)

INVCC0P75_PGOOD(35)INVCC1P5_PGOOD(37)

INTCLKC_N(11)INTCLKC_P(11)

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_A

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_A

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_A

C


DSPM-8303E

C3300.1uF16V

R130 10

R316330

R97 NL/1K

B35 120_100MHz 2A

C238 0.1uF 16V

B15 120_100MHz 2A

R4738.2K R87

10K

RST_WARM1

HDK632AR-ST

12

34

R129 10R212 0

R193 NL/0

C232 0.1uF 16V

R191 0

R189 0

C3310.1uF16V

R428 NL/100

R387 1K

R433 1K

C3740.1uF16V

C3100.1uF16V

R391 1K

R214 100

R171 0

R460 1K

R418 100

R1948.2K

C4870.01uF16V

B

SYSPG_D1

19-215SUBC/S280/TR8

12

C233 0.1uF 16V

R417 100

R151 NL/1K

R425 1K

Bank0Bank1

FPGA1A


IO_L01N_0C13

IO_L01P_0D13

IO_L02N_0B14

IO_L02P_0/VREF_0_1B15

IO_L03N_0D11

IO_L03P_0C12

IO_L04N_0A13

IO_L04P_0A14

IO_L05N_0A12

IO_L05P_0B12

IO_L06N_0/VREF_0_2E10

IO_L06P_0D10

IO_L07N_0A11

IO_L07P_0C11

IO_L08N_0A10

IO_L08P_0B10

IO_L09N_0/GCLK5D9

IO_L09P_0/GCLK4C10

IO_L10N_0/GCLK7A9

IO_L10P_0/GCLK6C9

IO_L11N_0/GCLK9D8

IO_L11P_0/GCLK8C8

IO_L12N_0/GCLK11B8

IO_L12P_0/GCLK10A8

IO_L13N_0C7

IO_L13P_0A7

IO_L14N_0/VREF_0_3E7

IO_L14P_0F8

IO_L15N_0B6

IO_L15P_0A6

IO_L16N_0C6

IO_L16P_0D7

IO_L17N_0C5

IO_L17P_0A5

IO_L18N_0B4

IO_L18P_0A4

IO_L19N_0B3

IO_L19P_0A3

IO_L20N_0/PUDCD5

IO_L20P_0/VREF_0_4C4

IP_0_1D6

IP_0_2D12

IP_0_3E6

IP_0_4F7

IP_0_5F9

IP_0_6F10

IP_0_7/VREF_0_5E9

VCCO_0_1B5

VCCO_0_2B9

VCCO_0_3B13

VCCO_0_4E8

IO_L01N_1/LDC2N14

IO_L01P_1/HDCN13

IO_L02N_1/LDC0P15

IO_L02P_1/LDC1R15

IO_L03N_1/A1N16

IO_L03P_1/A0P16

IO_L05N_1/VREF_1_1M14

IO_L05P_1M13

IO_L06N_1/A3K13

IO_L06P_1/A2L13

IO_L07N_1/A5M16

IO_L07P_1/A4M15

IO_L08N_1/A7L16

IO_L08P_1/A6L14

IO_L10N_1/A9J13

IO_L10P_1/A8J12

IO_L11N_1/RHCLK1K14

IO_L11P_1/RHCLK0K15

IO_L12N_1/TRDY1/RHCLK3J16

IO_L12P_1/RHCLK2K16

IO_L14N_1/RHCLK5H14

IO_L14P_1/RHCLK4J14

IO_L15N_1/RHCLK7H16

IO_L15P_1/IRDY1/RHCLK6H15

IO_L16N_1/A11F16

IO_L16P_1/A10G16

IO_L17N_1/A13G14

IO_L17P_1/A12H13

IO_L18N_1/A15F15

IO_L18P_1/A14E16

IO_L19N_1/A17F14

IO_L19P_1/A16G13

IO_L20N_1/A19F13

IO_L20P_1/A18E14

IO_L22N_1/A21D15

IO_L22P_1/A20D16

IO_L23N_1/A23D14

IO_L23P_1/A22E13

IO_L24N_1/A25C15

IO_L24P_1/A24C16

IP_L04N_1/VREF_1_2K12

IP_L04P_1K11

IP_L09N_1J11

IP_L09P_1/VREF_1_3J10

IP_L13N_1H11

IP_L13P_1H10

IP_L21N_1G11

IP_L21P_1/VREF_1_4G12

IP_L25N_1F11

IP_L25P_1/VREF_1_5F12

SUSPENDR16

VCCO_1_1E15

VCCO_1_2H12

VCCO_1_3J15

VCCO_1_4N15

R440 33 1%

R192 22

R385NL/10K

R443 0

C239 0.1uF 16V

R444 0

R211 0

R447 33 1%

R438 22

R138 1K

C1160.01uF16V

R445 10K

R164 1K

C4490.1uF16V

R213 22

R187 NL/0

R474 100

R141 10

C4340.1uF16V

C3940.1uF16V

RST_FULL1

HDK632AR-ST

12

34

C4300.1uF16V

R190 0

R416 100

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DEBUG_LED

BOOT STRAP CONFIGURATION

For BOOTMODESWITCH

SOCGPIO TOFPGA

CDCE62005

CDCE62002

For FPGA internal reset.

the signal of user define set to BM_GPIO_16 ( software setup )

A101-1

BM_GPIO_16 is not connected to FPGA, and so we make a workaround on FPGA code to control GPIO16 with SW2(user define pin)

A101-1

Description

0

1When the master bit of DEVSTAT is set to 1, the

ARM initiates boot

When the master bit of DEVSTAT is set to 0, the

CorePac initiates boot.

BM_GPIO16

Boot Master

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

PA driver from PA clkSGMII

PCIe

I2C

1 1 0

1 1 1

SPI

HyperLink

Boot

DeviceNOTE

PA driven from core clk

BM_GPIO

NO BOOT/EMIF16

sRIO

SGMII

3 2 1

CorePac Boot Device

0 0 0 0

UART

Ethernet

Ethernet

Ethernet

PCIe

1st Boot Device 2nd Boot Device BM_GPIO

No Boot

UART

UART

10 9 8 7

ARM Boot Device

N/A

EMIF16

EMIF16/wait

NAND

EMIF16

EMIF16/wait

NAND

SPI

SPI

EMIF16

NAND/I2C

NAND

PCIe

PCIe

SPI

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

EMIF16

EMIF16/wait

NAND

1 1 1 1

EMIF16

EMIF16/wait

NAND

NAND

EMIF16

EMIF16

Function

Boot Device

Endian

DIP Switch

CorePac Boot Configuration

BM_GPIO_00

BM_GPIO [01:03]

BM_GPIO [04:05] Reserved

BM_GPIO [06:10] Device Cfg

BM_GPIO [11:13] PLL Multiplier/I2C

SOC

GPIO0

GPIO[1:3]

Boot Mode

GPIO[4:5]

BOOTMODE[00:02]

Endian

BM_GPIO [14:15]

GPIO[6:10]

GPIO[11:13]

GPIO[14:15]

BM_GPIO 16 Master

Endpt/RootComplex

BOOTMODE[03:04]

BOOTMODE[05:09]

BOOTMODE[10:12]

PCIESSMODE[0:1]

BOOTMODE13GPIO16

Function

Reserved

Endian

DIP Switch

ARM Boot Configuration

BM_GPIO_00

BM_GPIO [01:02]

BM_GPIO [03:06] Boot Mode Config

BM_GPIO [07:10] Boot Mode Sequence

BM_GPIO [11:13] PLL Cfg

SOC

GPIO0

GPIO[1:2]

Boot Mode

GPIO[3:6]

BOOTMODE[00:01]

Endian

BM_GPIO [14:15]

GPIO[7:10]

GPIO[11:13]

GPIO[14:15]

BM_GPIO 16 Master

Endpt/RootComplex

BOOTMODE[02:05]

BOOTMODE[06:09]

BOOTMODE[10:12]

PCIESSMODE[0:1]

BOOTMODE13GPIO16

Description

0

1Initial state of the power domain and the clock

domain for PCIE subsystem is enabled

Initial state of the power domain and the clock

domain for PCIE subsystem is disabled

Input

PCIESSEN

INPUT Description

00b

01b

10b

PCIe in Legacy End-point mode(no support for MSI)

PCIe in Legacy Root complex mode

PCIe in End-point mode

BM_GPIO[15:14]

PCIe Modeselection(PCIESSMODE[1:0])

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

PA driver from PA clk100.00

156.25

250.00

1 1 0

1 1 1

312.50

122.88

INPUT

CLK (MHz)CorePac System PLL Configuration

PA driven from core clk

BM_GPIO

50.00

66.67

80.00

13 12 11

PLL Settings

DescriptionDSP_DSPCLKSELL = 0

Input

CLK ModeClock

SYSCLK /

ALTCORECLK

PASSCLK

DSP_DSPCLKSEL = 1

FPGA_PACLKSEL = 0

FPGA_PACLKSEL = 1

SYSCLK used to clock the core PLL.

ALTCORECLK is used to clock the core PLL

PASSCLK is not used and should be tied to a static state.

PASSCLK is used as a source for the PA_SS PLL. It must be present before the PA_SS PLL is removed from reset and programmed

Default_Down

Default_Down

FPGA_M0 FPGA_M1 FPGA_M2

DEBUG_LED_1 DEBUG_LED_3DEBUG_LED_2DEBUG_LED_0

BM_GPIO_00BM_GPIO_01BM_GPIO_02BM_GPIO_03




FPGA_M0FPGA_M1

FPGA_INIT#

BM_GPIO_05

BM_GPIO_14BM_GPIO_13

BM_GPIO_08BM_GPIO_07BM_GPIO_06

BM_GPIO_00


BM_GPIO_15


DSP_GPIO_05

DSP_GPIO_14DSP_GPIO_13

DSP_GPIO_08DSP_GPIO_07DSP_GPIO_06

DSP_GPIO_00

DSP_GPIO_12DSP_GPIO_11DSP_GPIO_10DSP_GPIO_09

DSP_GPIO_15

DSP_GPIO_04DSP_GPIO_03DSP_GPIO_02DSP_GPIO_01

DEBUG_LED_1DEBUG_LED_0

DEBUG_LED_3

PCIESSENUser define

PCIESSENUser define

DSP_TIMI0_R

FPGA_M2

CLOCK2_SSPSO

CLOCK2_SSPCS1CLOCK2CK

CLOCK2_SSPSI

CLOCK3_SSPSO

CLOCK3_SSPCS1CLOCK3CK

CLOCK3_SSPSI

REFCLK3_PD#

REFCLK2_PD#

CLOCK1CKCLOCK1_SSPCS1

MAIN_48MHZ_CLK_R

CLOCK3_PLL_LOCKCLOCK2_PLL_LOCKCLOCK1_PLL_LOCK

FPGA_INIT#DEBUG_LED_2

DSP_TIMI1_R

MAIN_48MHZ_CLK MAIN_48MHZ_CLK_R

FPGA_PACLKSEL

FPGA_PACLKSEL

CLOCK1_SSPSOCLOCK1_SSPSI

REFCLK1_PD#

MOD2_SCK_R

BM_GPIO_16

VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGAVCC3V3_FPGA VCC3V3_FPGAVCC3V3_FPGAVCC3V3_FPGA

VCC1V8_AUX

VCC1V8_AUX

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_AUX

VCC1V8VCC1V8

INDSP_GPIO_00(16,30)INDSP_GPIO_01(16,30)INDSP_GPIO_02(16,30)INDSP_GPIO_03(16,30)INDSP_GPIO_04(16,30)INDSP_GPIO_05(16,30)INDSP_GPIO_06(16,30)INDSP_GPIO_07(16,30)INDSP_GPIO_08(16,30)INDSP_GPIO_09(16,30)INDSP_GPIO_10(16,30)INDSP_GPIO_11(16,30)INDSP_GPIO_12(16,30)INDSP_GPIO_13(16,30)INDSP_GPIO_14(16,30)INDSP_GPIO_15(16,30)

IN CLOCK2_SSPSO (23)

IN CLOCK3_SSPSO (24)

OUT CLOCK2_SSPCK (23)OUT CLOCK2_SSPSI (23)

OUT REFCLK3_PD# (24)

OUT CLOCK3_SSPCK (24)OUT CLOCK3_SSPSI (24)

OUT CLOCK3_SSPCS1 (24)

OUT CLOCK2_SSPCS1 (23)


OUT CLOCK1_SSPCS1 (22)OUT CLOCK1_SSPCK (22)

IN CLOCK1_PLL_LOCK (22)



OUTDSP_TIMI1(16,30)OUTDSP_TIMI0(16,27,30)

OUT DSP_DSPCLKSEL (18,31)

IN FPGA_DONE (33)

OUT VID_OE# (18)

IN BUFCLK_FPGA (27)

IN CLOCK1_SSPSO (22)OUT CLOCK1_SSPSI (22)



OUT DAC_CLR# (27)OUT DAC_LD# (27)

OUT MOD2_SCK (17)BI MOD2_SDA (17)

IN TX_FAULT1 (17)IN TX_FAULT2 (17)IN TX_FAULT3 (17)IN TX_FAULT4 (17)

IN LOS_1 (17)

IN LOS_2 (17)IN LOS_3 (17)IN LOS_4 (17)

OUT TX_DISABLE (17)

OUT RATESELECT (17)

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_B

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_B

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_B

C


DSPM-8303E

R583 100

B16120_100MHz0.5A

B

FPGA_D4

19-215SUBC/S280/TR8

12

R340330

ON

SW3ESD104EZ1234 5

8

67

R402 10

R535 10K

R557 10K

R382 NL/10

R390NL/0

1

SW7ESD101EZ1 2

R546 10K

R383NL/330

R161 10

R398 10K

R549 10K

C2940.1uF16V

B

FPGA_D2

19-215SUBC/S280/TR8

12

C3680.1uF16V

R410NL/0

R541 10K

R82 NL/10

R99 10K

R388 10K

R401 10

R341330

R538 10K

C3040.1uF16V

R591 100

R547 10K

R584 100R539 10K

C2950.1uF16V

R581 100

ON

SW4ESD104EZ1234 5

8

67

R550 10K

R559 10K

C3110.1uF16V

R386NL/0

R580 100

TP51

R121 22

R534 10K

R572 100

R93330

R567 100

R537 10K

R540 10K

B3120_100MHz

2A

R570 100

Y2

48MHz_15pF

3.3V

VCC4

OUT3

GND2

OE1

Bank2Bank3

FPGA1B


IO_L01N_2/M0P4

IO_L01P_2/M1N4

IO_L02N_2/CSOT2

IO_L02P_2/M2R2

IO_L03N_2/VS2T3

IO_L03P_2/RDWRR3

IO_L04N_2/VS0P5

IO_L04P_2/VS1N6

IO_L05N_2R5

IO_L05P_2T4

IO_L06N_2/D6T6

IO_L06P_2/D7T5

IO_L07N_2P6

IO_L07P_2N7

IO_L08N_2/D4N8

IO_L08P_2/D5P7

IO_L09N_2/GCLK13T7

IO_L09P_2/GCLK12R7

IO_L10N_2/GCLK15T8

IO_L10P_2/GCLK14P8

IO_L11N_2/GCLK1P9

IO_L11P_2/GCLK0N9

IO_L12N_2/GCLK3T9

IO_L12P_2/GCLK2R9

IO_L13N_2M10

IO_L13P_2N10

IO_L14N_2/MOSI/CSIP10

IO_L14P_2T10

IO_L15N_2/DOUTR11

IO_L15P_2/AWAKET11

IO_L16N_2N11

IO_L16P_2P11

IO_L17N_2/D3P12

IO_L17P_2/INITT12

IO_L18N_2/D1R13

IO_L18P_2/D2T13

IO_L19N_2P13

IO_L19P_2N12

IO_L20N_2/CCLKR14

IO_L20P_2/D0/DIN/MISOT14

IP_2_1L7

IP_2_2L8

IP_2_3/VREF_2_1L9

IP_2_4/VREF_2_2L10

IP_2_5/VREF_2_3M7

IP_2_6/VREF_2_4M8

IP_2_7/VREF_2_5M11

IP_2_8/VREF_2_6N5

VCCO_2_1M9

VCCO_2_2R4

VCCO_2_3R8

VCCO_2_4R12

IO_L01N_3C1

IO_L01P_3C2

IO_L02N_3D3

IO_L02P_3D4

IO_L03N_3E1

IO_L03P_3D1

IO_L05N_3E2

IO_L05P_3E3

IO_L07N_3G4

IO_L07P_3F3

IO_L08N_3/VREF_3_1G1

IO_L08P_3F1

IO_L09N_3H4

IO_L09P_3G3

IO_L10N_3H5

IO_L10P_3H6

IO_L11N_3/LHCLK1H1

IO_L11P_3/LHCLK0G2

IO_L12N_3/IRDY2/LHCLK3J3

IO_L12P_3/LHCLK2H3

IO_L14N_3/LHCLK5J1

IO_L14P_3/LHCLK4J2

IO_L15N_3/LHCLK7K1

IO_L15P_3/TRDY2/LHCLK6K3

IO_L16N_3L2

IO_L16P_3/VREF_3_2L1

IO_L17N_3J6

IO_L17P_3J4

IO_L18N_3L3

IO_L18P_3K4

IO_L19N_3L4

IO_L19P_3M3

IO_L20N_3N1

IO_L20P_3M1

IO_L22N_3P1

IO_L22P_3N2

IO_L23N_3P2

IO_L23P_3R1

IO_L24N_3M4

IO_L24P_3N3

IP_L04N_3/VREF_3_3F4

IP_L04P_3E4

IP_L06N_3/VREF_3_4G5

IP_L06P_3G6

IP_L13N_3J7

IP_L13P_3H7

IP_L21N_3K6

IP_L21P_3K5

IP_L25N_3/VREF_3_5L6

IP_L25P_3L5

VCCO_3_1D2

VCCO_3_2H2

VCCO_3_3J5

VCCO_3_4M2

R545 10K

C330.1uF16V

ON

SW6ESD104EZ1234 5

8

67

C660.1uF16V

R573 100

R95330

R569 100

R579 100

R339330

TP50

R560 10K

B

FPGA_D1

19-215SUBC/S280/TR8

12

C3370.1uF16V

R1371K

R571 100

R392 10

R582 100

R313 100

B6120_100MHz

2A

R585 1K

R558 10KC1040.1uF16V

R128 331%

R536 10K

R578 100

R342330

R575 100

R577 100

R568 100

R564 10K

R542 10K

R574 100

ON

SW2ESD104EZ1234 5

8

67

R576 100

R543 10K

R544 10K

B

FPGA_D3

19-215SUBC/S280/TR8

12

ON

SW5ESD104EZ1234 5

8

67

R890

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

During Configuration :Must be High to allowconfiguration to start.

FPGA_PROG

FPGA_PROG

FPGA_DONE

FPGA_DONE

BSC_JTAG_TDI

BSC_JTAG_TCK

BSC_JTAG_TCK

BSC_FPGA_TCK

BSC_PHY_TCK

BSC_JTAG_RST#

BSC_JTAG_TMS

BSC_JTAG_TDO

BSC_JTAG_TCK

BSC_JTAG_TDO

BSC_JTAG_TMS

BSC_FPGA_TCK

BSC_JTAG_P8

BSC_JTAG_TDOBSC_JTAG_TMSBSC_JTAG_RST#BSC_JTAG_P8

BSC_JTAG_TCK

VCC3V3_FPGA VCC3V3_FPGA

VCC1V2_FPGAVCC1V2VCC3V3_FPGAVCC3V3_AUX

VCC3V3_FPGA

VCC1V2_FPGA

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_FPGA

OUT BSC_PHY_TCK (28)

OUTFPGA_JTAG_TDO(28)

IN BSC_JTAG_TDI (28)

OUT BSC_JTAG_TMS (28)OUT BSC_JTAG_RST# (28)

OUTFPGA_DONE(32)

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_C

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_C

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

FPGA_XC3S200AN_C

C


DSPM-8303E

C3500.1uF16V

C3330.1uF16V

C3450.1uF16V

R59 4.7K

R68 4.7K

R186 22

R185 22

R91NL/100K

R70 NL/1K

R3844.7K

R58 22

C3710.1uF16V

G

D1NL/KP-1608SGD

12

TAP_FPGA1PH_8x1V_2.54mm

12345

76

8

R42 4.7K

FPGA1C


DONET15

PROGA2

TCKA15

TDIB1

TDOB16

TMSB2

VCCAUX_1E11

VCCAUX_2F5

VCCAUX_3L12

VCCAUX_4M6

VCCINT_1G7

VCCINT_2G9

VCCINT_3H8

VCCINT_4J9

VCCINT_5K8

VCCINT_6K10

GND_1A1

GND_2A16

GND_3B7

GND_4B11

GND_5C3

GND_6C14

GND_7E5

GND_8E12

GND_9F2

GND_10F6

GND_11G8

GND_12G10

GND_13G15

GND_14H9

GND_15J8

GND_16K2

GND_17K7

GND_18K9

GND_19L11

GND_20L15

GND_21M5

GND_22M12

GND_23P3

GND_24P14

GND_25R6

GND_26R10

GND_27T1

GND_28T16

R370 22

C1090.1uF16V

C3490.1uF16V

C3360.1uF16V

C37810uF6.3V

C3090.1uF16V

U15BTI_SN74LVC2G125DCUR

7

5 3

B36 120_100MHz2A

C32910uF6.3V

R371 4.7K

C3770.1uF16V

R74 0

C3140.1uF16V

R69 4.7K

C22 0.1uF16V

C3340.1uF16V

C3320.1uF16V

R338NL/330

R248 22

R3471K

C3790.1uF16V

U15ATI_SN74LVC2G125DCUR

18

2

4

6

B8 120_100MHz2A

R56 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CVDDPMBus RESISTANCE ( K ohm )PMBus Address

OPEN

11

10

9

8

7

6

5

4

3

2

1

0

SHORT

--

205

178

154

133

115

100

86.6

75

64.9

56.2

48.7

42.2

--

PMBus Address Bins

PMBUS Address

=> 6*12+6 = 78

=> 0x4Eh

Remove other JTAG pins from the

boundary scan chain.

VCC1V0

SOC Vcore @TBDTemperaturesense pin

Current sensemonitor output

1K ohm

470 pF

10 ohm

10 ohm

EAP2EAN2

VCC1V0

GND

Series resistors on EA nets to be placed at the load for proper voltage feedback.

UCD9222

EAp1

EAn1

EAp2

EAn2

1K ohm

470 pF

SOC

10 ohm

10 ohm

EAP1EAN1

CVDD

GND

note: he caps on BPCAP and V33A/ V33D pins need to be placed at the same side with UCD9222 and keep the caps as close as possible.

A101-1Parallel the 0.1uF capacitor at the R102 and R103 for VCC1P0 DC load failure

PMBUS_DATPMBUS_CLK

PMBUS_ALT

RST#

PGUCD9222 EAP1EAN1

PMBUS_CTL

9222_TDO

9222_TMS9222_TDI

9222_TCK

9222_TRST#

9222_TMS9222_TRST#

9222_TDO

9222_TCK9222_TDI

PMBUS_ALTPMBUS_DAT

PMBUS_CTL

PMBUS_CLK

9222_TEMP2

CSN

CSP

SW_Shape

RDLY

VGG

9222_TEMP1

AVGG

PWM-2A

FF-1A2

PWM-1A

SRE_A

FF-1A1

lsenes-1ASRE_B

lsenes-2A

VGG

ILIM

FLTRST

EAP2EAN2

CS1AUCD9222_ENA1

FF-1A1PWM-1AUCD9222_PG1

FF-1A2

lsenes-2A

PWM-2A

CS2AUCD9222_ENA2UCD9222_PG2

lsenes-1A

UCD_VIN

EAP2

EAN2

EAP1

EAN1

9222_TEMP19222_TEMP2

linMon

linMon

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

CVDD

VCC3V3_AUX

VCC12

CVDD

VCC3V3_AUX

VCC12

VCC3V3_AUX

VCC1V0

VCC12

VCC3V3_AUX

VCC3V3_AUX

VCC1V0

VCC12

VCC3V3_AUX

VCC3V3_AUX

OUTPGUCD9222(31)

INUCD9222_RST#(31)

IN UCD9222_VIDA (18)IN UCD9222_VIDB (18)IN UCD9222_VIDC (18)IN UCD9222_VIDS (18)

IN UCD9222_ENA1 (31)OUT UCD9222_PG1 (31)

OUT UCD9222_PG2 (31)

IN UCD9222_ENA2 (31)

Title


Date: Sheet of


TMS320TCI6614 A101

Smart_Reflex AVS

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Smart_Reflex AVS

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Smart_Reflex AVS

C


DSPM-8303E

R136 0

R125NL/10K

L2 0.2uH 24A

R419 10

R318 10K

Rework 0.1uF

R412 10K

C411 0.01uF 16V

R102 10K

Q3

MICROCHIP_MCP9700AT-E/LT

NC11VOUT3

GND

2

VDD4

NC25

C4840.1uF16V

U12

TI_UCD9222RGZR

VinMon4

Vtrack45

Temp1/AuxADC146

Temp2/AuxADC22

ADC_REF48

EAp137

EAn138

EAp239

EAn240

JTAG_TRST31 JTAG_TMS30

JTAG_TDI/SYNC_IN29

JTAG_TDO/SYNC_OUT28

JTAG_TCK27

PMBus_ADDR044

PMBus_ADDR143

PowerGood17

PMBUS_CLK10

PMBUS_DATA11

PMBUS_ALERT19

PMBUS_CNTRL20

RESET5

V33FB41

V33A34

V33DIO33

BPCAP35

VID1A16

VID1B18

VID1C21

VID1S7

VID2A22

VID2B23

VID2C24

VID2S9

CS1A42

DPWM1A12

ENA125

FLT1A6

PG113

IinMon1 CS2A

3

DPWM2A14

ENA226

FLT2A8

PG215

AGND236

AGND347

DGND332

PowerPad49

Thermal_VIA150

Thermal_VIA251

Thermal_VIA352

Thermal_VIA453

Thermal_VIA554

Thermal_VIA655

Thermal_VIA756

Thermal_VIA857

Thermal_VIA958

Thermal_VIA1059

Thermal_VIA1160

Thermal_VIA1261

Thermal_VIA1362

Thermal_VIA1463

Thermal_VIA1564

Thermal_VIA1665

Thermal_VIA1766

Thermal_VIA1867

Thermal_VIA1968

Thermal_VIA2069

Thermal_VIA2170

Thermal_VIA2271

Thermal_VIA2372

Thermal_VIA2473

Thermal_VIA2574

C413 1uF 6.3V

C56347uF6.3V

R424 2.2 1%

C88 1uF 16V

C56122uF16V

R165 2.49K 1%

R126 10K

R42110K1%

C2200.1uF16V

R4310

C94 470pF 50V

R2681.3K1%

R180 100K

C130 0.1uF 16V

C12522uF16V

R423 10K 1%

R432 931 1%

L100.47uH17.5A

C45847uF6.3V

TROY (UCD74110)

U16

<Characteristic>TI_TROY(UCD74110)

ILIM32

SRE_MD30

CSP36

NC_2

6

VGG3

VGG_DIS2

RDLY39

NC_3

34

SW_17

FLT29

IMON33

AGND1

BP337

HS_SNS28

SRE31

PWM38 V

IN_3

23

AVGG40

VIN_4

24

VIN_1

21

BOOT5

VIN_2

22

NC_1

4

VIN_5

25

VIN_6

26

SW_28

SW_39

SW_410

SW_511

SW_612

VDD27

CSN35

PGND_113

PGND_214

PGND_315

PGND_416

PGND_517

PGND_618

PGND_719

PGND_820

Thermal_PAD41

Thermal_via142

Thermal_via243

Thermal_via344

Thermal_via445

Thermal_via546

Thermal_via647

Thermal_via748

Thermal_via849

Thermal_via950

Thermal_via1051

Thermal_via1152

Thermal_via1253

Thermal_via1354

Thermal_via1455

Thermal_via1556

Thermal_via1657

Thermal_via1758

Thermal_via1859

Thermal_via1960

Thermal_via2061

Thermal_via2162

TP6

R10448.7K1%

R134 10K

R166 2.49K 1%

R199 1K

R103 10K

R106 10K

C219470uF4V

R198 100K

R85 2K

C117470uF4V

C50347uF6.3V

C97 470pF 50V

R441 8.06K1%

R119 10K

C118470uF4V

R224 2K

C650.1uF16V

UCD74106

U23

<Characteristic>TI_UCD74106RGMT

FLTRST12

VGG5

SW6

FLT2

TMON10

IMON11

AGND

8

BP3

9

BST1

SRE3

PWM4

VIN13

PGND7

C461 0.1uF16V

R84 100K

C86 0.01uF 16V

C195470uF4V

C1861000pF50V

R1701K1%

R206 10K

R449 10K

R184 NL/2K

R86 2K

R182 NL/2K

R420 NL/0

R30710K

C46447uF6.3V

PMBUS1PH_5x1V_2.54mm

12345

R149 10K

R201 1K

R197 2.49K 1%

C81 0.01uF 16V

C49647uF6.3V

C870.1uF16V

C49747uF6.3V

C1870.1uF16V

C506 4.7uF 16V

R3231K1%

R464 0

R415 10

C412 0.01uF16V

R219 22.6K1%

R454 21%

C46047uF6.3V

C2244.7uF16V

C4190.1uF16V

R111 10K

C2210.22uF25V

R83 10KR414 10

C1280.22uF25V

Rework 0.1uF

C4890.1uF16V

TP19

C904.7uF6.3V

R81 1M

Q9

MICROCHIP_MCP9700AT-E/LT

NC11VOUT3

GND

2

VDD4

NC25

R408 10

C410 0.1uF 16V

C56447uF6.3V

C1891uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Vout=(R1+R2)/R2*1.204

R1

R2

R1

R2

Vout=(R1+R2)/R2*1.204

R1

R2

Vout=(R1+R2)/R2*1.204R1

R2

Vout=(R1+R2)/R2*1.2041.805V =(28k+56.2k)/56.2k*1.205

1.805V =(28k+56.2k)/56.2k*1.205

2.50V =(39.2k+36.5k)/36.5k*1.204

1.204V = (0+10k)/10k*1.204

VCC1V8

1.2V @0.38A

VCC1V2

VCC0V75

2.5V @0.21AVCC2V5

0.75V @TBD

1.8V@TBD

VCC1V8_AUX

1.8V_AUX @0.3A

VCC0P75_PGOOD

VCC2P5_EN

VCC0P75_EN

VCC2P5_PGOOD

VCC3V3_AUX VCC1V2 VCC3V3_AUX VCC1V8_AUX

VCC3V3_AUX

VCC2V5

VCC3V3_AUX

VCC0V75

VCC3V3_AUX VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX VCC1V8

VCC2V5

VCC1V5

OUT VCC0P75_PGOOD (31)

IN VCC0P75_EN (31)

INVCC2P5_EN(31)

IN

VCC1P8_EN1(31)


Title


Date: Sheet of


TMS320TCI6614 A101

Power_1.2V/1.8V/2.5V/0.75V

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power_1.2V/1.8V/2.5V/0.75V

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power_1.2V/1.8V/2.5V/0.75V

C


DSPM-8303E

C24110uF6.3V

C1000.1uF16V

C22610uF6.3V

C8910uF6.3V

C19310uF6.3V

R202 1K

R3321K1%

C1900.1uF16V

C2430.1uF16V

TP43

TP22

C12110uF6.3V

R17839.2K1%

R335 1K 1%

R53356.2K1%

R20710K

Q10TI_TPS73701DRBT

EN5

GND

4

VIN8

VOUT1

FB3

EPAD

9

NC1

2

NC2

6

NC3

7

R245 10K

R33010K

R532 10KR45010K1%

R43636.5K1%

VCC

GND

U14

TI_SN74LVC1G07DBVR

123 4

5

Q4TI_TPS73701DRBT

EN5

GND

4

VIN8

VOUT1

FB3

EPAD

9

NC1

2

NC2

6

NC3

7

TP7C12210uF6.3V

C990.1uF16V

C57310uF6.3V

C24910uF6.3V

R53128K1%

R32010K

C2480.1uF16V

C57410uF6.3V

C5710.1uF16V

C9810uF6.3V

C2460.1uF16V

C24010uF6.3V

C2270.1uF16V

C2510.01uF16V

R30928K1%

Q1TI_TPS73701DRBT

EN5

GND

4

VIN8

VOUT1

FB3

EPAD

9

NC1

2

NC2

6

NC3

7

C5720.1uF16V

Q2TI_TPS73701DRBT

EN5

GND

4

VIN8

VOUT1

FB3

EPAD

9

NC1

2

NC2

6

NC3

7

C24210uF6.3V

R246NL/1K

R43705%

C1190.1uF16V

R48210K

R32710K

R31156.2K1%

TP5

TP20

C5050.1uF16V

U25TI_TPS51200DRCT

REFIN1

VLDOIN2

VO3

PGND4

VOSNS5

REFOUT6

EN7

GND8

PGOOD9

VIN10

EPAD

11

VIA1

12

VIA2

13

VIA3

14

VIA4

15

VIA5

16

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

R1

R2

VCC5

5V @1A

VCC3V3_AUX

R1

R2

Assume 90% Pe,

Iin = ( 3.3V * 2.58A ) / 90% / 12V = 788mA

[email protected]_AUX @2.57A

Assume 80% Pe,

Iin = ( 5V * 1A ) / 80% / 12V = 520mA

[email protected]

+++output capacitor Calculation++++++Inductor Calculation+++L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw))L = ((12.6 - 5)/1 * Kind) * (5 / (12.7 * 570K))L = ((7.6/ 0.3) * (5 / (7239K))L = (25.3) * (0.69M)L = 17.5uH

Reference Inductor 22uH

5=0.8 V*(10k/1.87k+1)

Vout=0.8 V*(R1/R2+1)

(KIND=0.3)

Cout=1/( 2 * 3.14 * 5 * 25K)Cout=1.3 uf

Reference Capacitor=100uF

(KIND=0.3)(Over all tolerance is 5% ,DC tolerance is 2.5% )

Cout=(2*delta(Iout))/(Fsw*delta(Vout))

Cout=(2*3/(840kHz*0.0825)

Cout=~87uF


+++Inductor Calculation+++

L = (Vin - Vout)/(Iout * Kind) * (Vout/(Vin * Fsw)

L = ((12 - 3.3)/(3A * 0.3) * (3.3 / (12 * 840kHz))

L = 9.67 * 0.33u

L = ~3.2 uH

3.3=0.8 V*(10k/3.1k+1)

Vout=0.8 V*(R1/R2+1)

+++output capacitor Calculation+++

Reference Inductor 3.3uH

Rrt=48000xFsw(kHz)^(-0.997-2)

=48000x840^(-0.997-2)

=~56.2 (k ohms)

VCC3_AUX_PGOOD

VCC5_PGOOD

VCC3V3_AUX_ENVCC3V3_AUX_EN_R

VCC3V3_AUX_EN

VCC5

VCC12

VCC3V3_AUXVCC12

VCC12

VCC3V3_AUX

VCC12

VCC3V3_AUX

VCC5

INVCC_5V_EN(31)

OUT VCC3_AUX_PGOOD (31)

OUT VCC5_PGOOD (31)

Title


Date: Sheet of


TMS320TCI6614 A101

Power_VCC5 / VCC3V3_AUX

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101


C


DSPM-8303E

C12610uF16V

U21TI_TPS54620RGY

RT/CLK1

GND12

GND23

PVIN14

PVIN25

VIN6

VSENSE7

PWRGD14

BOOT13

PH212

PH111

EN10

SS/TR9

COMP8

EPAD

15

C1311200pF50V

VCC

GND

U17

TI_SN74LVC1G07DBVR

123 4

5

R52210K1%

R527 0

R26922.6K1%

C1580.1uF16V

TP17

R28031.6K1%

U18

TI_TPS54231D

BOOT1

VIN2

EN3

SS4

PH8

GND7

COMP6

VSENSE5

C51056pF50V

C1400.01uF16V

C518

0.1uF

16V

R308 56.2K 1%

R2551.87K1%

R28110K1%

B39120_100MHz

2A

R49133K

R2871.69K1%

C520NL/22uF12.5V

R49210K

C5178200pF50V

R52331.6K1%

C1200.01uF16V

C54410uF16V

C1460.01uF16V

C172100uF16V

R486 1K

C52310uF6.3V

D5B340A3A

12

R480 NL/0

C513NL/10uF16V

C53410uF16V

TP14C185 0.1uF 16V

C538100uF6.3V

R24010K1%

L4 22uH 2.8A

B38 120_100MHz2A

L3 3.3uH 6A

C546

0.1uF

16V

R23510K

R30610K

C161100uF6.3V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.52=0.8 V*(9.09k/10k+1)

Vout=0.8 V*(R1/R2+1)

R1

R2

1.5V @TBD

VCC1V5

(Over all tolerance is 5% ,DC tolerance is 2.5%)

Cout=(2*delta(Iout))/(Fsw*delta(Vout))

Cout=(2*2A)/(840kHz*0.0375)

Cout= 4/31.5k

Cout=~127uF


+++Inductor Calculation+++

L = (Vin - Vout)/(Iout * Kind) * Vout/(Vin * Fsw)

L = (12 - 1.5)/(2A * 0.3) * 1.5 / (12 * 840kHz)

L = (17.5) * (0.15u)

L = ~2.63uH

(KIND=0.3)

Reference Inductor 3.3uH

+++output capacitor Calculation+++

Assume 90% Pe,

Iin = ( 1.5V * 2.12A ) / 90% / 12V = 295mA

[email protected]

VCC1P5_EN

VCC1P5_PGOOD

VCC1V5

VCC3V3_AUX

VCC12

VCC12


IN VCC1P5_EN (31)

Title


Date: Sheet of


TMS320TCI6614 A101

Power VCC1V5

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power VCC1V5

C


DSPM-8303E

Title


Date: Sheet of


TMS320TCI6614 A101

Power VCC1V5

C


DSPM-8303E

U11TI_TPS54620RGY

RT/CLK1

GND12

GND23

PVIN14

PVIN25

VIN6

VSENSE7

PWRGD14

BOOT13

PH212

PH111

EN10

SS/TR9

COMP8

EPAD

15

C70100uF6.3V

R969.09K1%

R10510K1%

B9 120_100MHz2A

C7810uF16V

L13.3uH

6A

C630.01uF16V

C578200pF50V

R1161.69K1%

C82100uF6.3V

TP4

R15810K

R422 56.2K 1%

C37510uF16V

C79 0.1uF 16V

C64

0.1uF

16V

C342

0.1uF

16V

R11410K

5 4 3 2 1 d d tms320tci6614 evm board for...

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