5 February 2003 Paul Dauncey - Calice Status 1

CALICE Status

Paul Dauncey

Imperial College London

For the CALICE-UK groups: Birmingham, Cambridge, Imperial, Manchester, RAL, UCL

5 February 2003 Paul Dauncey - Calice Status 2

Study calorimetry for a future linear collider• Both electromagnetic (ECAL) and hadronic (HCAL)

• ECAL studies are for Si-W tracking calorimeter• HCAL studies are for analogue scintillating tile or digital (small cell) made

with RPC’s, scintillating tiles or GEM’s

• Big collaboration already…• 150 people, 24 institutes, 8 countries (including Europe, US and Asia)• DESY is a member (CALICE grew out of TESLA TDR studies)

• …and still expanding• 6 institutes have joined since the last LCUK meeting• FNAL have also approached the collaboration• Informal agreement on collaboration with SLAC/Oregon

• Recent summary of status written for DESY PRC in October• Can find from CALICE-UK page http://www.hep.ph.imperial.ac.uk/calice/

The CALICE collaboration

5 February 2003 Paul Dauncey - Calice Status 3

Major aim is beam test• ECAL 202020cm3

• 30 layers of tungsten• 9720 Si diode pads with

analogue readout

• HCAL 111m3

• 38 layers of iron• 15000 55cm2

scintillator pads with analogue readout, OR

• 350000 11cm2 RPC, scintillator or GEM pads with digital readout

• Timescale is short• mid 2004 – mid 2005

CALICE beam test

5 February 2003 Paul Dauncey - Calice Status 4

UK project (finally!) approved in Dec 2002• Funding only for two full FY’s, not the three requested

• Funds up to March 2005; cannot complete beam test or do analysis!• Can reapply to extend in ~18 months

• Equipment fund sufficient to build ECAL electronics• We will design and build VME boards and DAQ system for beam test• Hope to use same boards for HCAL readout (analogue and digital)

• Full effort request granted for engineering from Rutherford Laboratory

• New engineer (Adam Baird, RAL) has now joined the project

• One RA post for two years at Cambridge• For simulation work, the other part of the UK involvement

• Travel money for the two FY’s

CALICE-UK approval

5 February 2003 Paul Dauncey - Calice Status 5

Two sets of studies going on• Jet resolution is major driver for fine-grained calorimetry

• Simulation indicates required 30%/E is achievable using energy flow…• …but simulation needs to be verified• Hadronic interactions known to be difficult to model• Compare Geant3/Geant4/Fluka predictions• Birmingham and Cambridge groups

• Beam energy spread will be significant• Luminosity will need to be known as a function of s• Bhabha rate is high and (obviously) depends directly on luminosity• Measure s for each event from acollinearity angle of e+ and e–

• Could use tracker only but need very high efficiency at low angles• UCL group

CALICE-UK simulation studies

5 February 2003 Paul Dauncey - Calice Status 6

Expect EM response to be modelled well

• Use beam test configuration for studies

• Direct comparison to data when available

• Agreement is reasonable after tuning

• Low energy cut-offs• Production of -rays

Geant3/Geant4 electron comparisons

5 February 2003 Paul Dauncey - Calice Status 7

Did not expect hadronic response to be as good

• Pion beam agreement also pretty reasonable after same tuning

• Comparable to (better than?) electrons

Geant3/Geant4 pion comparisons

5 February 2003 Paul Dauncey - Calice Status 8

Protons show much worse agreement

• Small nucleon component in all jets

• Causes almost all of small discrepancy in pion jets

• Importance of using proton test beam

• Not previously recognised

Data may be different from both models!

Geant3/Geant4 proton comparisons

5 February 2003 Paul Dauncey - Calice Status 9

• Effort from several groups in ECAL readout electronics• Imperial, Manchester, UCL

• Following approval, RAL TD became involved; brought experience of CMS tracker

• Significant knowledge of design of Front End Driver (FED)• Readout board for CMS silicon tracker• Around 500 boards needed for whole tracking system

• FED architecture close to proposed CALICE board• Data gathering and control almost identical• Actual data input technology very different; CMS use fibre

• FED design is quite advanced• Physical board layout complete, firmware designs in progress• Two “final-specification” prototypes received two weeks ago and currently

undergoing tests

Will now use FED as a starting point for CALICE

CALICE-UK electronics work

5 February 2003 Paul Dauncey - Calice Status 10

Original proposed system

15 readout boards• Each handles digitisation of 2 layers

1 trigger board• Holds off further triggers until readout

complete

1 test board (not shown)• For testing cable connections of readout

board

Readout board most complex part• Each cable handled by slave

FPGA• Whole board controlled by master

FPGA

5 February 2003 Paul Dauncey - Calice Status 11

FED board compared to readout board

0V

Front End FPGA

12x Opto RxP

D A

rra

y4x

Prog

Delay

1

Synch &Processing

TTCrx

VME

QDR SSRAM2

5V 3.3V 1.5VDualADC

3.3V

DualADC

1

6

0V

Front End FPGA

12x Opto Rx

PD

Arr

ay

Synch &Processing

8 DualADC

DualADC

43

48

Readout &Synch Control

ASIC

ASIC

ASIC

FPGA

12

11

TempSense

TempSense

4x Prog

Delay

FPGA

1

3

4x Prog

Delay

FPGA

4x Prog

Delay

FPGA

22

24

TempSense

3.3V1.5V5V

-5V

spare

PD

Boundary Scan

SystemACE

E-FuseHot

swapDC-DC

Back End FPGA

TempSense

12x trim dac

12x trim dac

BufferJumper

Matrix

Compa

ct Flas

h

VME64xInterfaceFPG

A

Test Connector

SWSW

Hot swap cycle

Live extract reques

t

Config

E2PROMVr

ef

DAQTTS

Spare

1.5V

3.3 V5.0 V

2.5V

-5.0V

2.5V

96

85

Vref

1.5V

Run/Halt

VMEPower Good

LE

D s

extract

IdE2 Prom

FLT

LE

D s

FSYNC

Readout

+12V

LE

D s+5V+3.3V

FE 1

FE 8

EMU

LE

D sProcessTransfer

+2.5V

LE

D s+1.5V-5.0V

halted LE

D sBusyerror

TTC

Over temp

LE

D s

VME

ClockControl

Data

ClockControl

Data

8 3.3V1.5V

Master BE +VME; very similar

Slave FE; need to rewrite firmware

ADCs, etc; totally different

5 February 2003 Paul Dauncey - Calice Status 12

• Ideally• Keep everything

to the right• Redo everything

to the left

• FED is bigger• More £ per

board• More channels

per board also

• Total cost approximately the same

• Saving is on schedule and effort

FED layout

5 February 2003 Paul Dauncey - Calice Status 13

ECAL electronics schedule

J F M A M J J A S O N D J F M A M

Prototype 2 boards

Design

Layout

Fabrication and assembly

Testing, including VFE prototype tests

Production 9 boards

Redesign

Layout

Fabrication and assembly

Testing

2003 2004

5 February 2003 Paul Dauncey - Calice Status 14

• CALICE as a whole is still growing• Dominating the LC calorimetry community

• CALICE-UK is finally approved• Not everything we wanted (yet)• Will keep us going for the next two years

• Simulation studies producing useful results• Indicating the importance of proton beams• Ensures beam test will be sensitive to most critical issues

• Electronics getting close to producing hardware• Now based on CMS FED board; cost neutral but less effort needed• Should have prototypes this summer, final boards early in 2004

CALICE summary