Integrated Circuit Design for High-Speed Frequency Synthesis

John Rogers Calvin Plett Foster Dai

ARTECH H O US E BOSTON|LONDON a r t e c h h o u s e . c o m

Preface XI

CHAPTER 1 Introduction 1 1.1 Introduction to Frequency Synthesis 1 1.2 Frequency Synthesis for Telecommunications Systems 1 1.3 Frequency Synthesis for Digital Circuit Applications 5 1.4 Frequency Synthesis for Clock and Data Recovery 8 1.5 Frequency Synthesis for Modulation and Waveform Generation 11 1.6 Overview 13

References 14

CHAPTER 2 Synthesizer Architectures 1 7 2.1 Introduction yj 2.2 Integer-N PLL Synthesizers 17 2.3 Fractional-N PLL Frequency Synthesizers 18

2.3.1 Fractional-N Synthesizer with Dual-Modulus Prescaler 19 2.3.2 An Accumulator with Programmable Size 21 2.3.3 Fractional-N Synthesizer with Multimodulus Divider 23 2.3.4 Fractional-N Spurious Components 24

2.4 Delay-Locked Loops 27 2.5 Clock and Data Recovery (CDR) PLLs 29 2.6 Direct Digital Synthesizers 31

2.6.1 Direct Digital Synthesizer with Read-Only Memory Lookup Table 32 2.6.2 ROM-Less Direct Digital Synthesizer 33

2.7 Direct Analog Frequency Synthesizers 33 2.8 Hybrid Frequency Synthesizers 34

References 3 g

CHAPTER3 System-Level Overview of PLL-Based Frequency Synthesis 43 3.1 Introduction 43 3.2 PLLs (Example of a Feedback System) 43 3.3 PLL Components 44

3.3.1 VCOs and Dividers 44 3.3.2 Phase Detectors 4g 3.3.3 The Loop Filter 51

Contents

3.4 Continuous-Time Analysis for PLL Synthesizers 52 3.4.1 Simplified Loop Equations 53 3.4.2 PLL System Frequency Response and Bandwidth 55 3.4.3 Complete Loop Transfer Function, Including C2 56

3.5 Discrete-Time Analysis for PLL Synthesizers 58 3.6 Transient Behavior of PLLs 61

3.6.1 Linear Transient Behavior 62 3.6.2 Nonlinear Transient Behavior 66

3.7 Phase Noise and Timing Jitter in PLL Synthesis 71 3.7.1 Various Noise Sources in PLL Synthesizers 75 3.7.2 In-Band and Out-of-Band Phase Noise in PLL Synthesis 78 References 83

CHAPTER 4 Introduction to Digital IC Design 85 4.1 Digital Design Methodology and Flow 85 4.2 VerilogHDL 88

4.2.1 Verilog Program Structure 89 4.2.2 Verilog Data Formats 94 4.2.3 Verilog Operators 95 4.2.4 Verilog Control Constructs 95 4.2.5 Blocking and Nonblocking Assignments 97 4.2.6 Tasks and Functions 99

4.3 Behavioral and Structural Modeling 101 4.4 Combinational Digital Circuit Design 102 4.5 Sequential Digital Circuit Design 103 4.6 Digital Design Example I: A Multimodulus Divider 106 4.7 Digital Design Example II: A Programmable MASH A2 Modulator 109

4.7.1 MASH SA Modulator Top-Level Structure 110 4.7.2 Fractional Accumulator with Programmable Size and Seed-

Loading Capability 114 4.7.3 Reset Synchronization 116 4.7.4 Simulated Results 117 References 118

CHAPTER 5 CMOS Logic and Current Mode Logic 119 5.1 Introduction 119 5.2 CMOS Logic Circuits 120 5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs 121 5.4 Effect of Capacitance on Slew Rate 125 5.5 Trade-Off Between Power Consumption and Speed 129 5.6 CML Combinational Circuits 132 5.7 CML Sequential Circuits 134 5.8 Master-Slave D-Flip-Flop 139 5.9 CML Circuit-Delay Analysis 142

Contents VII

5.10 Low-Power CML Circuits 144 5.11 CML Biasing Circuits 146 5.12 Driver Circuits 150

References 152

CHAPTER 6 Dividers and Phase-Frequency Detectors 153 6.1 Introduction 153 6.2 Dividers 153

6.2.1 A Static Divide-by-Two Circuit 155 6.2.2 Programmable Divide-by-Two or Divide-by-Three Circuit 158 6.2.3 A 50% Duty Cycle, High-Speed, Divide-by-Three Circuit 163 6.2.4 A Multimodulus Divider 165 6.2.5 A Generic MMD Architecture 170 6.2.6 Pulse-Swallow Dividers 175

6.3 Multipliers 180 6.4 Phase Detectors 181

6.4.1 Basic Types of Phase Detectors 181 6.4.2 Circuit Implementations of PFDs 183 6.4.3 Dead Zone in PFDs 186 6.4.4 Lock-Detection Circuits 189 6.4.5 A Modified PFD with Aligned UP and DN Pulses 190 6.4.6 PFDs for CDR Applications 191 References 196

CHAPTER 7 Charge Pumps and Loop Filters 199 7.1 Introduction 199 7.2 Charge Pumps 199

7.2.1 A Basic Charge Pump 199 7.2.2 Saturation Voltage 200 7.2.3 Current Source Output Impedance 201 7.2.4 Reference Feedthrough 203 7.2.5 Transistor Gain Considerations 206 7.2.6 Charge Pump Noise 207 7.2.7 Charge Sharing 209 7.2.8 Improving Matching Between Ip and In 209 7.2.9 Charge Pumps Compatible with CML/ECL 211 7.2.10 A Differential Charge Pump 215 7.2.11 Common-Mode Feedback for a Differential Charge Pump 217 7.2.12 Another Differential Charge Pump 217 7.2.13 Programmable Bias Schemes 218

7.3 Loop Filters 218 7.3.1 Passive Loop Filters 219 7.3.2 Active Loop Filters 222 7.3.3 LC Loop Filters 224 References 230