508160 davinci evm e - spectrum...

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SPECTRUM DIGITAL INCORPORATED

508162-0001

Wednesday, March 14, 2007 1 35

B

TMS320DM6446 EVALUATION MODULE

Title Block

SCHEMATIC CONTENTS01 DAVINCI EVM TITLE SHEET 02 DAVINCI EVM BLOCK DIAGRAM 03 DAVINCI EMIF INTERFACE04 DAVINCI DDR INTERFACE05 DAVINCI VIDEO INTERFACE06 DAVINCI I/O INTERFACE07 DAVINCI USB & SD/MMC/MS CONTROLLER08 DAVINCI EMULATION & CLOCKS09 DAVINCI POWER PINS10 DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS

11 DDR2 MEMORY12 SRAM/NAND FLASH13 NOR FLASH14 EMIF LEVEL SHIFTER 15 EMIF CPLD MULTIPLEXER16 SD/MMC/MS CONNECTOR17 SM/xD CONNECTOR18 ATA INTERFACE19 COMPACT FLASH CONNECTOR20 RS232 INTERFACE

21 USB 2.0 INTERFACE22 ETHERNET INTERFACE23 TVP5146 LEVEL SHIFTER24 TVP5416 VIDEO DECODER 25 VIDEO OUT26 AIC33 AUDIO INTERFACE27 SPDIF OUTPUTS & USER LEDS28 MSP430 & IR INTERFACE29 EMIF EXPANSION CONNECTOR30 VIDEO INPUT/OUTPUT CONNECTORS

31 EMAC/GIO & McBSP/SPI & SD CONNECTORS32 VLYNQ CONNECTOR33 DAVINCI EMULATION HEADER34 POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC35 POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONNECTOR

REV

ENGR

2

REVISION STATUS OF SHEETS

1

11

SH

DATE

14 12 13

DATE

ENGR-MGR

MFG

7

DWN

DATE8

DATE

10

SH

DATE

CHK

RLSE

APPLICATION

REV

3 5

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

15

E E E E E E E

EEEEE

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

02/17/2005

02/17/2005

16 17 18 19 20

21 22 23 24 25 02/17/2005

02/17/2005

03/01/2004

02/17/2005

02/17/2005

REV

SH

E E E E E

E E E

E E E

E E E E E

E E E E

26 27 28 29 30

EE

31 32 33 34

A Initial schematic ready for layout - Alpha Release

DESCRIPTIONREV APPROVEDDATE

02/17/05 RRP

4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESSOTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATEDCIRCUITS THEY SHOULD BE PLACED NEAR.

NOTES, UNLESS OTHERWISE SPECIFIED:

1. RESISTANCE VALUES IN OHMS.

2. CAPACTITANCE VALUES IN MICROFARADS.

3. REFERENCE DESIGNATORS USED:

5. OBSERVE THE FOLLOWING LAYOUT NOTES:

1. TOP - SIGNAL ROUTING2. GROUND PLANE3. INNER1 - SIGNAL ROUTING4. VCC3 PLANE (3.3V BOARD)5. INNER2 - SIGNAL ROUTING6. INNER3 - SIGNAL ROUTING7. VCC PLANE 28. INNER4 - SIGNAL ROUTING9. GROUND PLANE10. BOTTOM - SIGNAL ROUTING

6. BOARD PROPERTIES

B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE

C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATINGD. INNER LAYERS 1.0 OZ CUE. FR4 BOARD MATERIALF. MINIMUM TRACE WIDTH/SPACING 4 MILSG. MINIMUM VIA SIZE 10/19 MILH. LAYER STACKUP:

A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE

B2. USB layer 90 ohm differential

35

E

B Beta Release RRP09/27/05

I2C ADDRESS TABLE

IO EXPANDER 0

IO EXPANDER 1

IO EXPANDER 2

I2C ROM

AIC33

TVP5146

MSP430

0x50

BASE

0x1B

0x5D

0x23

0x38 (LED)

0x39 (PLL/USER_SW)

0x3A (USB/CD_RESET)

SHEET

26

24

28

28

28

28

6

C Gamma Release RRP10/28/05

D Production Release 02/18/06 RRP

E Production Update - DM6446 symbol updated to current Data Sheet 02/18/07 RRP

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508162-0001


B


DAVINCI BLOCK DIAGRAM

DaVinciSH:3-9

DDR2 IFSH:4

SH:12NAND Flash (64MB)

SH:13NOR Flash (16MB)

SH:12SRAM (4MB)

SH:14Switch

SH:32VLYNQ Connector

SH:16SD/MMC/MS Connector

SH:25(4) DAC Video Outputs

SH:30DC #5 Connector


SH:27SPDIF Outputs

SH:7Switch

SH:26

Stereo Codec (AIC33)



SH:5

VCXO/PLL (Audio & VideoClock Generation)

SH:17SMC/xD Connector

SH:19Compact Flash Connector

SH:14,15

1.8V to 3.3VLevel Shifters

SH:18ATA Connector

SH:33Emulator Header


SH:11DDR2 SDRAM (256MB)

SH:21USB 2.0 IF

SH:22Ethernet IF



SH:22Switch

SH:6EEPROM

SH:27(8) LEDs

SH:23

Level Shifter & Switch

SH:20

UART(Debug Term)

SH:24

Video Decoder (TVP5146)

SH:28

MSP430IR/RTC/SC

EmulatorSH:8

USB 2.0SH:7

Image InSH:5

UART1SH:3

I2CSH:6

SH:28

ResistorPop Option

SH:6

EMAC/GPIOs

UART0SH:6


Config Control & EM_CS2 Select

SH:10

Power Supply (3.3V)& System Reset Logic

SH:34

Power Supply (1.8V & DSP Core)& DC #7 Connector

SH:35

EMIF/VLYNQSH:3

SD/MMC/MSSH:7

(4) DACsSH:5

Video OutSH:5

PWM0SH:5

Timer InSH:8

PWM [2:1]SH:5

SPISH:6

McBSPSH:7

Power PinsSH:9

SH:8Crystal/Osc

SH:8

PLLs

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EM_D15

EM_D11

EM_D13

EM_D9

EM_D5

EM_D7

EM_D3

EM_D1

EM_A21

EM_A16

EM_A18

EM_A20

EM_A14

EM_A8

EM_A6

EM_A10

EM_A4

EM_A12

EM_A19

EM_A17

EM_A15

EM_A13

EM_A11

EM_A9

EM_A7

EM_A5

EM_A3

EM_D14

EM_D12

EM_D8

EM_D4

EM_D6

EM_D2

EM_D0

EM_D10

CPU.VLYNQ_CLK

VLYNQ_SCRUN

VLYNQ_CLK

VCC_1.8V

VCC_1.8V

EM_D[0:15] 12,13,14,29EM_A[3:21] 12,13,14,29

CLE_EM_A2 12,13,15,29ALE_EM_A1 12,13,15,29ATA2_EM_A0 12,13,15,29ATA1_EM_BA1 12,13,15,29

ATA_CS0 15,29ATA_CS1 15,29

READ_OE 12,13,15,29WRITE_WE 12,13,15,29

EM_CS2 10,15EM_CS3 29

ATA0_EM_BA0 15,29

INTRQ_EM_RNW15,29

UART_TXD1/DMACK 15

VLYNQ_CLK 32

VLYNQ_SCRUN 32

WAIT/BUSY15,29

INTRQ_EM_RNW 15,29

UART_RXD1/DMARQ 15

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508162-0001


B


DAVINCI EMIF INTERFACE

R1611K

R174 22

R168 22

R180 22

U28B

TMS320DM6446

EM_D14/DD14/HD14H5 EM_D13/DD13/HD13F2 EM_D12/DD12/HD12D1 EM_D11/DD11/HD11G4 EM_D10/DD10/HD10G5 EM_D09/DD09/HD09E2

EM_D15/DD15/HD15E1

EM_D08/DD08/HD08F3

EM_D07/DD07/HD07C1 EM_D06/DD06/HD06F4 EM_D05/DD05/HD05D2 EM_D04/DD04/HD04E4 EM_D03/DD03/HD03E3 EM_D02/DD02/HD02F5 EM_D01/DD01/HD01D3 EM_D00/DD00/HD00E5

EMRWn/INTRQ/HRWn G3

EM_WAIT/(RDY_BUSYn)/IORDYn/HRDYnF1

EM_OEn/REn/IORDn/DIORn/HDS1n H4EM_WEn/WEn/IOWRn/DIOWn/HDS2n G2

DMACK/UART_TXD1 H3DMARQ/UART_RXD1 G1

EM_CS5n/GPIO8/VLYNQ_CLOCK T1

EM_CS2n/HCSn C2EM_CS3n B1EM_CS4n/GPIO9/VLYNQ_SCRUN T2

EM_BA1/DA1/GPIO52 H2

EM_A2/(CLE)/HCNTL0 J1EM_A3/GPIO28 K2EM_A4/GPIO27 K4EM_A5/GPIO26 K3

EM_A6/GPIO25 N1EM_A7/GPIO24 N2EM_A8/GPIO23 N3EM_A9/GPIO22 M4EM_A10/GPIO21 P1EM_A11/GPIO20 P2EM_A12/GPIO19 R1EM_A13/GPIO18 N4

EM_A14/GPIO17/VLYNQ_RXD3 P4EM_A15/GPIO16/VLYNQ_TXD3 P3EM_A16/GPIO15/VLYNQ_RXD2 R5EM_A17/GPIO14/VLYNQ_TXD2 R2EM_A18/GPIO13/VLYNQ_RXD1 P5EM_A19/GPIO12/VLYNQ_TXD1 R4EM_A20/GPIO11/VLYNQ_RXD0 R3

EM_BA0/DA0/HINTn J3

GPIO52/ATA_CS0 J5GPIO51/ATA_CS1 H1

EM_A21/GPIO10/VLYNQ_TXD0 T3

EM_A1/(ALE)/HHWIL J2

EM_A0/DA2/HCNTL1/GPIO53 J4

R167 22

R173 22

RN9 RPACK8-10

12345678 9

10111213141516

RN3 RPACK8-10

12345678 9

10111213141516

C171

NO-POP

R170 22

R179 22

RN8 RPACK8-10

12345678 9

10111213141516

R171243

R394NO-POP

RN7 RPACK8-10

12345678 9

10111213141516

RN2 RPACK8-1012345678 9

10111213141516

C170

NO-POP

R175 22

R203 22

R169 22

R172 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_D8

DDR_D12

DDR_D14

DDR_D6

DDR_D25

DDR_D16

DDR_D26

DDR_D19

DDR_D21DDR_D20

DDR_D22DDR_D23

DDR_D28

DDR_D31

DDR_D27

DDR_D17

DDR_D29

DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5

DDR_D7

DDR_D9DDR_D10DDR_D11

DDR_D13

DDR_D15

DDR_D18

DDR_D24

DDR_D30

DDR_A0DDR_A1DDR_A2DDR_A3



DDR_A12DDR_BS00DDR_BS01DDR_BS02

DDR_CS

DDR_CLKDDR_CLK_N

DDR_DQS0

DDR_DQM0

DDR_DQS1DDR_DQS2DDR_DQS3

DDR_DQM3

BDDR_A0

BDDR_A3BDDR_A4BDDR_A5BDDR_A6BDDR_A7

BDDR_BS02BDDR_BS01BDDR_BS00

BDDR_A8BDDR_A9BDDR_A10BDDR_A11

BDDR_A12

BDDR_DQS0BDDR_DQS1BDDR_DQS2BDDR_DQS3

BDDR_DQM0BDDR_DQM1BDDR_DQM2BDDR_DQM3

BDDR_CS

BDDR_CLKBDDR_CLK_N

BDDR_CKE

DDR_DQM2DDR_DQM1

VREF_STL

BDDR_A1BDDR_A2

DDR_RAS

DDR_CKEDDR_WE

DDR_CAS

BDDR_WE

BDDR_RASBDDR_CAS

VCC_1.8V

DDR_D[0:31]11 DDR_A[0:12] 11

DDR_DQM0 11

DDR_DQS2 11

DDR_CAS 11

DDR_CLK 11

DDR_CS 11

DDR_CLK_N 11

DDR_WE 11DDR_RAS 11

DDR_CKE 11

DDR_DQS3 11

DDR_DQS1 11DDR_DQS0 11

DDR_DQM3 11

DDR_BS02 11DDR_BS01 11DDR_BS00 11

DDR_DQM1 11DDR_DQM2 11

VREF_STL11

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508162-0001


B


DAVINCI DDR INTERFACE

SURFACE MOUNT TEST POINT PADSUSED FOR VERIFYING DDR TIMINGS

ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN

PLACE RESISTOR BY DATA TERMINATOR PINSBALANCE LINE LENGTHS WITH DATA BYTES LENGTHS

R41 47

TP171

TP61

RN10 RPACK4-47

1234 5

678

L10

BLM21PG221SN1D1 2

R220 47

R53 0.22

R205 47

RN17 RPACK4-47

1234 5

678

R219 200

R221 47

R204 200

RN13RPACK4-47

12345

678

R206 47

TP40

1

R51 47

TP451

RN11RPACK4-47

1234 5

678

TP39

1

R181 47

R33 47

C2160.22uF

TP71

R52 47

R218 0

R182 47

TP381

RN12 RPACK4-47

1234 5

678

R32 47

C1901uF

C1890.1uF

U28A

TMS320DM6446

DDR_A00 W13DDR_A01 U13DDR_A02 V13DDR_A03 U12DDR_A04 V12DDR_A05 W12DDR_A06 W11DDR_A07 V11DDR_A08 V10DDR_A09 U11DDR_A10 U10DDR_A11 W10DDR_A12 W9

DDR_BS00 U8

DDR_CSn T9

DDR_CLK0n W8

DDR_WEn T8

DDR_CLK0 W7

DDR_CKE V8

DDR_ZP T13

DDR_ZN T12

DDR_VSSDLL T11

DDR_VDDDLL T10

DDR_CASn T7

DDR_RASn U7

DDR_D00U1DDR_D01U2DDR_D02V1DDR_D03V2DDR_D04W2DDR_D05U3DDR_D06V3DDR_D07W3

DDR_D08V4DDR_D09W4DDR_D010U5DDR_D11V5DDR_D12W5DDR_D13V6DDR_D14W6DDR_D15V7

DDR_D16W14DDR_D17V14DDR_D18W15DDR_D19V15DDR_D20U15DDR_D21W16DDR_D22V16DDR_D23T17

DDR_D24V17DDR_D25U17DDR_D26U18DDR_D27W17DDR_D28V18DDR_D29W18DDR_D30V19DDR_D31U19

DDR_BS01 V9DDR_BS02 U9

RSV7 R8

DDR_DQS0 U4DDR_DQS1 U6

DDR_DQM0 T4DDR_DQM1 T6

DDR_DQS3 U16DDR_DQS2 U14

DDR_DQM2 T14DDR_DQM3 T16

DDR_VREFT15

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AVREF_0.5V VREF_1.24V

VCC_1.8V

VCC_3.3V

VCC_1.8V

DSP_CORE_VDD

VCC_1.8V

VCC_1.8V

VCC_3.3V

VCC_3.3V

VCC_3.3VVCC_3.3V

VCC_3.3VCOUT0 10,30

COUT2 10,30

COUT4 30

YOUT0 10,30

YOUT2 10,30

VSYNC 30

COUT1 10,30

COUT3 10,30

HSYNC 30

YOUT1 10,30

YOUT3 10,30

COUT6 30COUT7 30

COUT5 30

YOUT5 30YOUT4 10,30

YOUT6 30YOUT7 30

VPBECLK 30

VCLK 30

PWM1 30

PWM2 30

HD23,30

VD23,30

CI530

CI730

CI430

CI630

CI330CI230CI130CI030

YI423,30

YI623,30

YI323,30

YI523,30

YI223,30YI123,30YI023,30

PCLK23,30

YI723,30

DAC_IOUTA 25

DAC_IOUTB 25

DAC_IOUTC 25

DAC_IOUTD 25

AUDIO_CLK 26,31

VID_CLK 30

3V3.DC_PCLK27

PLL.FS228PLL.FS128

PLL.SR28

PLL.CSEL28

CPLD_TIMER_IN 15

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508162-0001


B


DAVINCI VIDEO INTERFACE

VREF =1.24 VOLTS

R63 0.22

C310NO-POP

+ C7110 uF

U57SN74AUC1G1253

4

5

2

1

R297 33

R234 22

C3110.1uF

C231.001uF

R236 22

+C6510uF

U39

TLV431ADBV53

4

R62 0.22

R291 33

R366 33

R232 22

U28I

TMS320DM6446

CI7/CCD15/UART_RXD2N19CI6/CCD14/UART_TXD2N18CI5/CCD13/UART_CTS2N17CI4/CCD12/UART_RTS2N16CI3/CCD11N15CI2/CCD10M17CI1/CCD09M16CI0/CCD08M15

YI7/CCD07L18YI6/CCD06L17YI5/CCD05L16YI4/CCD04L15YI3/CCD03K19YI2/CCD02K18YI1/CCD01K17YI0/CCD00K16

PCLKM19

HDM18

VDL19

PWM2/B2/GPIO47 A15

PWM1/R2/GPIO46 B15

YOUT7/R7 E18YOUT6/R6 E17YOUT5/R5 E16

YOUT4/R4/AEAW4 E15YOUT3/R3/AEAW3 D18YOUT2/G7/AEAW2 D17YOUT1/G6/AEAW1 D16YOUT0/G5/AEAW0 D15

COUT7/G4 C16COUT6/G3 B19COUT5/G2 B18COUT4/B7 A18

COUT3/B6/DSP_BT B17COUT2/B5/EM_WIDTH A17

COUT1/B4/BTSEL1 B16COUT0/B3/BT_SEL0 A16

VCLK D19

VSYNC C18

HSYNC C17

VPBECLK C19

PWM0/GPIO45 C15

R301NO-POP

C266

0.1uF

TP67

1

RN18 RPACK8-33

12345678 9

10111213141516

C271NO-POP

TP54

1

R2421K

L22BLM21PG221SN1D

12 TP53

1C268

0.1uF

U55

PLL1705

VDD1 1VDD2 13

XT110

XT211

VDD3 20

VCC 8

DGND1 4DGND2 16SR7FS26FS15

SCKO1 19

AGND 9

DGND3 17

SCKO3 3

SCKO0 18

SCKO2 2

MCKO2 15MCKO1 14

CSEL12R293 NO-POP

Q12N3904

C273

100pF

TP55

1

R294 NO-POP

C265

0.1uF

R2404.99K

C230.1uF

C234.1uF

C269

0.1uF

RN21 RPACK8-33

12345678 9

10111213141516

R29610K

+C6610uF

R30010K

C31210pF

R194 22

R233 22

C2720.1uF

R292 33

R305 22.1K 1%

R29910K

C232.1uF

R3071K

R295 NO-POP

C2351uF

U28G

TMS320DM6446

DAC_IOUT_A P19

DAC_IOUT_B P18

DAC_IOUT_C R19

DAC_IOUT_D T19

VSSA_1P1VT18

VSSA_1P8VP17

DAC_VREF R17

VDDA_1P8VR18

DAC_RBIAS R16

VDDA_1P1VP16

R29810K

R2430

L21BLM21PG221SN1D1

2

R3042.2K

TP61

1

R241 7.5K

R239 4.02K

R216 22

C233.001uF

C267

0.1uF

R365 33

U56SN74AUC1G1253

4

5

2

1

R303 100K

R244NO-POP

R3020

R290 33

U54

PI6CX100-27W

X11 X2 8

GND4 VIN3 VDD 6CLKOUT 5

NC12 NC2 7

TP66

1

Y5

27MHz

C270

0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C_CLK

I2C_DATA

UART_RXD0UART_TXD0

3V3.I2C_CLK

3V3.I2C_DATA

1V8.MSP430_INT

VCC_1.8V

VCC_3.3V

VCC_3.3VVCC_3.3V

VCC_1.8V

VCC_1.8V

1V8.I2C_CLK 26,30,31

GIO3 30

GIO6 30

GIO0 30

GIO2 30

GIO5 30

GIO38 30

GIO4 30

GIO1 30

GIOV33_0 22,31

GIOV33_2 22,31

GIOV33_4 22,31

GIOV33_6 22,31

GIOV33_8 22,31

GIOV33_10 22,31

GIOV33_12 22,31

GIOV33_14 22,31

GIOV33_16 22,31

GIOV33_1 22,31

GIOV33_3 22,31

GIOV33_5 22,31

GIOV33_7 22,31

GIOV33_9 22,31

GIOV33_11 22,31

GIOV33_13 22,31

GIOV33_15 22,31

SPI_EN1 31

SPI_EN0 31

SPI_CLK 31

SPI_DI 31SPI_DO 31

3V3.I2C_CLK 24,27,28

3V3.I2C_DATA 24,27,28

UART_RXD0 20UART_TXD0 20

1V8.I2C_DATA 26,30,31

1V8.MSP430_INT15

ATA_DIR 15

Size:

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508162-0001


B


DAVINCI I/O INTERFACE

EEPROM ( 32KBytes )

R41010K

C1940.1uF

R2142.2K

R2112.2K

R42410K

R213100K

U28C

TMS320DM6446

GPIOV33_1/TXCLK A13GPIOV33_2/COL A12

GPIOV33_3/TXD0 B12

GPIOV33_13/RXER D10

GPIOV33_4/TXD1 D12GPIOV33_5/TXD2 A11GPIOV33_6/TXD3 C12GPIOV33_7/RXD0 E12

GPIOV33_14/CRS C10

GPIOV33_8/RXD1 C11GPIOV33_9/RXD2 B11

GPIOV33_10/RXD3 E11GPIOV33_11/RXCLK A10

GPIOV33_15/MDIO E10

GPIOV33_12/RXDV D11

GPIOV33_0/TXEN B13

GPIO0/LCD_OE C13GPIO1/C_WEn E13

GPIO2/G0 D13GPIO3/B0/LCD_FIELD C14

GPIO4/R0/C_FIELD B14GPIO5/G1 E14GPIO6/B1 A14

SDA/GPIO44 B4

GPIO38/R1 D14

SCL/GPIO43 C4

UART_TXD0/GPIO36 C5UART_RXD0/GPIO35 D5

SPI_DO/GPIO41 A2

SPI_EN0/GPIO37 A4

SPI_EN1/HDDIR/GPIO42 B2

SPI_CLK/GPIO39 A3

GPIO7 C3

GPIOV33_16/MDC B10

SPI_DI/GPIO40 B3

R2152.2K

R2122.2K

U34

24WC256

A01 VCC 8

VSS4 NC3 SCL 6SDA 5

A12 WP 7

VREF2

GND

VREF1

ENABLE

SCL1

SDA1

SCL2

SDA2

U33PCA9306

7

6

2

8

3

1

54R197 22

R201 22

C1950.1uF

RN14 RPACK4-22

1234 5

678

C1620.1uF

R198 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_3.3V

VCC_1.8V

VCC_3.3V

SD_CLK 16,31,32

SD_DATA0 16,31,32

SD_CMD 16,31,32

SD_DATA1 16,31,32

SD_DATA3 16,31,32SD_DATA2 16,31,32

CLKR 31

FSR 31

DR 31DX 27,31

FSX 31

CLKX 31

USB_ID 21

USB_VBUS 21

B_CLKR 26

B_FSR 26

B_DR 26B_DX 26

B_FSX 26

B_CLKX 26

McBSP_EN31

USB_DM 21

USB_DP 21

Size:

Date:

DWG NORevision:

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E


508162-0001


B


DAVINCI USB & SD/MMC/MMC CONTROLLER

Place C206 as close to device as possible, between 2 to 5 millimeters

U53 is a switch used for DC3 to allow the McBSPto be disconnected from on-board circuitry. Signal levels are at 1.8 Volt logic levels on both sides of switch

Place R217 as close to device as possible

C2061uF

C2110.01uF

TP47

1

+C5910uF

RN16 RPACK4-22

1234 5

678

C274

0.1uF

+C6010uF

U5374CBTLV3245

A12 B1 18A23 B2 17A34 B3 16A45 B4 15A56 B5 14A67 B6 13A78 B7 12A89 B8 11

G19NC1 VCC 20

GND 10

L15

BLM21PG221SN1D1 2

C2090.1uF

R60 0.22

U28H

TMS320DM6446

USB_VDDA3P3.1J19

USB_VSSA3P3.2J18

USB_VDD1P8H17

USB_VSS1P8H16

USB_DP G19

USB_ID J16

USB_VBUS J17

USB_VDDA1P2LDOG18

USB_VSSREF G16

USB_DM H19

USB_R1 H18

USB_VSSA1P2LDOG17

C2070.01uF

R309360

L13

BLM21PG221SN1D1 2

R30810K

R196 22

R61 0.22

R199 22

U28F

TMS320DM6446

FSX/GPIO31 C8

FSR/GPIO32 C7

CLKX/GPIO29 B8

CLKR/GPIO30 A8

DX/GPIO33 B7

DR/GPIO34 A7

SD_DATA1 E9

SD_DATA0 D8

SD_DATA2 D9

SD_DATA3 C9

SD_CMD B9

SD_CLK A9 R195 22

R200 22

TP48

1

TP46

1

R21710K

RN15

RPACK4-22

1234 5

678

TP49

1

C2120.1uF

VCC_1.8V

VCC_1.8VVCC_1.8V

VCC_1.8V

VCC_1.8V

DSP_CORE_VDD

DSP_EMU033

DSP_EMU133

DSP_TRST#33

DSP_TDO33

DSP_TDI33

DSP_TMS33

DSP_RTCK33

DSP_TCK33

TIMER_IN15

1.8V.SYS_RESETz13,15,26,29,30,31,34

CLKOUT0 29

Size:

Date:

DWG NORevision:

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508162-0001


B


DAVINCI EMULATION & CLOCKS

OPTIONAL OSCILLATOR POPULATION

CRYSTAL AND CAPS REMOVED WHENOSCILLATOR IS USED

TP20

1

TP8

1

R34 NO-POP

L5

NO-POP1 2

R35 0.22

C148NO-POP

R237 0

R178 NO-POP

C228 18 pF

TP18

1

L2

BLM21PG221SN1D1 2

U40

NO-POP/24 MHz

VCC4

OUT3 GND 2

EN 1

C140NO-POP

TP19

1

C227.1uF

EIA0402

C1371000pF

Y227MHz

C142NO-POP

C139 18pF

C229 18pF

L14

BLM21PG221SN1D1 2

C141.1uF

EIA0402C1380.1uF

R238NO-POP

U12

NO-POP/27 MHz

VCC4

OUT3 GND 2

EN 1

TP9

1

R177 0

TP10

1

R176NO-POP

L6

BLM21PG221SN1D1 2

C144 18pF

Y3

24MHz

R235 NO-POP

U28E

TMS320DM6446

TCKA6

TMSE6

TRSTnD7

TDIA5

TDOB5

EMU1C6

EMU0D6

RESETnL4

M24XO F19

M24VSS F17

M24XI F18

CLK_OUT1/TIM_IN/GPIO49 E19

CLK_OUT0/GPIO48 K1

RTCKB6

MXO M1

MXI/CLKIN L1

MXVSS L2

RSV24M3

RSV6L3

PLLVDD18M2

C1471uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_DSP_CORE_VDDIMX

CPU_VCC_3.3V

CPU_DSP_CORE_VDD

CPU_VCC_1.8V

CPU_VCC_1.8V

CPU_VCC_1.8V

CPU_VCC_1.8V

CPU_VCC_1.8V

CPU_DSP_CORE_VDDIMX

CPU_VCC_3.3V

CPU_DSP_CORE_VDD

VCC_3.3V

VCC_1.8V

DSP_CORE_VDD

DSP_CORE_VDDIMX

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


DAVINCI POWER PINS

+C130NO-POP

C169

0.1uF

+C3122uF

C204

0.1uF

C111

0.1uF

C199

0.1uF

C167

0.1uF

+C2922uF

+C4722uF

R42 0.025

C168

0.1uF

C186

0.1uF

R54 0.025

C181

0.1uF

C178

0.1uF

C201

0.1uF

+C125NO-POP

C210

0.1uF

TP421

C136

0.1uF

C205

0.1uF

C203

0.1uF

C115

0.1uF

C174

0.1uF

+C3022uF

TP22

1

+C2722uF

TP11

1

C146

0.1uF

C208

0.1uF

C187

0.1uF

C143

0.1uF

C183

0.1uF

C184

0.1uF

+C4922uF

C185

0.1uF

C134

0.1uF

R36 0.025

C202

0.1uF

C213

0.1uF

U28D

TMS320DM6446

DVDD18.1E7 DVDD18.2F6 DVDD18.3F8 DVDD18.4F14

M24VDDF16

DVDD18.5G7 DVDD18.6G9 DVDD18.7G15 DVDD18.8H6 DVDD18.9H14 DVDD18.10J7 DVDD18.11J15 DVDD18.12K6 DVDD18.13K14

MXVDDL5

DVDD18.14L7 DVDD18.15L13 DVDD18.16M6 DVDD18.17M14

CVDDDSP.1H8 CVDDDSP.2H10 CVDDDSP.3H11 CVDDDSP.4H12 CVDDDSP.5J9 CVDDDSP.6J10 CVDDDSP.7J11 CVDDDSP.8J13 CVDDDSP.9K8 CVDDDSP.10K9 CVDDDSP.11K11

CVDD.1F15 CVDD.2K10 CVDD.3K12 CVDD.4L8 CVDD.5L9 CVDD.6L10 CVDD.7L11

RSV2 A19

RSV5D4

VSS.19 K5VSS.20 K7VSS.21 K13VSS.22 K15VSS.23 L6VSS.24 L12VSS.25 L14VSS.26 M5VSS.27 M7VSS.28 M9VSS.29 M11VSS.30 M13VSS.31 N6VSS.32 N8VSS.33 N10VSS.34 N12VSS.35 N14VSS.36 P7VSS.37 P9VSS.38 P11VSS.39 P13VSS.40 P15VSS.41 R6VSS.42 R7VSS.43 R10VSS.44 R12

VSS.13 H13VSS.14 H15VSS.15 J6VSS.16 J8VSS.17 J12VSS.18 J14

VSS.1 E8VSS.2 F7VSS.3 F9

VSS.7 G11

VSS.9 G13

VSS.4 G6

VSS.8 G12

VSS.10 G14VSS.11 H7VSS.12 H9

DVDDR2.1N7 DVDDR2.2N9 DVDDR2.3N11 DVDDR2.4N13 DVDDR2.5P6 DVDDR2.6P8 DVDDR2.7P10 DVDDR2.8P12 DVDDR2.9P14 DVDDR2.10R9 DVDDR2.11R11 DVDDR2.12R13 DVDDR2.13R15

CVDD.8M8 CVDD.9M10 CVDD.10M12

DVDD33.1F10 DVDD33.2F11 DVDD33.3F12 DVDD33.4F13

VSS.5 G8VSS.6 G10

DVDD18.18N5

VSS.45 R14

RSV4 W19

DVDDR2.14T5

RSV1 A1RSV3 W1

C215

0.1uF

C177

0.1uF

C214

0.1uF

TP41

1

C182

0.1uF

+C4822uF

C175

0.1uF

C188

0.1uF

R37 0.025

R202 0

C145

0.1uF

C176

0.1uF

C179

0.1uF

TP30

1

+C2822uF

TP31

1

C135

0.1uF

TP32

1

+C4022uF

+C132NO-POP

C180

0.1uF

TP21

1

+ C127NO-POP

C113

0.1uF

C200

0.1uF

+C5822uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_1.8V

YOUT0 5,30YOUT1 5,30YOUT2 5,30YOUT3 5,30YOUT4 5,30

EM_CS23,15

NAND_CEz 12SRAM_CEz 12FLASH_CEz 13

DC_EM_CS2 29

COUT3 5,30COUT2 5,30COUT1 5,30COUT0 5,30

USER_SW 28

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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508162-0001


B


DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS

BOOT CONFIGURATION SWITCH

ONLY ONE DEVICE CAN BE SELECTED AT A TIME AT POWER UP.TO RECONFIGURE BOARD POWER DOWN EVM, CHANGE JUMPER TO DESIRED DEVICE.

11 = Boot from ROM (UART)

1 = GEM Self-Boots

PINS FUNCTION SWITCH S1

Selects ARM Boot Mode

BTSEL[1:0] 00 = Boot from ROM (NAND)

01 = Boot from AEM IF

10 = Boot from ROM (HPI)

Non-secure device

COUT[1:0]

MODE

Selects AEM IF CS2 Bus Width

8_16COUT2 0 = 8-bit

1 = 16-bit

S1-2=XXX S1-1=XXX

S1-3=XXX

S1-3=XXX

S1-2=XXX S1-1=XXX

S1-2=XXX S1-1=XXX

S1-2=XXX S1-1=XXX

COUT3 DSP_BT0 = ARM boots GEM S1-4=XXX

S1-4=XXX

YOUT[4:0] AEAW [4:0]

Address Bus Width

DSP BOOT

S1-5=XXX

S1-6=XXX

S1-7=XXX

S1-8=XXX

ALL ADDRESS LINES GPIO

S1-9=XXX

SPARE SWITCH

R229 1K

12345678910

S3

DIP_SWITCH-10

123456789

10

20191817161514131211

RN29 RPACK8-1K

12345678 9

10111213141516

R228NO-POP

RN28RPACK8-NO-POP

1 2 3 4 5 6 7 8910111213141516

R230 1K

J4

CONN 4x2

2468

1357

R22710K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A10

DDR_A8DDR_A7

DDR_A1

DDR_A9

DDR_A5

DDR_A0

DDR_A6

DDR_A2

DDR_A11DDR_A12

DDR_A3DDR_A4DDR_A4

DDR_A3

DDR_A12DDR_A11

DDR_A2

DDR_A6

DDR_A0

DDR_A5

DDR_A9

DDR_A1

DDR_A7DDR_A8

DDR_A10

DDR_BS00DDR_BS01DDR_BS02DDR_BS02

DDR_BS01DDR_BS00

DDR_CLK_NDDR_CLK

DDR_CS

DDR_CLKDDR_CLK_N

DDR_CAS

DDR_CKE

DDR_RASDDR_WE

DDR_DQS0

DDR_DQM0

DDR_DQS1

DDR_DQS2

DDR_DQM1DDR_DQM2DDR_DQM3

DDR_CS

DDR_RAS

DDR_CKE

DDR_CAS

DDR_WE

DDR_DQS3

VREF_STL

VREF_STL

DDR_D12DDR_D14

BDDR_D15BDDR_D14BDDR_D13BDDR_D12



BDDR_D3BDDR_D2BDDR_D1

BDDR_D14BDDR_D12

DDR_D28

DDR_D29

DDR_D30


BDDR_D27

BDDR_D28




BDDR_D29

BDDR_D30BDDR_D28

BDDR_D[16:31]

DDR_D2DDR_D0

BDDR_D2

BDDR_D0

BDDR_D0

DDR_D9DDR_D11BDDR_D11

BDDR_D9

DDR_D31DDR_D24

BDDR_D31BDDR_D24

BDDR_D13DDR_D15DDR_D13

BDDR_D15

DDR_D10DDR_D8

BDDR_D10BDDR_D8

DDR_D6DDR_D4

BDDR_D6BDDR_D4

DDR_D1DDR_D3

BDDR_D1BDDR_D3 BDDR_D17

BDDR_D19

BDDR_D20BDDR_D22

BDDR_D27BDDR_D25

DDR_D27DDR_D25

BDDR_D16BDDR_D18

DDR_D16DDR_D18

BDDR_D23

BDDR_D21

DDR_D23

DDR_D21

BDDR_D5BDDR_D7 DDR_D7

DDR_D5

BDDR_D26 DDR_D26

DDR_D17DDR_D19

DDR_D22DDR_D20

BDDR_D[0:15]

VCC_1.8V

VCC_1.8VVCC_1.8V

DDR_D[0:31]4

DDR_A[0:12]4

DDR_BS024DDR_BS014DDR_BS004

DDR_WE4DDR_CKE4

DDR_CLK4

DDR_RAS4

DDR_CLK_N4

DDR_CAS4DDR_CS4

DDR_DQM24DDR_DQM34

DDR_DQS24

DDR_DQS14

DDR_DQS04

DDR_DQM14DDR_DQM04

VREF_STL 4

DDR_DQS34

Size:

Date:

DWG NORevision:

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E


508162-0001

Thursday, March 08, 2007 11 35

B


DDR2 MEMORY

128 MEGABYTES 128 MEGABYTES

C1530.1uF

C156

0.1uF

C224

0.1uF

+ C1822 uF

+ C5722 uF + C102

NO-POP

RN5 RPACK4-47

1234 5

678

C154

0.1uF

R2071K 1%

RN19 RPACK4-471234 5

678

C2170.1uF

R1520

C2220.1uF

C2250.1uF

RN6 RPACK4-471234 5

678

C2200.1uF

RN30 RPACK4-47

1234 5

678

C152

0.1uF

RN20 RPACK4-471234 5

678

C150

0.1uF

C2180.1uF

C151

0.1uF

C2230.1uF

C2210.1uF

RN27 RPACK4-47

1234 5

678

C155

0.1uF

U32

MT47H64M16BT

A12V2A11U7A10R2A9U3A8U8A7U2A6T7A5T3

A4T8A3T2A2R7A1R3A0R8BA2P1BA1P3BA0P2

NC.1AA9NC.2AA8NC.3AA2NC.4AA1NC.5D2NC.6V8NC.7A9NC.8A8NC.9A2NC.10A1NC.11H2

RFU.1V3RFU.2V7ODTN9

CS#P8CAS#P7RAS#N7WE#N3CKEN2

CKM8CK#N8

UDQS#/NUD8UDQSE7LDQS#/NUH8LDQSJ7

UDME3LDMJ3

VDD.1 M9VDD.2 H1VDD.3 R9VDD.4 D1VDD.5 V1

VDDQ.1 F3VDDQ.2 F7VDDQ.3 K1VDDQ.4 K3VDDQ.5 K7VDDQ.6 K9VDDQ.7 D9VDDQ.8 F1VDDQ.9 F9

VDDQ.10 H9

VDDL M1

VREF M2

DQ15 E9DQ14 E1DQ13 G9DQ12 G1

DQ11 G3DQ10 G7DQ9 F2DQ8 F8

DQ7 J9DQ6 J1DQ5 L9DQ4 L1

DQ3 L3DQ2 L7DQ1 K2DQ0 K8

VSS.1 U9VSS.2 T1VSS.3 H3VSS.4 D3VSS.5 M3

VSSQ.1 G8VSSQ.2 J8VSSQ.3 D7VSSQ.4 J2VSSQ.5 E2VSSQ.6 L8VSSQ.7 L2VSSQ.8 E8VSSQ.9 H7

VSSQ.10 G2VSSDL M7

C157

0.1uF

U20

MT47H64M16BT

A12V2A11U7A10R2A9U3A8U8A7U2A6T7A5T3

A4T8A3T2A2R7A1R3A0R8BA2P1BA1P3BA0P2

NC.1AA9NC.2AA8NC.3AA2NC.4AA1NC.5D2NC.6V8NC.7A9NC.8A8NC.9A2NC.10A1NC.11H2

RFU.1V3RFU.2V7ODTN9

CS#P8CAS#P7RAS#N7WE#N3CKEN2

CKM8CK#N8

UDQS#/NUD8UDQSE7LDQS#/NUH8LDQSJ7

UDME3LDMJ3

VDD.1 M9VDD.2 H1VDD.3 R9VDD.4 D1VDD.5 V1

VDDQ.1 F3VDDQ.2 F7VDDQ.3 K1VDDQ.4 K3VDDQ.5 K7VDDQ.6 K9VDDQ.7 D9VDDQ.8 F1VDDQ.9 F9

VDDQ.10 H9

VDDL M1

VREF M2

DQ15 E9DQ14 E1DQ13 G9DQ12 G1

DQ11 G3DQ10 G7DQ9 F2DQ8 F8

DQ7 J9DQ6 J1DQ5 L9DQ4 L1

DQ3 L3DQ2 L7DQ1 K2DQ0 K8

VSS.1 U9VSS.2 T1VSS.3 H3VSS.4 D3VSS.5 M3

VSSQ.1 G8VSSQ.2 J8VSSQ.3 D7VSSQ.4 J2VSSQ.5 E2VSSQ.6 L8VSSQ.7 L2VSSQ.8 E8VSSQ.9 H7

VSSQ.10 G2VSSDL M7

R1510

RN31 RPACK4-47

1234 5

678

C2190.1uF

C149

0.1uF

RN26 RPACK4-471234 5

678

R2081K 1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EM_A7EM_A6

EM_A9

EM_A4

B.EM_A11B.EM_A10

EM_A5

EM_A8

EM_A3

B.EM_A16B.EM_A15

B.EM_A13B.EM_A12

B.EM_A17

B.EM_A14

B.EM_A19B.EM_A18

ATA2_EM_A0ATA1_EM_BA1

SRAM_CE2

EM_D2

EM_D8

EM_D5

EM_D0

EM_D2EM_D3EM_D4

EM_D4

EM_D14EM_D15

EM_D5

EM_D3

EM_D7

EM_D12

EM_D1

EM_D6

EM_D13

EM_D6

EM_D0

EM_D11EM_D10EM_D9

EM_D7

EM_D1

CLE_EM_A2

CLE_EM_A2

ALE_EM_A1

ALE_EM_A1

WRITE_WE

READ_OE

READ_OEWRITE_WE

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8V

EM_A[3:21]3,13,14,29

ATA2_EM_A03,13,15,29ALE_EM_A13,13,15,29

WRITE_WE3,13,15,29

CLE_EM_A23,13,15,29

SRAM_CEz10

ATA1_EM_BA13,13,15,29

READ_OE3,13,15,29

NAND_CEz10

EM_D[0:15] 3,13,14,29

NAND_BUSY15

B.EM_A[10:21]13,14,29

Size:

Date:

DWG NORevision:

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508162-0001


B


SRAM/NAND FLASH

SRAM ( 4MBytes )

NAND FLASH ( 64MBytes )

K9K1G08 supports 128 MEGABYTES

C92.1uF

R139NO-POP

R13810K

R1360

R113NO-POP

U7

SAMSUNG->K1S3216BCD

DQ16 G1

DQ1 B6DQ2 C5DQ3 C6DQ4 D5DQ5 E5DQ6 F5DQ7 F6DQ8 G6

DQ9 B1DQ10 C1DQ11 C2DQ12 D2DQ13 E2DQ14 F2DQ15 F1

A0A3 A1A4 A2A5 A3B3 A4B4 A5C3 A6C4 A7D4 A8H2 A9H3 A10H4 A11H5

VS

S.1

D1

VS

S.2

E6

CS1B5

WEG5OEA2

UBB2LBA1

A12G3 A13G4 A14F3 A15F4 A16E4 A17D3 A18H1 A19G2

VC

C.2

E1

VC

C.1

D6

NC.1 E3CS2A6

A20H6

R1340

C910.1uF

R13710K

C93.1uF

R14110K

R14010K

C900.1uF

R13510K

SAMSUNG K9K1208/Q/D/U/0C

U6

NC

.1B

1N

C.2

B4

NC

.3B

5N

C.4

B6

NC

.5C

1N

C.6

C2

R/BA6

REB2

CEA4

NC

.7C

3N

C.8

C4

VCC.1 F6

VSS.1 A3

NC

.20

E4

NC

.21

E5

CLEB3

ALEA2

WEA5

WPA1

NC

.19

E3

NC

.18

E2

NC

.17

E1

NC

.16

D6

NC

.15

D5

VSS.2 H1

I/O00 F2

NC

.9C

5

I/O01 G2

NC

.10

C6

I/O02 H2

NC

.11

D1

I/O03 H3

NC

.12

D2

NC

.14

D4

NC

.22

F1

NC

.13

D3

VCC.2 G4

LOCKPREE6

NC

.23

F3

I/O04 H4

NC

.25

F5

I/O05 G5

NC

.24

F4

I/O06 H5I/O07 G6

VSS.3 H6

NC

.26

G1

NC

.27

G3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EM_D3

EM_D8

WRITE_WEREAD_OE

EM_D6

1.8V.SYS_RESETz

FLASH_CEz

EM_D5

EM_D7

EM_D0EM_D1EM_D2

EM_D4

EM_D9EM_D10EM_D11

EM_D13EM_D12

EM_D14EM_D15

ATA1_EM_BA1ATA2_EM_A0ALE_EM_A1CLE_EM_A2

B.EM_A21

EM_WPn

B.EM_A18

EM_A8EM_A9

EM_A7

B.EM_A19

EM_A6

EM_A4

B.EM_A15

B.EM_A12B.EM_A11

B.EM_A17

EM_A3

B.EM_A13

B.EM_A10

B.EM_A16

B.EM_A14

EM_A5

B.EM_A20

EM_D1EM_D0

EM_D3EM_D2

EM_D6

EM_D4EM_D5

EM_D8EM_D9

EM_D7

EM_D10EM_D11

EM_D13EM_D12

EM_D15EM_D14

ATA1_EM_BA1

EM_A4

B.EM_A21B.EM_A20B.EM_A19B.EM_A18B.EM_A17B.EM_A16B.EM_A15B.EM_A14B.EM_A13B.EM_A12B.EM_A11B.EM_A10EM_A9EM_A8EM_A7EM_A6EM_A5

ATA2_EM_A0ALE_EM_A1CLE_EM_A2EM_A3

WRITE_WE

1.8V.SYS_RESETz

EM_WPn

FLASH_CEzREAD_OE

VCC_1.8V

VCC_1.8V

VCC_3.3V

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8V

EM_D[0:15] 3,12,14,29

FLASH_CEz10

ATA1_EM_BA13,12,15,29

EM_A[3:21]3,12,14,29

ATA2_EM_A03,12,15,29ALE_EM_A13,12,15,29CLE_EM_A23,12,15,29

WRITE_WE3,12,15,29READ_OE3,12,15,29

1.8V.SYS_RESETz8,15,26,29,30,31,34

B.EM_A[10:21]12,14,29

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


NOR FLASH

16 MBytes

R14210K

U13 NO-POP/AM29LV256M

A031A126A225A324A423A522A621A720A810A99A108A117A126A135A144A153A1654

BYTE53

CE32OE34

RESET14

WE13

VCC 43

VSS1 33VSS2 52

RY/BY 17

DQ15/A-1 51

DQ0 35DQ1 37DQ2 39DQ3 41DQ4 44DQ5 46DQ6 48DQ7 50DQ8 36DQ9 38

DQ10 40DQ11 42DQ12 45DQ13 47DQ14 49

A1719A1818A1911A2012A2115A222A231

NC1 27NC2 28NC3 30NC4 55NC5 56

WP/ACC16

VIO 29

R116NO-POP

R11510K

R14310K

C165.1uF

C94.1uF

C172.1uF

C166.1uF

C120.1uF

UX13

PC28F128P30T85

A1A1A2B1A3C1A4D1A5D2A6A2A7C2A8A3A9B3A10C3A11D3A12C4A13A5A14B5A15C5A16D7A17D8A18A7A19B7A20C7

D0 F2D1 E2D2 G3D3 E4D4 E5D5 G5D6 G6D7 H7D8 E1D9 E3

D10 F3D11 F4D12 F5D13 H5D14 G7D15 E7

VSS.3 H2

VSS.1 B2VSS.2 H4

CEB4OEF8

WEG8

RSTnD4

WPnC6

A21C8

CLKE6

ADVF6

WAIT F7

A22A8A23G1NC/A24H8

VCC.1 H3VCC.2 A6

VCCQ.1 D5

VSS.4 H6

VCCQ.3 D6

VPP A4

RFU.3 G2RFU.2 H1RFU.1 F1

NC/A25B6

VCCQ.2 G4

RFU.5 E8RFU.4 B8

C173.1uF

R11410K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VLYNQ_RXD3VLYNQ_RXD2

EM_A12

EM_A10EM_A11

B.EM_A16

B.EM_A20B.EM_A15B.EM_A17

B.EM_A18

B.EM_A19B.EM_A21

B.EM_A14

EM_A18

EM_A21

EM_A17EM_A19

EM_A15

EM_A16EM_A14

EM_A20

B.VLNQ_TXD0B.VLNQ_TXD1B.VLNQ_TXD2B.VLNQ_TXD3

VLYNQ_TXD1VLYNQ_TXD2

VLYNQ_TXD0

VLYNQ_TXD3

EM_A13

B.EM_A10

B.EM_A13

B.EM_A11B.EM_A12


3V3.EM_D153V3.EM_D143V3.EM_D133V3.EM_D123V3.EM_D113V3.EM_D103V3.EM_D93V3.EM_D8


EM_D15EM_D14EM_D13EM_D12EM_D11EM_D10EM_D9EM_D8

EM_D7EM_D6EM_D5EM_D4EM_D3EM_D2EM_D1EM_D0

VCC_3.3V

VCC_3.3V

VCC_3.3VVCC_1.8V

VLYNQ_ONz28EM_A[3:21]3,12,13,29

VLYNQ_RXD032VLYNQ_RXD132VLYNQ_RXD232VLYNQ_RXD332

SLP_CLK_EN 32ELP_REQ/WAKEUP 32PM_EN 32

WLAN_INTR 32

B.EM_A[10:21] 12,13,29

VLYNQ_TXD3 32

VLYNQ_TXD1 32VLYNQ_TXD2 32

VLYNQ_TXD0 32

3V3.EM_D[0:15] 17,18,19

EM_D[0:15]3,12,13,29

1V8.EM_DATA_BUF_EN151V8.EM_DATA_BUF_DIR15

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


EMIF LEVEL SHIFTER

U11 is a switch used to enable Vlynq functions.Signal levels are at 1.8 Volt logic levels on both sides of switch

L A TO B1

DIR BUS L B->A H B<-A

U8

SN74AVCB164245VR

1B121B231B351B461B581B691B7111B812

2B1132B2142B3162B4172B5192B6202B7222B823

1A1 471A2 461A3 441A4 431A5 411A6 401A7 381A8 37

2A1 362A2 352A3 332A4 322A5 302A6 292A7 272A8 26

1DIR11OEn48

2DIR242OEn25

VCCB7VCCB18 VCCA 42

VCCA 31

GND 28GND 34GND 39GND 45


C373

560pF

R393NO-POP

C1060.1uF

R418 22R417 22

C880.1uF

R392NO-POP

U11

SN74CBTLV16292DGGR

NC.1456

GN

D.2

19

1A2

11A25

1B1 54

1B2 53

GN

D.1

8V

CC

.117

GN

D.3

38G

ND

.449

NC.1355

2A43A64A95A116A137A158A189A2110A23

12A27

NC.13NC.25NC.37NC.410NC.512NC.614NC.716NC.820

S1

2B1 523B1 50

9B1 36

4B1 475B1 456B1 437B1 418B1 39

10B1 34

2B2 513B2 484B2 465B2 446B2 427B2 408B2 37

11B2 3112B2 29

NC.922NC.1024NC.1126NC.1228

11B1 3212B1 30

9B2 3510B2 33

C890.1uF

C119NO-POP

R412 22R413 22R414 22

R419 22

C1210.1uF

C1050.1uF

C117

5.6pF

C116

5.6pFR144 10K

R415 22

C118

NO-POP

R416 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ISR_TCK

ISR_TMS

ISR_TDO

ISR_TCKISR_TDOISR_TMS

ISR_TDI

ISR_TCK

ISR_TDOISR_TDI

DLOOP1

DLOOP2

DLOOP3

DLOOP4

DLOOP5

ISR_TMS

VCC_3.3VVCC_1.8V

VCC_3.3V VCC_3.3V

VCC_3.3V

VCC_1.8V

VCC_1.8VVCC_1.8V

VCC_3.3V

VCC_3.3V

3V3.SM_CEz28CFn_SEL28

3V3.CF_PWR_ON19,28

ATA_SEL28

1.8V.SYS_RESETz8,13,26,29,30,31,34

1V8.MSP430_INT6INTRQ_EM_RNW3,29

WAIT/BUSY3,29

ATA1_EM_BA13,12,13,29

ALE_EM_A13,12,13,29ATA2_EM_A03,12,13,29

CLE_EM_A23,12,13,29

WRITE_WE3,12,13,29READ_OE3,12,13,29

1V8.EM_DATA_BUF_DIR141V8.EM_DATA_BUF_EN14

3V3.ATA_BUFF_ENz 183V3.ATA_BUFF_DIR 18

ATA_DIR6

EM_CS23,10ATA_CS13,29ATA_CS03,29

UART_RXD1/DMARQ3UART_TXD1/DMACK3

ATA0_EM_BA03,29

3V3.ATA_RESETn 18

3V3.ATA.WAIT/BUSY 18

3V3.ATA.DMARQ 183V3.ATA.INTRQ_EM_RNW 18

3V3.ATA.DIOW 18

3V3.ATA.CS0 18

3V3.ATA.DIOR 183V3.ATA.DA0 183V3.ATA.DA1 183V3.ATA.DMACK 18

3V3.ATA.CS1 183V3.ATA.DA2 18

MSP430_INT 283V3.SYS_RESETz 22,24,28,31

3V3.SM.WAIT/BUSY 173V3.SM.SM_CEz 17

3V3.SM.WRITE_WE 173V3.SM.READ_OE 17

3V3.SM.ALE_EM_A1 173V3.SM.CLE_EM_A2 17

3V3.CF.ATA0_EM_BA0 193V3.CF.ATA1_EM_BA1 193V3.CF.ATA2_EM_A0 19

3V3.CF.READ_OE 193V3.CF.ATA_CS0 193V3.CF.ATA_CS1 19

3V3.CF.WRITE_WE 193V3.CF.WAIT/BUSY 19

3V3.CF.INTRQ_EM_RNW 19

3V3.UART_RXD1 28,313V3.UART_TXD1 28,31

SPAREIO3 28

SPAREIO2 28SPAREIO1 28

NAND_BUSY12

TIMER_IN8

TIMER_IN_DC331

CPLD_TIMER_IN 5

Size:

Date:

DWG NORevision:

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E


508162-0001


B


EMIF DATA BUS LEVEL SHIFTER

CPLD REVISION 508163-0001B

L63

BLM41P750SPT

C1040.1uF

R310K

RN24

RPACK4-10K

1234 5

678

C1090.1uF

C1290.1uF

R165 0

C1310.1uF

C1280.1uF

U14

EPM240GTC100

B1.PIN22B1.PIN33

TDI.B123

B1.PIN44

B1.PIN66B1.PIN77B1.PIN88

B1.

VC

CIO

1A9

GN

DIO

110

GN

DIN

TA11

B1.GCLK012V

CC

INT1

13

B1.GCLK114

TMS.B122

B1.PIN1616B1.PIN1717B1.PIN1818B1.PIN1919B1.PIN2020B1.PIN2121

B1.PIN2727 B1.PIN2626

B1.PIN2828B1.PIN2929B1.PIN3030

B1.

VC

CIO

1B31

B1.PIN3333B1.PIN3434B1.PIN3535B1.PIN3636B1.PIN3737


B1.DEV_OE43B1.DEV_CLRn44

B1.

VC

CIO

1C45

GN

DIO

346


B2.PIN52 52

GN

DIO

232

B2.PIN54 54B2.PIN55 55

B2.PIN57 57B2.PIN58 58

B2.

VC

CIO

1A59

GN

DIO

460

B2.PIN61 61

TCK.B124

VC

CIN

T263

B2.PIN66 66

GN

DIN

TB65

B2.PIN67 67B2.PIN68 68B2.PIN69 69B2.PIN70 70B2.PIN71 71B2.PIN72 72

TDO.B125

B2.PIN73 73

B2.PIN76 76B2.PIN77 77

GN

DIO

579

B2.

VC

CIO

1B80

B2.PIN81 81

B2.PIN83 83

B2.PIN84 84B2.PIN85 85

B2.GCLK3 64B2.GCLK2 62

B2.PIN86 86

GN

DIO

693

B2.

VC

CIO

1C94

B2.PIN96 96B2.PIN97 97B2.PIN98 98B2.PIN99 99

B2.PIN100 100

B1.PIN55

B1.PIN1515

B2.PIN53 53

B2.PIN56 56

B2.PIN74 74B2.PIN75 75

B2.PIN78 78

B2.PIN82 82

B2.PIN87 87B2.PIN88 88B2.PIN89 89B2.PIN90 90B2.PIN91 91

B2.PIN92 92B2.PIN95 95

B2.PIN1 1

C1070.1uF

L62

NO-POP

R192 0

R40610K

R36933

R368 NO-POP

R19110K

C1260.1uF

J17

SMT FEMALE HEADER 5X2

1 23 45 67 89 10

C1080.1uF

R4310K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MS.CLKMS.DATA3

MS.DATA0

SD_DATA0

SD_CMD

SD_DATA1MS.CMD.BS

MS.DATA1

MS.DATA1

MS.DATA0MS.DATA2

MS.DATA2

SD_DATA2

MS.DATA3MS.CLK

SD_CLK

SD_DATA3

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

SD_DATA17,31,32

SD_DATA37,31,32SD_DATA27,31,32

SD_CLK7,31,32

SD_CMD7,31,32

SD_DATA07,31,32

SD/MMC.INS 28

MS.INS 28

SD/MMC.WP 28

Size:

Date:

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E


508162-0001


B


SD/MMC/MS CONNECTOR

SELECTS TERMINATION FOR SD/MMC/MS

WHEN USING DAT3 CARD DETECTIONPULL DOWN IS POPULATED WITH 470K OHMRESISTOR AND PULL UP IN NOT POPULATED

J5 TERMINATION

MEMORY STICK

MEMORY STICK PRO

MMC CARD

SD CARD

1-2

1-2

1-2

2-3

R12251K

J5

HEADER 3

123

R990

R121100K

R118NO-POP

+ C10

10uFR12651K

R119NO-POP

C95

0.1uF

R127 0

R12051K

R11751K

R7351K

J3SCDB2A101

SD.DAT31SD.CMD2SD.VSS13SD.VDD4SD.CLK5SD.VSS26SD.DAT07SD.DAT18

SD.DAT29

WP

20

CO

M22

INS

21

GN

D.1

23

MS.VSS1 10MS.BS 11MS.DATA1 12MS.SDIO/DATA0 13MS.DATA2 14MS.XINS 15MS.DATA3 16MS.SCLK 17MS.VCC 18MS.VSS2 19

U5

SN74LVC1G125 3

4

5

2

1

R10851K

R125NO-POP

R12451K

C78

.1uFR12351K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3.WRITE_WE3V3.ALE_EM_A1

3V3.SM_CEz

3V3.CLE_EM_A2

3V3.READ_OE3V3.WAIT/BUSY


SM.xD.WP

3V3.WRITE_WE3V3.ALE_EM_A1

3V3.READ_OE3V3.SM_CEz

3V3.WAIT/BUSY

3V3.CLE_EM_A2

SM.xD.WP


VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

3V3.SM.SM_CEz153V3.SM.READ_OE15

3V3.SM.WRITE_WE153V3.SM.ALE_EM_A1153V3.SM.CLE_EM_A215

3V3.EM_D[0:15]14,18,19

3V3.SM.WAIT/BUSY15

SM.CD 28

xD.CD 28

SM.xD.WP 28

Size:

Date:

DWG NORevision:

Sheet o f

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E


508162-0001


B


SM/xD CONNECTOR

Chant Sincere SM/xD Connector

J15

SM/xD_CONNECTOR

SM.I/O1SMC6SM.I/O2SMC7SM.I/O3SMC8SM.I/O4SMC9SM.I/O5SMC13SM.I/O6SMC14SM.I/O7SMC15SM.I/O8SMC16

SM.CLESMC2SM.ALESMC3SM.WESMC4SM.WPSMC5

SM.OPTIONSMC18

SM.R/BSMC19SM.RESMC20SM.CESMC21

xD.VCC2 XD20

SM

.VS

S1

SM

C1

SM

.VS

S2

SM

C10

SM

.LV

DS

MC

17

SM

.VC

C2

SM

C22

SM.CDSMC11

SM

.SE

NS

.1S

MC

SW

1

SM

.25

SM

CW

P1

SM

.26

SM

CW

P2

SM

.SE

NS

.2S

MC

SW

2

xD.CD XD1

xD.CLE XD5xD.ALE XD6xD.WE XD7xD.WP XD8

xD.R/B XD2xD.RE XD3xD.CE XD4

xD.VSS1 XD9xD.I/O0 XD10xD.I/O1 XD11xD.I/O2 XD12xD.I/O3 XD13xD.I/O4 XD14xD.I/O5 XD15xD.I/O6 XD16xD.I/O7 XD17

SM

.VC

C1

SM

C12

xD.VCC1 XD18

xD.VSS2 XD19

R10610K

R77NO-POP

R10710K

RN23

100K

12346 7 85

R7810K

R7610K

RN22

100K

1 2 3 4678 5

+ C910uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ATA_DASPn

ATA_CSEL

ATA.DD0ATA.DD1ATA.DD2ATA.DD3ATA.DD4ATA.DD5ATA.DD6ATA.DD7ATA.DD8ATA.DD9ATA.DD10ATA.DD11ATA.DD12ATA.DD13ATA.DD14ATA.DD15

3V3.EM_D4

3V3.EM_D63V3.EM_D5

3V3.EM_D23V3.EM_D13V3.EM_D0

3V3.EM_D3

3V3.EM_D7

3V3.EM_D15

3V3.EM_D93V3.EM_D103V3.EM_D113V3.EM_D12

3V3.EM_D8

3V3.EM_D133V3.EM_D14

ATA.DD0ATA.DD1ATA.DD2ATA.DD3ATA.DD4ATA.DD5ATA.DD6

ATA.DD7 ATA.DD8ATA.DD9ATA.DD10ATA.DD11ATA.DD12ATA.DD13ATA.DD14ATA.DD15

ATA.DD[0:15]

ATA.DA0ATA.DA1

ATA.DA2

ATA.DMACK

ATA.CS0 ATA.CS1

ATA.DIORATA.DIOW

ATA.DMARQ

ATA.INTRQ

ATA.DMARQ

ATA.IORDY

ATA.INTRQ

ATA_RESETn

ATA_RESETn

ATA.IORDY

ATA.CS1ATA.CS0

ATA.DIORATA.DIOW

ATA.DMACK

ATA.DA0

ATA.DA2ATA.DA1

VCC_5V

VCC_5V

VCC_5V

VCC_3.3V

VCC_3.3V

VCC_3.3VVCC_3.3V

VCC_3.3V

3V3.ATA.DA215

3V3.ATA.CS115

3V3.EM_D[0:15]14,17,19

3V3.ATA.DA0153V3.ATA.DA115

3V3.ATA.CS015

3V3.ATA.DIOR153V3.ATA.DIOW15

3V3.ATA.DMARQ 15

3V3.ATA.INTRQ_EM_RNW 15

3V3.ATA.WAIT/BUSY 15

3V3.ATA_RESETn15

3V3.ATA_BUFF_DIR15

3V3.ATA_BUFF_ENz15

3V3.ATA.DMACK15

Size:

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DWG NORevision:

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E


508162-0001


B


ATA INTERFACE

KEY

NC

IOCS16


MOUNTING HOLES

R57 33

R150 82

R48 33

C86.1uF

C87.1uF

Z8

1

Z71

R15820K

C103.1uF

R55 33

Z9

1

DS10

LED,GRN

R153 82

R56 33

R157 82

R11210K

TP33TEST POINT1R58 33

U9

SN74LVT16245B/SN74CB3Q16245

Vcc7Vcc18 Vcc 31Vcc 42

1A1 471A2 461A3 441A4 431A5 411A6 401A7 381A8 37

1B121B231B351B461B581B691B7111B812

2A1 362A2 352A3 332A4 322A5 302A6 292A7 272A8 26

2B1132B2142B3162B4172B5192B6202B7222B823

1OE 481DIR 12OE 252DIR 24


GND28GND34GND39GND45

R47 22R45 22

R1551K

R46 22

Z6

1

R156 33

RN1 RPACK8-3312345678 9

10111213141516

C101.1uF

R2232K

TP34TEST POINT1

R1485.6K

R15410K

R440

R401NO-POP

RN4 RPACK8-3312345678 9

10111213141516

JP1

HEADER 22X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 44

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CF_A2CF_A1CF_A0

3V3.EM_D153V3.EM_D143V3.EM_D133V3.EM_D123V3.EM_D113V3.EM_D103V3.EM_D93V3.EM_D83V3.EM_D73V3.EM_D63V3.EM_D53V3.EM_D43V3.EM_D33V3.EM_D23V3.EM_D13V3.EM_D0

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

3V3.CF_CD1 283V3.CF_CD2 28

3V3.EM_D[0:15] 14,17,18

3V3.CF_RESETz28

3V3.CF.WAIT/BUSY15

3V3.CF.ATA0_EM_BA0153V3.CF.ATA1_EM_BA115

3V3.CF.ATA2_EM_A0153V3.CF_PWR_ON15,28

3V3.CF.WRITE_WE15

3V3.CF.READ_OE15

3V3.CF.ATA_CS015

3V3.CF.ATA_CS115

3V3.CF.INTRQ_EM_RNW15

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


COMPACT FLASH CONNECTOR

R221K

R25

10K

R26

20K

R1102K

P1

Compact Flash Connector

GND1

D03 2D04 3D05 4D06 5D07 6

CE17

A108

OE9

A0910 A0811 A0712

VCC13

A0614 A0515 A0416 A0317 A0218 A0119 A0020 D00 21D01 22D02 23

WP24 CD2 25CD1 26

D11 27D12 28D13 29D14 30D15 31

CE232

VS1 33

IORD34

IOWR35

WE36

RDY/BSY37

VCC38

CSEL39

VS2 40RESET41

WAIT42

INPACK#43

REG44

BVD2 45BVD1 46

D08 47D09 48D10 49

GND50

R20100K

+C1610uF

R111 NO-POP

R240

C15.1uF

R2310K

R28100K

R270

R400NO-POP

U10

FDC6331L

VIN4 VOUT 3

VOUT 2

R1/C16

ON/OFF5

R2 1

R109100K

R21

20K

C17.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

S_A_TXD

S_A_RXDS_A_RXD

3V3.UART_RXD0

UART_TXD0 3V3.UART_TXD0

UART_RXD0

VCC_3.3V VCC_3.3V

VCC_3.3V

VCC_3.3VVCC_1.8V

VCC_3.3VVCC_1.8V

UART_TXD06

UART_RXD06

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


RS232 INTERFACE

L B-->A

H A-->B

DIR FUNCTION

C301.1uF

C243

.1uF

C300

10pF

R357

10

+ C3021uF

C295

10pF

U43

SN74AVC1T45

A1 3

VCCB6 VCCA 1

GND12

B14

DIR 5

+ C77

47uF

L54

BLM21PG221SN1D

1 2

C246.1uF

R35410K

L46 1uH

C297

10pF

U42

SN74AVC1T45

A1 3

VCCB6 VCCA 1

GND12

B14

DIR 5

R356 0

C245

.1uF

C244.1uF

+ C2991uF + C296

1uF

C294

10pF

L47 1uH

+ C2981uF

P6

DSUB9-Male

594837261

1011

L55

BLM21PG221SN1D

1 2

R35510K

U64 MAX3221

DIN11

INVALID10

ROUT9

C1+2

C1-4

V+3

VC

C15

GN

D14

V- 7

C2- 6

C2+ 5

RIN 8

ENABLE1

FORCEOFF 16

DOUT 13

FORCEON 12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_DP

USB_SHIELD

USB_DM

USB_SHIELD

USB_SHIELD

USB_SHIELD

USB_SHIELD

VCC_5V

VCC_5VVCC_3.3VVCC_5V

VCC_3.3V VCC_3.3V

USB_DM7USB_DP7

USB_VBUS7

USB_ID7

USB.DRVVBUSz28

GIOV33_1522,31

GIOV33_16

22,31

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


USB 2.0 INTERFACE

THESE FOOTPRINTS ARE OVERLAYED ONLY 1 OF 3 IS POPULATED AT 1 TIME

Selects Terminationfor Host/Clientconfigurations

MINI A-B CONNECTOR

FULL SIZE B CONNECTOR

FULL SIZE A CONNECTOR

For host mode Capacitor Minimum Capacitanceis 100uF, this design uses 104.7uFboth C133 and C69 installed. For Peripheral or OTG the Capacitancer should be 4.7 uF so remove R132 thus C69 provides capacitance

Q3

R425-R429

TP71-TP74

R3371.5K

R427NO-POP

J10A

USB-miniAB/A/B connector

VBUS1AB

D-2AB

D+3AB

GND5AB

SH

IELD

55

ID4AB

SH

IELD

66

SH

IELD

77

SH

IELD

88

R377100K

R166

10K

L53

BLM21PG221SN1D

1 2

R429

NO-POP

TP731

J10C


VBUS-A1A

D-2AD+3A

GND4A

SHIELD3 3

SHIELD4 4

+C133100uF

R43010K

R428NO-POP

U59SN74AHC1G08

1

24

53

TP601

Q3NO-POP

U15SN74LVC1G073

4

5

21

J10B


ATTACH1B

D-2BD+3B

GND4B

SHIELD1 1

SHIELD2 2

+C694.7uF

R133 0

D6 NO-POP

TP72

1

C351.1uF

R379

1K

C350.1uF

TP751

TP741

R3781K

J7

HEADER 3

123

S

D

G

Q2

IRLML6401

R132 0

C293

100nF

C3740.1uF

TP71

1

C197

1uF

TP761

L52

BLM21PG221SN1D

1 2

TP591

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LXT_RDM

LXT_

TDC

T

LXT_TDP

MII_RXDV

MII_CRS

XSPDO_MDIO

MII_RXD3

MII_RCLK

MII_TXCLK

RBIAS

MII_RDX2

MTXD3LXT_RDP_c

MII_RXD1

MTXEN

MTXD2MTXD1

LXT_RDM_c

MII_RXD0

MDINT_TP

MTXD0

PWRDWN

SLEEP

MII_COL

SYS_RSTz

MII_RXER

XSPCLK_MDCLK

PAUSETXSLEW1TXSLEW0

LXT_RDP

MTXD3MTXEN

MTXD0

ENET_ENABLEz

ENET_ENABLEz

LINKLED-

LED1-

MTXD1MTXD2

LXT_TDM

PWRDWN

TXSLEW0

SLEEPPAUSE

TXSLEW1

LED1-

LINKLED-

AVCC3.3

AVCC3.3

AVCC3.3VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

ENET_ENABLEz 31

GIOV33_0 6,31

GIOV33_2 6,31

GIOV33_4 6,31

GIOV33_6 6,31

GIOV33_8 6,31

GIOV33_10 6,31GIOV33_12 6,31

GIOV33_14 6,31

GIOV33_16 6,31

GIOV33_1 6,31

GIOV33_3 6,31

GIOV33_5 6,31

GIOV33_7 6,31

GIOV33_9 6,31

GIOV33_11 6,31

GIOV33_13 6,31

GIOV33_15 6,31

3V3.SYS_RESETz 15,24,28,31

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


ETHERNET INTERFACE

DUPLEXSTATUS

Place terminationsclose to PHY sourcepins.

COLLISION/LINK/ SPEEDACTIVITY

Route pairs together,pairs are (3 and 6) and(1 and 2).

R261 22

L57

BLM21PG221SN1D

1 2

U58

LXT971ALE

TX_CLK55TXD057TXD158TXD259TXD360

TX_EN56TX_ER54

COL62CRS63RX_CLK52RXD048RXD147RXD246RXD345

RX_DV49RX_ER53MDDIS3MDC43MDIO42MDINT#64

TDI27TDO28

TPFOP 19TPFON 20

TPFIP 23TPFIN 24

LED/CFG1 38

LED/CFG2 37

LED/CFG3 36

ADDR0 12ADDR1 13ADDR2 14ADDR3 15ADDR4 16

XO 2REFCLK/XI 1

PWRDWN 39

RBIAS 17

TEST1 35

RESET#4

TEST0 34

VCCA 22

GND 25

SD/TP# 26

GN

D1

7G

ND

211

GN

D3

18G

ND

441

GN

D5

50G

ND

661

VC

CD

51

VC

CIO

18

VC

CIO

240

VC

CA

21

TMS29TCK30TRST#31

TxSLEW05TxSLEW16PAUSE33SLEEP32

N/C1 9N/C2 10N/C3 44

R285 10k

L56

BLM21PG221SN1D

1 2

R281 NO POP

C259

.1uF

R277100

C258.1uF

R258NO-POP

C247.1uF

R40710K

R274 0 EIA0402

L31EXC-3BB102H

12

C260

270pF

R279 10k

C2570.01uF

TP58MDINT

P2

RJ45 HALO HFJ11-2450E-L21

TXD-CT4

NC17GND8

TXD+1

TXD-2

RXD+3

RXD-6 RXD-CT5

S0

14S

113

LED1+9 LED1-10

LED2-12LED2+11

C303

.1uF

C24810pF

R278 10k

C226

.1uF

R275100

RN34 RPACK8-3312345678 9

10111213141516

C304

270pF

R35849.9

R287 10k

C26410pF

R257 0 EIA0402

U41CBTLV16210DGGR

2OE 47

1OE 48

1A1 2

2A1 13

1B146

2B135

GN

D8

GN

D17

GN

D32

GN

D41

VC

C15

1A2 31A3 41A4 51A5 61A6 71A7 91A8 101A9 11

1A10 12

2A2 142A3 162A4 182A5 192A6 202A7 212A8 222A9 23

2A10 24

NC1

1B2451B3441B4431B5421B6401B7391B8381B9371B1036

2B2342B3332B4312B5302B6292B7282B8272B9262B1025

R28849.9

C262.1uF

R280 1.5k

R283 10k

R259 360

L32 BLM41P750SPT

R276100

R286 NO POP

R260 NO POP

C261.1uF

R222 360

R282 10k

C2630.01uF

Y625MHz

R284 22.1k

R262 22

R289 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TVP5146VIDEO4TVP5146VIDEO3TVP5146VIDEO2TVP5146VIDEO1TVP5146VIDEO0

TVP5146VIDEO6TVP5146VIDEO7

TVP5146VIDEO5

Y I0Y I1Y I2Y I3Y I4Y I5Y I6Y I7

B.YI0B.YI1B.YI2B.YI3B.YI4B.YI5B.YI6B.YI7

VCC_3.3VVCC_1.8V

VCC_1.8V

TVP5146VIDEO[0:7]24

TVP5146HSYNC24TVP5146VSYNC24

TVP5146PCLK24

YI3 5,30YI4 5,30YI5 5,30

YI7 5,30

YI0 5,30YI1 5,30

HD 5,30VD 5,30

CAPTURE_EN30

YI2 5,30

1.8V_DC3_PCLK 31

YI6 5,30

PCLK 5,30

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


TVP5146 LEVEL SHIFTER


U66 is a tri-stateable logic translator used for DC4 to allow the TVP5146 to be disconnected from on-board circuitry.Signal levels are at 1.8V logiclevels on B side and 3.3V on A sides of translator.

C680.1uF

RN32 RPACK4-33

1234 5

678

RN33RPACK8-33123456789

10111213141516

R226 0

U66

SN74AVCB164245VR

1B1 21B2 31B3 51B4 61B5 81B6 91B7 111B8 12

2B1 132B2 142B3 162B4 172B5 192B6 202B7 222B8 23

1A1471A2461A3441A4431A5411A6401A7381A837

2A1362A2352A3332A4322A5302A6292A7272A826

1DIR 11OEn 48

2DIR 242OEn 25

VCCB 7VCCB 18VCCA42

VCCA31

GND28 GND34 GND39 GND45

GND4GND10GND15GND21

R2310

C610.1uF

C670.1uF

R26410K

C620.1uF

R64360

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LUMA




TVP5146VIDEO5

TVP5146VIDEO2

3.3VA_DDEC 3.3VD_DDEC1.8VD_DDEC

3.3VD_DDEC

3.3VA_DDEC

3.3VD_DDEC

1.8VA_DDEC

3.3VD_DDEC

3.3VD_DDEC

1.8VD_DDEC

1.8VA_DDEC

3.3VA_DDEC

3.3VD_DDEC1.8VD_DDEC

1.8VA_DDECVCC_1.8V VCC_3.3V

VCC_1.8V VCC_3.3V

3V3.SYS_RESETz15,22,28,31

TVP5146VIDEO[0:7] 23

TVP5146VSYNC 23

TVP5146PCLK 23

TVP5146HSYNC 23

3V3.I2C_CLK6,27,28

3V3.I2C_DATA6,27,28

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


TVP5146 VIDEO DECODER

DDEC_GND DDEC_GND DDEC_GND DDEC_GND

DDEC_GND

DDEC_GND DDEC_GND DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GNDDDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE

DDEC_GND

C332330pF

J11749181-1

3 4

21

5 6

L37 BLM41P750SPT1 2

R37575

C343

.1uF

L40 2.7uH

R266 22

U51TVP5146

VI_3_B17

VI_3_A16

VI_2_B8

VI_2_C9

Y8 44Y9 43

Y7 45

THERMAL81

CH

3_A

18G

ND

15C

H4_

A18

GN

D24

CH

1_A

18G

ND

79

DG

ND

456

CH

1_A

33G

ND

3

CH

3_A

33G

ND

19C

H2_

A33

GN

D6

VI_3_C18

VI_4_A23

Y2 52Y3 51

Y6 46

CH

4_A

33G

ND

22

DG

ND

232

DG

ND

342

IOG

ND

139

IOG

ND

249

IOG

ND

362

PLL

_A18

GN

D77

DG

ND

127

DG

ND

568

A18

GN

D_R

EF

13A

GN

D26

CH

2_A

18V

DD

11C

H3_

A18

VD

D14

CH

4_A

18V

DD

25C

H1_

A18

VD

D78

CH

1_A

33V

DD

4C

H2_

A33

VD

D5

CH

3_A

33V

DD

20C

H4_

A33

VD

D21

A18

VD

D_R

EF

12

DV

DD

131

DV

DD

241

DV

DD

355

DV

DD

467

IOV

DD

138

IOV

DD

248

IOV

DD

361

PLL

_A18

VD

D76

VI_2_A7

VI_1_C2

VI_1_B1

VI_1_A80

SCL28

SDA29

Y5 47Y4 50

Y1 53Y0 54

C9 57C8 58C7 59C6 60C5 63C4 64C3 65C2 66C1 69C0 70

XTAL1 74

XTAL2 75

DATACLK 40

RESETB34

PWRDWN33

INTREQ 30

FSS/GPIO35

GLCO/12CA 37

HS/CS/GPIO 72

VS/VBLK/GPIO 73

FID/GPIO 71

AVID/GPIO 36

CH

2_A

18G

ND

10

C325680pF

TP62

1

TP561

C327

0.1uF

C345

0.1uF

R331 22

L43 2.7uH

L38 BLM41P750SPT1 2

C290

0.1uF

R327

NO POP

C348

0.1uF

C285

0.1uF

C342330pF

C329

0.1uF

TP571

C288

0.1uF

C286

0.1uF

C338

330pF

C287

0.1uF

L28 BLM41P750SPT1 2

R374

75

C339

.1uF

C337

0.1uF

R265

4.7K

C326330pF

R37675

C289

.1uF

C333

.1uF

C367

330pF

L41 2.7uH

C340

680pF

R335 22

C250

0.1uF

L23 BLM41P750SPT1 2

L39 2.7uH

C346

0.1uF

C328

.1uF

R333

4.7K

L42 2.7uH

R332

100K

Y4

14.31818mhz

C292

33pF

C334

0.1uF

L44 2.7uH

C331

0.1uF

C291

0.1uF

R336 0

R328

NO POP

C284

0.1uF

R334

2.2K

C283

0.1uF

C368

330pF

C347

0.1uF

C3350.1uF

RN35RPACK8-3312345678 9

10111213141516

C336

0.1uF

J12RCA JACK

1

2

C341

0.1uF

C344680pF

C330

0.1uF

C349

33pF

R330

2K

R329

2K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VOUT_ON

VOUT_ON

VOUT_ON

3V3A_VOUT

VOUT_ON

VCC_3.3V DAC_3V3

DAC_3V3

DAC_3V3

DAC_3V3

DAC_3V3

DAC_3V3

DAC_IOUTA5

DAC_IOUTB5

DAC_IOUTD5

DAC_IOUTC5

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


VIDEO OUTPUT

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GNDDENC_GND

DENC_GND DENC_GND

DENC_GND DENC_GND


DENC_GND

DENC_GNDDENC_GND

DENC_GNDDENC_GND

DENC_GND

DENC_GNDDENC_GND

DENC_GND DENC_GND

DENC_GNDDENC_GND

DENC_GND DENC_GND

1812LS-273XJB 1812LS-273XJB

1812LS-273XJB1812LS-273XJB

1812LS-273XJB 1812LS-273XJB

1812LS-273XJB 1812LS-273XJB

C361

10pF

R346 75

R381 NO-POP

R343 1130 1%

R353267 1%

R339 1130 1%

R2721K

L35 1uH

R3481K

-

+

U47

OPA357AIDBV

3

4

526

1

L24 12uH

L26 12uH

R2701K

L27 12uH

R350 75

+ C64220uF

+ C6310uF

J8

DUAL RCA JACK

2

1

3

4

5

6

L19 12uH

R3521K

L20 12uH

L36 1uH

C254

27pF

R351 1130 1%

R3401K

C252

27pF

-

+

U48

OPA357AIDBV

3

4

526

1

C251

27pF

R342 75

R380 10K

C363

10pF

-

+

U49

OPA357AIDBV

3

4

526

1

L18 12uH

C357

10pF

C2550.01uF

R345267 1%

C253

27pF

C2560.1uF

C354

10pF

R3441K

R2711K

C3590.1uF

C3520.1uF

R341267 1%

-

+

U50

OPA357AIDBV

3

4

526

1

C353

10pF

R338 75

C360

10pF

L17 12uH

R347 1130 1%

R2691K

L12 BLM41P750SPT

L25 12uH

R349267 1%

L34 1uH

C356

10pF

J9749181-1

3 4

21

5 6

C3580.1uF

C3550.1uF

C362

10pF

L16 BLM41P750SPT

L33 1uH

VCC_1.8V

VCC_1.8V

VCC_3.3V

VCC_1.8V

B_CLKR7

B_FSR7

B_DR7

B_DX7

B_FSX7

B_CLKX7

1V8.I2C_DATA6,30,31

1V8.I2C_CLK6,30,31

AUDIO_CLK5,31

1.8V.SYS_RESETz8,13,15,29,30,31,34

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


AIC33 AUDIO INTERFACE

MIC_IN

LINE_IN


R385 5.6K

R312 10

R31120K

C276

1uF

C323 .1uF

P5

DUAL RCA JACK

2

1

3

L30 BEAD M2301

TP64 1

R37047K

R37310K

R324 10K

L45

BLM21PG221SN1D

+

C7610uF,6.3V

R388 5.6K

C315.1uF

R314 10

C317220pF

R325 NO-POP

L29

BLM21PG221SN1D

C321.1uF

R36720K

R31010

R317 10

+C73 33uF,6.3V

R322 10K

C322 .1uF

R3230

R38220K

R3865.6K

R316 10

R31810K

P3

Dual-Stereo

1U 2

1L 5

4U 35U 1

5L 44L 6

L51 BLM21PG221SN1D

C281

.1uF

C249.1uF

R320 10

+C72 33uF,6.3V

R326 NO-POP

C282

.1uF

TP69

1

U52

TVL320AIC33IZQE

HPLOUT D1HPLCOM E1

LINE1R+B7LINE1R-B6

LINE2L+A4LINE2L-B5

MICBIASA2

WCLKF9

DOUTF8

MPF2A8

MCLKG8

SELECTE8

SDA D8

RIGHT_LO+ J6

DRVSS.1 E2DRVSS.2 F2

GPIO2 J8

LEFT_LO+ J4LEFT_LO- J5

MONO_LO- J3

DINE9

MIC3RA1

LINE2R+B4LINE2R-A3

HPRCOM F1HPROUT G1

MIC3LB3

DRVDD.2 H1AVDD_ADC B1

AVSS_ADC.1 C2

AVDD_DAC J1AVSS_DAC.1 G2

RESETH8

MFP0B8MFP1B9

DVDDH9

DVSSD9 IOVDDC9

MICDETB2

RIGHT_LO- J7

SCL C8

MONO_LO+ J2

GPIO1 J9

LINE1L-A5 LINE1L+A6

BCLKG9

MFP3A9

AVSS_ADC.2 D2

AVSS_DAC.2 H2

DRVDD.1 C1

R31320K

+C7010uF

TP65

1

L49BLM21PG221SN1D

R3210

C316.1uF

C318.1uF

+

C7510uF,6.3V

C366220pF

P4

Headphone Out

3

421

+C7410uF

C365220pF

C278.1uF

R38420K

C280.1uF

C319.1uF

C279.1uF

R31920K

C320 .1uF

L48BLM21PG221SN1D

R38320K

TP63 1

C277

.1uF

C324 .1uF

R3875.6K

C314.1uF

C275

.1uF

R371330

R372330

L50 BLM21PG221SN1D

R315 10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3VVCC_1.8V

VCC_3.3V

3V3.I2C_CLK6,24,283V3.I2C_DATA6,24,28

DX7,31

3V3.DC_PCLK 5

1V8.DC_PCLK30

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

E


508162-0001


B


SPDIF OUTPUTS & USER LEDS

L B-->A H A-->B

DIR FUNCTION

USER CONTROLLED LEDS

SPDIF OUT

OPTICAL SPDIF OUT

R66330

C364

0.1uF

C79.1uF

C309

0.1uF

R364 0

DS5

LED

U62

SN74AVC2T45

A1 2

VCCB8 VCCA 1

GND1 4

B17

B26 A2 3

DIR5

C305 0.1uF

DS1

LED

R361 0

R72330

R67330

R70330

R65330

DS7

LED

U65 TOTX141P

VCC2

GND1

IN3

MP

14

MP

25

DS8

LED

R359100

DS3

LED

C307.1uF

DS2

LED

DS4

LED

R362100K

U2

PCF8574AGND 8P3 7

A0 1A1 2A2 3P0 4

P2 6P1 5

VDD16SDA15SCL14INT13P712P611P510P49

J13RCA JACK

1

2

R360 220

C308.1uF

DS6

LED

C306

0.1uF

U61

SN74LVC1G125 3

4

5

2

1

R363 33

U63

SN74LVC1G125 3

4

5

2

1

R71330

R69330

R68330

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

430_TEST/VPP

430_TMS

MSP430_3V3

430_TDO

430_TDI

430_TDI430_TDO

430_TMS430_TEST/VPP430_TCK

430_TCK

MSP430_3V3

VCC_3.3VVCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_1.8V VCC_3.3V

VCC_3.3V

VCC_3.3V

VCC_3.3V

3V3.I2C_DATA 6,24,27

3V3.SYS_RESETz15,22,24,31

3V3.CF_CD1193V3.CF_CD219

3V3.I2C_DATA6,24,273V3.I2C_CLK6,24,27

3V3.UART_RXD1 15,31

3V3.UART_TXD1 15,31

SD/MMC.WP16

SD/MMC.INS16MS.INS16

3V3.SM_CEz15

VLYNQ_ONz 14VDDIMX_EN 35

USB.DRVVBUSz 21

SM.CD17

3V3.CF_PWR_ON15,19xD.CD17

3V3.CF_RESETz 19

3V3.I2C_CLK 6,24,27

SM.xD.WP17

MSP430_INT 15

PLL.FS1 5PLL.SR 5PLL.CSEL 5

PLL.FS2 5

3V3.I2C_DATA6,24,273V3.I2C_CLK6,24,27

1V8.WLAN_RESETz 32

ATA_SEL 15

CFn_SEL 15

USER_SW10

SPAREIO115SPAREIO215SPAREIO315

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


MSP430 & IR INTERFACE

C85

0.1uF

U35

PCF8574AGND 8P3 7

A0 1A1 2A2 3P0 4

P2 6P1 5


D3BAT17

R22410K

C84.1uF

+ C1310uF 6.3V

R102NO-POP

R96 NO-POP

C193.1uF

R7410KD4

BAT17

BHT1

BA2032SM

2

1

J2

HEADER 7X2TDO/TDI1 NC2 2TDI/VPP3 VCC_MSP 4TMS5 XOUT 6TCK7 TEST/VPP 8GND9 ACLK 10RST/NMI11 ACLKEN 12NC113 TCLKEN 14

R105100K

C83.1uF

C163

0.1uF

RN25RPACK4-10K

1 2 3 45678

C100.1uF

U4

MSP430F1232IPW

VC

C2

P2.0/ACLK8P2.1/INCLK9

XIN6

XOUT5

VS

S4

P1.0/TACLK 21

TEST 1

P2.2/CAOUT/TA010

RST/NMI7

P1.1/TA0 22P1.2/TA1 23

P1.3/TA2 24

P1.4/SMCLK/TCK 25

P1.5/TA0/TMS 26

P1.6/TA1/TDI 27

P1.7/TA2/TDO 28

P2.3/CA0/TA119P2.4/CA1/TA220P2.5/ROSC3

P3.0/STE0/A511P3.1/SIMO012P3.2/SOMI013P3.3/UCLK014P3.4/UTXD015P3.5/URXD016P3.6/A617P3.7/A718

R10447K

U18

PCF8574AGND 8P3 7

A0 1A1 2A2 3P0 4

P2 6P1 5


TP41

R42210K

+ C110uF 6.3V

R10110K

R273 0

Y1

32.768KHz

R98 0

R103 0

R421NO-POP

R75100

U30SN74LVC1G063

4

5

21

L1

BLM41P750SPT

U3

TSOP34840

2

31

R97 NO-POP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

B.EM_A16B.EM_A18

B.EM_A12

EM_A7

B.EM_A14

B.EM_A21

EM_A5

EM_A9 EM_A8B.EM_A11

EM_A6

B.EM_A17

B.EM_A10

EM_A3

B.EM_A13

B.EM_A19

B.EM_A15

B.EM_A20

EM_A4

EM_D14

EM_D10EM_D12

EM_D8

EM_D4EM_D6

EM_D2EM_D0

EM_D15

EM_D11EM_D13

EM_D9

EM_D5EM_D7

EM_D3EM_D1

VCC_1.8VVCC_5V

VCC_3.3VVCC_3.3V

EM_A[3:21]3,12,13,14

EM_D[0:15]3,12,13,14

ATA1_EM_BA13,12,13,15ATA_CS13,15

WRITE_WE3,12,13,15 READ_OE 3,12,13,15INTRQ_EM_RNW 3,15

ATA0_EM_BA0 3,15ATA_CS0 3,15

ALE_EM_A13,12,13,15CLE_EM_A2 3,12,13,15ATA2_EM_A0 3,12,13,15

DC_EM_CS2 10

WAIT/BUSY3,15

EM_CS33CLKOUT0 8

B.EM_A[10:21]12,13,14

1.8V.SYS_RESETz8,13,15,26,30,31,34

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


EMIF EXPANSION CONNECTOR

EMIF CONNECTOR

DC1

HEADER 35x2

1133557799111113131515171719192121232325252727292931313333353537373939414143434545474749495151535355555757595961616363656567676969

2 24 46 68 8

10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 6062 6264 6466 6668 6870 70

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_1.8VVCC_1.8V

VCC_1.8VVCC_1.8V

VCC_5VVCC_5V

VCC_5V VCC_5V

VCC_3.3VVCC_3.3V

VCC_3.3VVCC_3.3V

GIO36GIO66

COUT05,10COUT25,10

GIO06

COUT45

GIO2 6GIO5 6

VSYNC 5

COUT1 5,10

VCLK5

YOUT65

COUT65

VPBECLK5

YOUT05,10YOUT25,10YOUT45,10

COUT3 5,10

HSYNC 5

COUT7 5COUT5 5

YOUT1 5,10YOUT3 5,10YOUT5 5YOUT7 5

YI05,23

YI65,23

CI05CI25

PCLK5,23

YI45,23YI25,23

YI1 5,23YI3 5,23

YI7 5,23YI5 5,23

CI1 5CI3 5

GIO4 6

PWM2 5

HD 5,23VD 5,23

CI5 5CI7 5

PWM15

1V8.I2C_DATA 6,26,31

GIO16

CAPTURE_EN 23

1V8.I2C_CLK6,26,31

CI45CI65

1V8.DC_PCLK27

VID_CLK5

1V8.I2C_CLK6,26,311V8.I2C_DATA6,26,31

GIO38 6

1.8V.SYS_RESETz 8,13,15,26,29,31,34

1.8V.SYS_RESETz8,13,15,26,29,31,34

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


VIDEO INPUT/OUTPUT CONNECTORS

VIDEO INPUT CONNECTOR

VIDEO OUTPUT CONNECTOR

R267 NO-POP

DC4

HEADER 25X2

2468101214161820222426283032343638404244464850

13579

1113151719212325272931333537394143454749

R268 NO-POP

DC5

HEADER 25X2

2468101214161820222426283032343638404244464850

13579

1113151719212325272931333537394143454749

R225

NO-POP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_5V

VCC_3.3V

VCC_5V

VCC_3.3V

VCC_3.3V VCC_3.3V

VCC_5V VCC_1.8V

VCC_1.8V

GIOV33_1 6,22GIOV33_3 6,22GIOV33_5 6,22

GIOV33_7 6,22GIOV33_9 6,22GIOV33_11 6,22

GIOV33_13 6,22GIOV33_15 6,22

GIOV33_06,22GIOV33_26,22GIOV33_46,22

GIOV33_66,22GIOV33_86,22

GIOV33_106,22

GIOV33_126,22GIOV33_146,22GIOV33_166,22

SPI_CLK6

CLKR7FSR7

DR7

SPI_DO 6

DX 7,27

FSX 7CLKX 7

SPI_EN0 6SPI_DI6

SPI_EN16

SD_CLK7,16,32

SD_DATA27,16,32

SD_CMD 7,16,32

SD_DATA1 7,16,32SD_DATA3 7,16,32

SD_DATA07,16,32

1V8.I2C_DATA 6,26,30

ENET_ENABLEz22

AUDIO_CLK5,261.8V_DC3_PCLK 23

McBSP_EN71V8.I2C_CLK 6,26,301.8V.SYS_RESETz8,13,15,26,29,30,34

TIMER_IN_DC3 15

3V3.SYS_RESETz 15,22,24,28

3V3.UART_TXD1 15,283V3.UART_RXD1 15,28

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


EMAC/GIO & McBSP/SPI & SD CONNECTORS

DC2

HEADER 20X2

246810121416182022242628303234363840

13579

111315171921232527293133353739

DC6

HEADER 5X2

246810

13579

R263 NO-POP

DC3

HEADER 15X2

24681012141618202224262830

13579

11131517192123252729

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


VLYNQ_TXD3

VLYNQ_TXD2

VCC_3.3V VCC_5V

VCC_3.3V

VCC_1.8V

VCC_1.8V

VCC_1.8VVCC_1.8V

SD_CLK 7,16,31

VLYNQ_CLK 3

SD_DATA07,16,31

VLYNQ_SCRUN3

SD_CMD 7,16,31

SD_DATA3 7,16,31

SD_DATA2 7,16,31

SD_DATA1 7,16,31

VLYNQ_TXD0 14

VLYNQ_RXD0 14

VLYNQ_TXD1 14

VLYNQ_RXD1 14

SLP_CLK_EN 14

PM_EN 14ELP_REQ/WAKEUP 14

WLAN_INTR 14


VLYNQ_TXD214

VLYNQ_TXD314

1V8.WLAN_RESETz28

Size:

Date:

DWG NORevision:

Sheet o f

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E


508162-0001


B


VLYNQ INTERFACE

Resistors are only populated for modulesrequiring the upper VLYNQ data pairs

Resistors are only populated for modulesrequiring the upper VLYNQ data pairs

R399NO-POP

+C533uF

R391 NO-POP

R5 0

R3981K

R3971K

R40910K

R13 NO-POP

R19 NO-POP

C4

0.1uF

R10 0

C114

0.1uF

R9 0

L59

BLM41P750SPT

J16

mPCI

LED1_GRNP11 +3.3

V.3

63

LED1_GRNN13

SYS_AUDIO_IN 116

+3.3

V.4

40

INTA20

SYS_AUDIO_OUT.GND 117

+3.3

V.5

31

LED2_YELP12

AUDIO_GND.1 119

LED2_YELN14

8PMJ-3 3

RST26

TIP 1

GNT30

RING 2

PME34

AD30388PMJ-1 4

AD2842

AD2644

GN

D.1

237

AD2446

IDSEL48

8PMJ-6 5

AD2252

AD2054

GN

D.1

427

AD1858

AD1660

8PMJ-4 8

FRAME64

GN

D.1

149

TRDY66

GN

D.3

101

STOP68 RESERVED_J 112

AC_SYNC 103

AUDIO_GND.3 120

RESERVED_H 98

PAR56

AD1576

RESERVED_K 121

AD1378

AD1180

GN

D.2

102

AD984

C/BE086

RESERVED_I 100

AD690

AD492

GN

D.8

62

AD294

AD096

RESERVED_F 43

CLKRUN65

EMC1 EMC1

RESERVED_A 16

+5V

.218

M66EN 104

GN

D.1

332

SYS_AUDIO_OUT 115

+3.3

V.8

70

+3.3

V.1

89

INTB 17

AC_SDATA_IN 105

MPCIACT 122

SYS_AUDIO_IN.GND 118

VCC5VA 123

GN

D.1

050

CLK25

GN

D.1

114

REQ29

8PMJ-5 10

AD3133

AD2935

GN

D.9

55

AD2739

AD2541

RESERVED_G 93

C/BE345

AD2347

GN

D.4

83

AD2151

AD1953

8PMJ-8 9

AD1757

C/BE259G

ND

.15

23

IRDY61

+3.3

V.2

88

DEVSEL72

GN

D.7

69

EMC4 EMC4

PERR71

8PMJ-2 6

SERR67

8PMJ-7 7C/BE173

AD1475

GN

D.6

77

AD1279

AD1081

EMC2 EMC2

AD885 AD787

RESERVED_B 21

AD591

AD395

GN

D.5

82

AD199

EMC3 EMC3

CH

8GN

D15

RESERVED_E 36RESERVED_C 22

+3.3

V.6

28+3

.3V

.719

+3.3

VA

UX

.112

4+3

.3V

AU

X.2

24

+5V

.197

AC_BIT_CLK 107

AUDIO_GND 113MOD_AUDIO_MON 111

AC_CODEC_ID0# 108

AC_SDATA_OUT 106

AC_CODEC_ID1# 109AC_RESET# 110

GN

D.1

674

R390 10K

C11

0.1uF

C7

0.1uF

R11 NO-POP

R7 NO-POP

C8

0.1uF

+C233uF

+C11033uF

C6

0.1uF

R18 NO-POP

C112

0.1uF

R6 NO-POP

C3

0.1uF

R14 0R12 NO-POP

R40810K

L58

NO-POP

R15 NO-POP

C12

0.1uF

R4 NO-POP

L60

BLM41P750SPT

R17 0

R8 NO-POP

L61

BLM41P750SPT

R16 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CTI_EMU0 CTI_EMU1CTI_TCK

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8V

VCC_1.8VVCC_3.3V

DSP_TDI 8

DSP_TMS 8

DSP_EMU0 8

DSP_EMU1 8

DSP_TRST# 8

POR_RSTz34

DSP_TDO8DSP_RTCK8

DSP_TCK 8

EMULATOR_RSTn 34

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


DAVINCI EMULATION HEADER

S2/S1 SETTINGS

TI COMPATABLE EMULATORS1 1-2 S1 4-5 S2 1-2 S2 4-5

C80

NO-POP

R8210K

R87NO-POP

R880

R79 10K

R93 39

S2

CASD20TB

123

456

R91 0

U1

TPS3808G09DBVR

VDD 6

MR3

SENSE15

CT4

GND 2

RESET 1

C810.1uF

R86NO-POP

R8010K

R842.2K

R95NO-POP

S1

CASD20TB

123

456

R812.2K

R832.2K

R94 39

C82NO-POP

R85NO-POP

R90 0

J1

20 PIN CTI INTERFACE

SRST15

GND.1 8GND.2 10GND.3 12

GND.4 16

GND.5 20

EMU013 EMU1 14

EMU217 EMU3 18

TCLK11

EMU419

KEY 6TDIS 4

TDO7

TDI3 TRSTn 2TMS1

TVD5

TCKRTN9

R890

R92 33

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PBSW_RSTz

VCC_5V

AGNDVCC_5V

VCC_3.3V

VCC_3.3V VCC_1.8V

VCC_3.3V

VCC_3.3VVCC_3.3V

VCC_3.3V

DSP_CORE_VDD

VCC_3.3V

VCC_3.3V

VCC_1.8V

1.8V.SYS_RESETz 8,13,15,26,29,30,31

EMULATOR_RSTn33

POR_RSTz 33

3V3_PWR_OK 35

1V8_PWR_OK 33

1V2_PWR_OK 33

Size:

Date:

DWG NORevision:

Sheet o f

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E


508162-0001


B


POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC

3.3 sq in AGND,min thermal pad

Connectat pin 1

SetsVoltage

3.3V @1.5Amp Max

2.5 MM JACK

POWER INPUT

BBB

AAA

SENSE THRESHOLD FOR TPS3808G01 IS 0.405 VOLTS

BOX MOUNTING HOLES

CASE SHIELDING TABS FOR POWER SUPPLY

SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS

TP27

1

TP15

1

Z1

1

C960.1uF

R24710K

TP5

1

C978200pF

D5 BAS16-7

SW1SWITCH

3 1 6 4

52

78

X2

1

R160NO-POP

TP68

1

C2380.1uF

C25

0.1uF

U45

TPS3808G09DBVR

VDD 6

MR3

SENSE15

CT4

GND 2

RESET 1

C237

NO-POP

R2551K

C2361uF

DS9

GREEN

R31

71.5K 1%

J14

RASM712

CENTERSHUNTSLEEVE

Z31

R29 0.025

R254 10K

TP1

1

X41

R128107 1%

Z51

F1

F_4.0A

1 2

TP2

1

R303.74K 1%

R251 10K

R159NO-POP

TP3

1

TP16

1

R12910K 1%

+C19

100 uF

R25010K

TP28

1

C21

0.047uF

R389 no-pop

R25210K

C239

NO-POP

C26

0.039uF

D7SMCJ6A

R24910K

U44

TPS3808G09DBVR

VDD 6

MR3

SENSE15

CT4

GND 2

RESET 1

S4

PUSHBUTTON SW

X1

1

J6

HEADER 2

12

C241

NO-POP

R25310K

R245

33

C99

NO-POP

C233300pF

U46

TPS3808G09DBVR

VDD 6

MR3

SENSE15

CT4

GND 2

RESET 1

C39

0.1uF +C369

100uF 4V

+C20

100uF 4V

Z21

U19

TPS54310PWP

AGND 1VSENSE 2

COMP 3PWRGD 4

BOOT 5

PH1 6PH2 7PH3 8PH4 9PH5 10PGND111 PGND212 PGND313

VIN114 VIN215 VIN316

VBIAS17 SS/ENA18 SYNC19 RT20 POWERPAD21

R248 0

R256 0

Z41

C22470pF

X3

1

R100220

TP70

1

C2400.1uF

TP14

1

C2420.1uF

C981000pF

R13110K

R1302K 1%

L4

BLM41P750SPT+ C14

47uF

L33.3 uH

X5

1

R24610K

+C24

10uF LESR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3_PWR_OK

1V8_PWR_OK

1V2_PWR_OK

1V2_PWR_OK

1V8_PWR_OK

3V3_PWR_OK

VCC_1.8V

AGND

AGND

DSP_CORE_VDD

VCC_5V

VCC_5V

DSP_CORE_VDDIMX

VCC_5VVCC_5V

VCC_1.8V VCC_1.8V

DSP_CORE_SUPPLY

DSP_CORE_SUPPLY DSP_CORE_SUPPLY

VCC_5V

VCC_3.3V

VCC_5V

VDDIMX_EN28

VDDIMX_EN28

3V3_PWR_OK34

1V8_PWR_OK 35

1V2_PWR_OK 35

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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E


508162-0001


B


POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONN

3.3 sq in AGND,min thermal pad

Connectat pin1

SetsVoltage

3.3 sq in AGND, minthermal pad

Connect at pin 1

1.2V -> 28.0K 1%1.05V -> 56.0K 1%

CORE VOLTAGE SUPPORT FOR 0.95 TO 1.2 VOLTS

0.95V -> 150K 1%

+C51

100 uFTP35

1

C42560pF

C363300pF

TP43

1

+C32

100 uF

TP37

1

R423 0

+C44

10uF LESR

C196

NO-POP

C56

0.1uF

R50

71.5K

R1472K 1%

TP29

1

U38

TPS54310PWP

AGND 1VSENSE 2

COMP 3PWRGD 4

BOOT 5




R14610K 1%

L9

BLM41P750SPT+

C54

10uF LESR

R395

10KC46

0.039uF

R3910.2K 1%

C1238200pF

C55

0.1uF

R4928.0K 1%

+C50

100 uF

TP25

1

R38 0.025

R188 100K

U27

TPS54310PWP

AGND 1VSENSE 2

COMP 3PWRGD 4

BOOT 5




TP44

1

C192NO-POP

R186

10K

C38

0.039uF

U37

UMC2N

DTR2C4 DTR2E 3

DTR1B 2

DTR1C/DTR2B6 DTR1E 1

R40

71.5K 1%

R20910K

L112.7 uH

R210NO-POP

TP36

1C161

1000pF

C37

0.1uF

TP12

1

C1220.1uF

U36AO3404

GG

SS

DD

C1590.01uF

C35470pF

TP26

1

C1911000pF

DC7

HEADER 5X2

246810

13579

R164 NO-POP

C433300pF

C160

NO-POP

R163 NO-POPR183107 1%

L7

BLM41P750SPTC45

0.1uF

R162 NO-POP

R210K

R18410K 1%

+C33

100 uF

+ C52100uF 4V

R189 0

R145107 1%

R59 0.025

R110K

R1851.65K 1%

U31AO3404

GG

SS

DD

C53

0.047uF

R187NO-POP

C34

0.047uF

+C41

100uF 4V

L82.7 uH

C1580.1uF

C124

1000pF

508160 davinci evm e - spectrum...

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