52gb/s chip to module channels using zqsfp+
TRANSCRIPT
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52Gb/s Chip to Module Channels using zQSFP+ Mike Dudek QLogic
Barrett Bartell Qlogic
Tom Palkert Molex
Scott Sommers Molex
10/23/2014
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Channel
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Channel
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Trace.s4p Connector.s4p ADS Trace
zQSFP+
HFSS Model
0.83 inch, 110Ω Stripline
Model
Host Stripline Measured
with VNA, 97Ω
3 Lengths used:
3.00in
4.46in
5.92in
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Host Stripline (measured)
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• Trace Width: 4.5mil
• Gap: 5.5mil
• PCB: FR408HR
• Surface Roughness: RTF
• Differential Z: 97Ω
2.92mm Connectors
16mil Stubs
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Molex zQSFP+ (56gig) SMT Connector
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- Molex zQSFP+ (56Gig) SMT connector
- S-parameters provided courtesy of Molex - Backward Compatible
- Retuned and Optimized for 56 gig
- Signal SMT launch pads shortened by .25mm, ground
pads remain the same size as today
- Same mating interface (connector to module) as today
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Comments on the channels.
• Channel loss per inch is conservative (based on measurements of FR408HR), Megtron 6 or equivalent could be used with lower loss.
• Channels are provided with a range of potential target losses.
• Difference in impedance between the host and module boards is not worst case, but 110 Ohms was chosen for the Module board to make it as bad as it could be with the measured channels.
• Via stub length is worst case, however the vias aren’t a major contributing factor to the degradation.
• The 2.92mm connectors are probably not as bad as an IC package/breakout is and certainly don’t have the loss that a large package would have.
• For these reasons I am not suggesting these are worst case channels, but they are realistic and any proposed solution should operate on them, (or at least the shorter ones if we choose a lower loss maximum target loss).
• The ILD fitting and FOMILD are per Clause 93A except that the fitting was only to 0.75*fb. The fitting was performed for both 52GBaud (NRZ) and 26GBaud (PAM4) results. (FOMILD is called ILDrms )
• Channel Models have been submitted for uploading to the channel data area as Chip to Module channels.
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3.0 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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25.78125 Gb/s
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3.0 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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52 Gb/s
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4.46 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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25.78125 Gb/s
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4.46 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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52 Gb/s
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5.92 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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25.78125 Gb/s
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5.92 inch Host Trace (97Ω) + zQSFP + 0.83 inch Stripline (110Ω)
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52 Gb/s
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NRZ Performance with Frequency-scaled
802.3bm CTLE
(52 Gb/s, 1e-6 BER)
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Channel
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Trace.s4p Connector.s4p ADS Trace
zQSFP+
HFSS Model
0.83 inch, 110Ω Stripline
Model
Host Stripline Measured
with VNA, 97Ω
3 Lengths used:
3.0in
4.46in
5.92in
CTLE Settings for different Host Trace Lengths:
6dB
7dB
9dB
TX RX
Gaussian filter to set Tx
20/80 risetime, 5ps.
60GHz Bessel filter to
emulate scope bandwidth
Data Rate 52Gb/s.
Voltage Swing 1Vpp
differential.
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Comments on the Simulations.
• This simulation is not making a proposal that the optimum solution is no Tx FIR and just an Rx CTLE but it investigates the suggestion that this is out of the question.
• The Tx risetime could be somewhat faster than the on-die risetime.
• Jitter hasn’t been included in the simulation.
• As discussed earlier the 2.92mm connectors are likely to be better than an IC package/footprint and the channels aren’t completely worst case.
• Additional package loss beyond the 2.92mm connector loss is likely to be equivalent to longer host traces.
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TX 20/80 Risetime: 5ps
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TX Eye: After Gaussian Filter
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3.0 inch Host Trace + zQSFP + 0.83 inch Stripline
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6 dB CTLE
optimum
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3.0 inch Host Trace + zQSFP + 0.83 inch Stripline, CTLE 6dB
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4.46 inch Host Trace + zQSFP + 0.83 inch Stripline
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7 dB CTLE
optimum
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4.46 inch Host Trace + zQSFP + 0.83 inch Stripline, CTLE 7dB
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5.92 inch Host Trace + zQSFP + 0.83 inch Stripline
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9+ dB CTLE
optimum
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5.92 inch Host Trace + zQSFP + 0.83 inch Stripline, CTLE 9dB
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Conclusions from the Simulations.
• The eyes are reasonably open even on the highest loss channel (approx 18dB) at Nyquist.
• More work would be required to determine if the NRZ, no Tx FIR, CTLE only Rx is a viable solution for Chip to Module.
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