5.4: A Single-Chip, Dual-Band, Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g Wireless LAN

Masoud Zargari1, Steve Jen2, Brian Kaczynski2, MeeLan Lee2, Michael Mack2, Srenik Mehta2, Sunetra Mendis2, Keith Onodera2, Hirad Samavati2, Weimin Si2, Kalwant Singh2, Ali Tabatabaei3, Manolis Terrovitis2, David Weber2, David Su2

and Bruce Wooley4

1Atheros Communications, Irvine, California2Atheros Communications, Sunnyvale, California

3IRF Semiconductor, Cupertino, California4Stanford University, Stanford, California

❑ Introduction

❑ Overall System Architecture

❑ Circuit Design• Receiver• Transmitter

❑ Summary

Outline

IEEE 802.11 Wireless LAN

Available Spectrum

Frequency of Operation

non-overlappingchannels

Modulation

Data Rate

555MHz 83.5MHz 83.5MHz

5.150 - 5.350 GHz5.470 - 5.825 GHz

27 3 3

2.400 - 2.483 GHz 2.400 - 2.483 GHz

OFDM CCK CCK/OFDM

6 - 54 Mbps 1 - 11 Mbps1 - 11 Mbps6 - 54 Mbps

IEEE 802.11a IEEE 802.11b IEEE 802.11g

Overall System Architecture

DigitalBaseband

RadioTransceiver

DAC

DAC

ADC

ADC

Dig

ital C

ore

Synthesizer

TransmitterDual

ReceiverDual

I

Q

I

Q

Balun

Balun

Dual-BandAntenna (I)

Dual-BandAntenna (II)

External PA

External LNA

5G

5G

2.4G

2.4G

RX/TX

Antenna

Switch

Diversity

Control(Optional)

(Optional)

Transceiver Architecture

Dual conversion with sliding IF

• Low LO leakage

• Weak LO pulling

• No need for complicated DC offset cancellation

• Can be designed to have comparable power dissipation to direct conversion

Frequency Plan

LO1 = 2/3 fRF

LO1 5GHzBand

fRf

LO2 = 1/3 fRF

LO1 IF

LO2 2.4GHzBand

672MHz

LO1

5GHz Mode

2.4GHz Mode

❑ Share the signal path between different modes

IF

• Reduce the die size

DAC

LNA

LNA

fRF13

I

Q Bas

eban

dG

ain

Co

ntr

ol

672 MHz

RF GainControl

I

Q

IF GainControl

5GHz

2.4GHz

DACOffsetControl

Receiver Block Diagram

fRF23

Frequency SynthesizersfRF

13

fRF23

672 MHzS1 S2

DACDACOffsetControl

M1

M7

M6

M8

Vdd

gain gain

gain

M2

M3 M4

M5

L3 L4

ntL1 L2

L5

Low-Noise Amplifier (LNA)

Overall Receiver NF = 4.5/5.5dB @ 2.4/5GHz

Vin+ Vin-

Vout- Vout+

Receiver Baseband Filters

Low-Q Biquad

High-Q Biquad

Transresistance Amplifier

ReplicaBiquad

Phase Detector

StateMachine10MHz

Iout

Iin

gm1 gm3 gm4

-gm3

Vin Vout

CalibrationLoop

110

100Freq. (MHz)

0

BB Filter Response over Temp. and Process

Passband Detail

0

-10

-20

-30

-40

-50

-60

-70

dB

Frequency (MHz)

1 10 100

0

-1

-2

-3

-4

dB

Baseband Filters Frequency ResponseOver Process and Temperature

-30 -20 -10 0 10 20 30-80

-70

-60

-50

-40

-30

-20

-10

0

5GHz Receiver Linearity

IIP3 = 5dBm

Bas

eban

d O

utp

ut

(dB

m)

RF Input (dBm)

Fund.IM3

FundamentalIM3

6MH

z6.

1MH

z

4800 5000 5200 5400 5600 5800 6000-100

-90

-80

-70

BPSK, 6Mbps

64QAM, 54Mbps

Sen

siti

vity

(d

Bm

)

Channel Frequency (MHz)

5GHz Receiver Sensitivity

I

Q

5GHz

2.4GHz

PA

PA

672 MHz

IQ I Q

I Q I Q

RF GainControl

Bas

eban

dG

ain

Co

ntr

ol

fRF23

fRF13

fRF13

Transmitter Block Diagram

LO1=LO2=

RC-CR

IQ

fRF23

fRF23

Transmitter Baseband Filters

3rd order Butterworth, with f3dB = 15MHz

Needs to be flat within 0.5dB in the passband

Iout

gm1 -gm3 gm4

-gm2

-gm5

DAC CurrentMirror

gmout

Requires 40dB attenuation at the DAC sampling

C1

C2 C3

2nd Order gm-C 1st Order gm-C

No auto-tuning required

160MHz

frequency of 160MHz

PA with Dynamic Biasing

ID

VGS

ID

VGS

Dynamically BiasedConventional Class A

OFDM signal has a 17dB peak-to-average ratio

BUT signal peaks are infrequent

IDmax IDmax

ID1

ID1 << IDmax

Simplified PA Block Diagram

PA

1/α

Pre-drivers

Input Output

Envelope detectors

Simplified PA Schematic

DynamicBias

FixedBias

PA_in

PA_out

1/2 of the differential circuit

Envelope Detector

PA Output Stage

Psat = 26dBm2.4GHz:

Psat = 19dBm5GHz:

M1

M2

3.3V

S1

C1

C2

Envelope Detector

2.4GHz PA Characteristics

-5 0 5 10 15 20

-32

-30

-28

-26

-24

-22

Pout (dBm)

EV

M (

dB

)

Ipa = 130mADynamic Bias

IDynamic=130mA

IDynamic=50mA

64-QAM

IDynamic=65mA

5dB

2.4GHz Transmitter Performance

EVM @ Pout = 5dBm Spectral Mask

IEEE 802.11gOFDM Mask

10dB/ Span=100MHz

Synthesizer Phase Noise

-130

-120

-110

-100

-90

1K 10K 100K 1M 10M

Frequency Offset (Hz)

Ph

ase

No

ise

(dB

c/H

z)

5 GHz

2.4 GHz

Measured at the RF output

Die Micrograph

Dual RX

Dual TX

2.4GHz PA

5GH

z PA

Synth 1

Synth 2

Bias

Co

ntro

l

Technology 0.25 µm CMOS, 1P5M

Transmitter Power Dissipation 2.4 GHz 5 GHz

741 mW @ Pout = 5 dBm710 mW @ Pout = 5 dBm

Receiver Power Dissipation 2.4 GHz 5 GHz

370 mW320 mW

TX EVM 2.4 GHz 5 GHz

-32 @ Pout = 5 dBm-30 @ Pout = 5 dBm

RX Noise Figure 2.4 GHz 5 GHz

4.5 dB5.5 dB

Phase Noise @ 100 kHz offset 2.4 GHz 5 GHz

-109 dBc/Hz-107 dBc/Hz

Measured Performance

■ IEEE 802.11a/b/g radio transceiver in 0.25 µm standard CMOS

■ No external filters

■ Sharing of the blocks between the 2.4 and 5GHz modes of operation: reduced die size

■ Integrates:

• Dual-band Receiver• 4.5/5.5dB noise figure for 2.4/5 GHz

• Dual-band Transmitter• -32/-30dB EVM @ Pout=5dBm for 2.4/5 GHz

• Frequency Synthesizers• -109/-107 dBc/Hz @100KHz offset for 2.4/5GHz

Conclusions

Support of the entire Wireless Design Team at Atheros

in particular: H.Dieh, J. Lu, J. Thomson, R. Yu, G. Hsieh,

W. McFarland, N. Zhang, P. Husted, D. Johnson, C. Lee,

D. Nakahira, M. Robinson, J. Zheng, P. Dua, J. Chako,

A. Shor and A Dao

Acknowledgements