5x5 pixel array status 4 february 2004

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UCSB ASIC BiWeekly Status Meeting Slide 1 5x5 Pixel Array Status 4 February 2004 Sam Burke Sean Stromberg UCSB HEP Group

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5x5 Pixel Array Status 4 February 2004. Sam Burke Sean Stromberg UCSB HEP Group. ASIC Progress. SPDT Analog Transmission Gate Created. SPDT Transmission Gate. SPDT Transmission Gate. 12x6.75um cell Blue: Metal1 Red: Poly1 Green: Active Pink: P+ Yellow: N Well Lt Green:Active - PowerPoint PPT Presentation

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Page 1: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 1

5x5 Pixel Array Status4 February 2004

Sam Burke

Sean Stromberg

UCSB HEP Group

Page 2: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 2

ASIC Progress

• SPDT Analog Transmission Gate Created

Page 3: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 3

SPDT Transmission Gate

Page 4: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 4

SPDT Transmission Gate•

12x6.75um cell – Blue: Metal1

– Red: Poly1

– Green: Active

– Pink: P+

– Yellow: N Well

– Lt Green:Active

– Blk squares: Contact

– Wht #1: Via1

– Gray: Metal2

– Note: N+ not drawn?

Page 5: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 5

SPDT Trans Gate Net List

Page 6: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 6

Transmission Gate

• Transient Response Tlh=59ps Thl=154ps

Page 7: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 7

PIXEL Usage

• 250 um Pixel Size Area=250^2=62500 um^2

• 18 bit Counter 18*498=8964 um^2 (14%)• Analog Circuits 10,000 um^2 est (16%)• Misc. Glue Logic (7%)

10 Inverters 10*54= 540 um^2 8 DFFR 8*498= 3984 um^2

• Unused Area 62500-23488=39012 um^2 (62%)

Page 8: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 8

PIXEL Area Usage

Page 9: 5x5 Pixel Array Status 4 February 2004

UCSB ASIC BiWeekly Status Meeting Slide 9

Future Plans

• Continue creating new Cell Library NMOS & PMOS Transistors Inverter1 (done) Transmission Gate (done) NAND Gate NOR Gate D Flip Flop D Flip Flop with Clear