6 dynamic logic

7/28/2019 6 Dynamic Logic

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DynamicDynamic CMOS CircuitsCMOS Circuits


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OutlineOutline In-depth discussion of CMOS logic families

Static and DynamicStatic and Dynamic

Dynamic circuitsDynamic circuits

ominoomino loi cloi c

NpNp-- logiclogic

TspcTspc--logiclogic

NoraNora--logiclogic

Area, Speed, Energy or Robustness

High Performance circuit-design techniquesDynamic logicNitin ChaturvediNitin Chaturvedi


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Dynamic GateDynamic Gate

InIn11

InIn22 PDNPDN

MpCLKCLK

OutOut

CCLL

OutOut

CLKCLK

AA

Mpon

1

off!((A&B)|C)

on

InIn33

MeCLKCLK

CLKCLK

BB

Me

Two phase operation

PrechargePrecharge(CLK = 0)EvaluateEvaluate (CLK = 1)

off

Dynamic logicNitin ChaturvediNitin Chaturvedi


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Conditions on OutputConditions on Output Once the output of a dynamic gate is discharged, it

cannot be charged again until the next precharge

operation.

Inputs to the gate can makeat mostat most one transition.

Output can be in high impedance state during andduring andafterafterevaluation (PDN off), state is stored on CL

This behavior is fundamentally different than the staticcounterpart that always has a low resistance pathbetween the output and one of the power rails



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Properties of Dynamic GatesProperties of Dynamic Gates Number of transistors is N +Number of transistors is N + 22 (versus 2N for static

complementary CMOS)

Logic function is implemented by the PDN only

Should be smaller in area than static complementary CMOS

u sw ng ou pu su sw ng ou pu s OL = an OH= DD

NonratioedNonratioed- sizing of the devices is not important for

proper functioning (only for performance)

Low noise marginLow noise margin (NML)

PDN starts to work as soon as the input signals exceed VVTnTn, so

set VVMM, VVIHIHand VVILIL all equal to VTn



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Properties of Dynamic Gates IIProperties of Dynamic Gates II Faster switching speedsFaster switching speeds

Reduced load capacitance due to lower number of transistors

per gate (CCintint) so a reduced logical effort

Reduced load capacitance due to smaller fan-out (CCextext)

NoII so all the current rovided b PDN oes into

discharging CCLL

Ignoring the influence of precharge time on the switching

speed of the gate,ttpLHpLH= 0 but the presence of the evaluation

transistor slows down thettpHLpHL

Needs a precharge/evaluate clockNeeds a precharge/evaluate clock



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Properties of Dynamic Gates IIIProperties of Dynamic Gates III Power dissipation should be better than CMOS

Consumes only dynamic powerConsumes only dynamic power no short circuit power

consumption since the pull-up path is not on when evaluating Lower CLower CLL- both Cint (since there are fewer transistors

connected to the drain output) and Cext (since there the outputload is one er connected ate not two

No glitchesNo glitches - By construction can have at most one transitionper cycle

However overall power dissipation is usually higher

than static CMOS due to higher transition probabilitieshigher transition probabilities

extra load on CLKextra load on CLK



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Dynamic BehaviorDynamic Behavior

CLKCLK

InIn11

InIn22

OutOut

In &In &

1.5

2.5EvaluateEvaluate

CLKCLK

InIn44

#Trs#Trs VVOHOH VVOLOL VVMM NMNMHH NMNMLL ttpHLpHL ttpLHpLH ttpp

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps

CLKCLKuu

-0.5

0 0.5 1

Time (ns)Time (ns)

PrechargePrecharge

all data inputs set to 1



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Notes on Dynamic BehaviorNotes on Dynamic Behavior The precharge time is determined by the time it takes to

charge CCLL through the PMOS precharge transistor.

Often, the overall digital system can be designed in such a way

that the precharge time coincides with other system functions

(e.g., precharge of a FU can coincide with instruction decode).

The duration of the precharge cycle can be adjusted bychanging the size of the PMOS precharge transistor.

But making it too large increasesincreases the gates CCintint as well

as increasing the capacitive load on the clock.



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Gate Parameters are Time IndependentGate Parameters are Time Independent The amount by which the output voltage drops is a

strong function of the input voltage and theavailableavailableevaluation time.evaluation time.

Noise needed to corrupt the signal has to be larger if theevaluation time is short i.e., the switching threshold is trulytime independent.

Time (ns)

-0.5

0.5

1.5

2.5

0 20 40 60 80 100

Voltage

(V)

CLKCLKVVoutout (V(VGG==00..4545))

VVoutout (V(VGG=0.5)=0.5)

VVoutout (V(VGG==00..5555))



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Power Consumption of Dynamic GatePower Consumption of Dynamic Gate

InIn11

InIn22 PDNPDN

MpCLKCLK

OutOut

CCLL

Power only dissipated whenPower only dissipated whenprevious Out =previous Out = 00

InIn33

MeCLKCLK

But what about clock power impact?But what about clock power impact?

EliminatesEliminatesStatic powerStatic powerConsumptionConsumption



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AA BB OutOut

0 0 1

Dynamic 2Dynamic 2--input NOR Gateinput NOR Gate

Assume signal probabilitiessignal probabilitiesPA=1 = 1/2PB=1 = 1/2

Dynamic PC is Data DependentDynamic PC is Data Dependent

1 0 0

1 1 0

Then transition probabilitytransition probabilityPP0011 = P= Pout=0out=0 x Px Pout=1out=1

= 3/4 x 1 = 3/4

Switching activity can be higherhigherin dynamic gates!PP0011 = P= Pout=out=00

(static NOR gate PP0011 = 3/16)



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Issues in Dynamic DesignIssues in Dynamic Design 11:: Charge LeakageCharge LeakageCLKCLK

CLKCLKOutOut

A=A=00 CCLL

Mp

11

3344

VVOutOut

Precharge

CLKCLK

Leakage sourcesLeakage sources

Me

Minimum clock rate of a few kHzMinimum clock rate of a few kHz



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Source of Charge LeakageSource of Charge Leakage Charge stored on CCLL will leak away with time (input in

low state during evaluation)

Dominant leakage sources are reverse-biased diode ((11))and the sub-threshold leakage ((22)) of the NMOSpulldown device.

PMOS precharge device also contributes some leakagedue to reverse bias diode ((33)) and subthresholdconduction ((44)) that, to some extent, offsets the leakagedue to the pull down paths.

Requires a minimum clock rateRequires a minimum clock rate

Not good for low performance products such as watches (orwhen there are conditional clocks)



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Impact of Charge LeakageImpact of Charge Leakage Output settles to an intermediate voltage determined by a

resistive dividerresistive divider of the pull-up and pull-down networks

Once the output drops below the switching threshold of thefan-out logic gate, the output is interpreted as a low voltage.

-0.5

0.5

1.5

2.5

0 20 40

Time (ms)

Voltage

(V)

CLK

Out



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A Solution to Charge LeakageA Solution to Charge Leakage

Same approach asSame approach aslevel restorer logiclevel restorer logic

KeeperKeeper

KeeperKeeper compensates for the charge lost due to the pull-

down leakage paths.

CLKCLK Mp Mkp

CCLL

CLKCLK Me

BB

uu

StateState PDNPDN OutOut MMkpkp

PrechargePrecharge Irr. VDD ONON

EvaluateEvaluate OFFOFF VDD ONONONON VDD 0 ONON OFFOFF

If PDN is on, there is a fight between the PDN and the PUNIf PDN is on, there is a fight between the PDN and the PUN -- circuitcircuitmust be ratioed so thatmust be ratioed so thatPDN wins, eventuallyPDN wins, eventually



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Issues in Dynamic DesignIssues in Dynamic Design 22::

Charge SharingCharge Sharing

Charge stored originally on

CCLL is redistributed (sharedshared)over CCLL and CCAA leading tostatic power consumption by

CCLL

CLKCLK

CCaaB=0B=0

AA

OutOutMp

possible circuit malfunction.

When VVoutout== -- VVDDDD((CCaa/ (/ (CCaa++ CCLL )))) the drop in VVoutout islarge enough to be belowbelowthe switching threshold ofthe gate it drives causing a malfunction.

CLKCLK CCbbMe



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What is the worst case voltage drop ony? (Assume all inputs arelow during precharge and that all internal nodes are initially at 0V.)

Charge Sharing ExampleCharge Sharing Example

CLKCLK

AA !A!A

y = Ay = A BB CC

CCyy==5050fFfF

LoadLoadinverterinverter

a

CLKCLK

BB !B!B BB !B!B

CC!C!C

CCaa==1515fFfF

CCcc

==1515fFfF

CCbb==1515fFfF

CCdd

=10fF=10fF

b

dc

VVoutout== -- VVDDDD[([(CCaa++ CCcc)/(()/((CCaa++ CCcc) +) + CCyy)])]

== -- 22..55V*(V*(3030/(/(3030++5050)) =)) = --00..9494VV



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Solution to Charge RedistributionSolution to Charge Redistribution

MpCLKCLK

AA

OutOut

Mkp CLKCLK

Prechargeinternal nodes using a clock-driven transistor(at the cost of increased area and power)

MeCLKCLK



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==11=0=0

Susceptible to crosstalk due to 1) high impedance of the

output node and 2) capacitive coupling

Issues in Dynamic DesignIssues in Dynamic Design 33::Backgate CouplingBackgate Coupling

CLKCLKOutOut11

Mp

OutOut22

M5M6

CLKCLK

B=0B=0

Me

InIn

Dynamic NANDDynamic NAND

Static NANDStatic NAND

1

M2 M3

4LL11

LL22

OutOut22 capacitively couples with OutOut11through the gate-source and gate-drain capacitances of M4



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Backgate Coupling EffectBackgate Coupling Effect

2

3

Capacitive coupling means OutOut11 drops significantly so

OutOut22 does not go all the way to ground

Time (ns)Time (ns)

-1

0

1

0 2 4 6

CLK

In

Out1

Out2



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Notes on Backgate Coupling EffectNotes on Backgate Coupling Effect

The high impedance of the output node makesthe circuit verysensitive to crosstalksensitive to crosstalk effects.

A wire routed over or next to a dynamic node maycouple capacitively and destroy the state of thefloating node.

Due to capacitive backgate coupling between theinternal and output node of the static gate andthe output of the dynamic gate, Out1Out1 voltage is

reduced.

Out1Out1 overshoots VVDDDD (2.5V) due to clockfeedthrough



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A special case of capacitive coupling between the clock

input of the precharge transistor and the dynamic output

node

Issues in Dynamic DesignIssues in Dynamic Design 44:: Clock FeedthroughClock Feedthrough

CCLL

CLKCLK

BB

AAOutOut

p

Me

CLKCLK input of the prechargedevice due to the gate- drain

capacitance. So voltage of

OutOut can rise above VVDDDD. Thefast rising (and falling edges)

of the clock couplecouple to OutOut.



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CLKCLK

InIn11

InIn22

OutOut

1.5

2.5

ClockClockfeedthroughfeedthrough

Clock Feedthrough ExampleClock Feedthrough Example

CLKCLK

InIn33

InIn44

CLKCLKOutOut

Time (ns)Time (ns)

-0.5

0.5

0 0.5 1

feedthroughfeedthrough

Signal levels can rise enough aboveSignal levels can rise enough above VVDDDDthat the normally reversethat the normally reverse--biased junction diodes become forwardbiased junction diodes become forward--biased causing electronsbiased causing electronsto be injected into the substrate.to be injected into the substrate.



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Cascading Dynamic GatesCascading Dynamic Gates

VV

CLKCLK

InInOut1Out1

CLKCLK

InIn

Mp

OutOut22

CLKCLK Mp

tt

uu

OutOut22VV

TnTn

Only a singleOnly a single 00 11 transition allowed at thetransition allowed at theinputs during the evaluation period!inputs during the evaluation period!

CLKCLKCLKCLK Me Me



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Domino LogicDomino Logic

1 11 0

0 00 1

OutOut11 OutOut22

Mkp

InIn11

MpCLKCLK MpCLKCLK

InIn22 PDNPDNInIn33

MeCLKCLK

InIn22

PDNPDN

InIn33

MeCLKCLK

Assume all inputs to the Domino gate are initially zerozero



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Why Domino?Why Domino?

In1

CLKCLK

CLKCLK

i

Inj

i

Inj

i

Inj

i

Inj

Like falling dominos!Like falling dominos!



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Notes on Dominic LogicNotes on Dominic Logic

Ensures all inputs to the Domino gate are set to 0 at theend of the precharge period. Hence, the only possible

transition during evaluation is 0 to 1 Additional advantage is that the fan-out of the gate is

driven by a static inverter with a low-impedance outputa ncreases e no se mmun y.

The buffer also reduces the capacitance of the dynamicoutput node byseparating internal and loadcapacitances.

Finally, the inverter can be used to drive a bleeder tocombat leakage and charge redistribution.



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CC

CLKCLK

GG

PP00 PP11 PP22 PP33

GG GG GG

CCi,i,441234

3 3 3 3 3

Domino Manchester Carry ChainDomino Manchester Carry Chain

,,

CLKCLK 6 2345

!(G!(G00 + P+ P00 CCi,i,00)) !(G!(G11 + P+ P11GG00 + P+ P11PP00 CCi,0i,0))

Automatically forms all the intermediate carries



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CLKCLKAA33 AA22 A1A1 AA00

OutOut

Domino ComparatorDomino Comparator

BB33 BB22 BB11 BB00

Dont need isolation NMOS in the pullDont need isolation NMOS in the pull--down,down,since the PDN is forced off during precharge.since the PDN is forced off during precharge.



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Properties of Domino LogicProperties of Domino Logic

Onlynon-inverting logic can be implemented, fixes

include

can reorganize the logic using Boolean transformations

use differential logic (dual rail)

-

Very high speedVery high speed

ttpHLpHL = 0, only Low-High transitions allow

static inverter can be optimized to match fan-out (separation offan-in and fan-out capacitances)

Input capacitances reduced -smaller logical effortsmaller logical effort



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1 0 1 0

onoff

Differential (Dual Rail) DominoDifferential (Dual Rail) Domino

Mp Mkp Mkp MpCLKCLK

!Out = !(AB)!Out = !(AB)

CLKCLK

Out = ABOut = AB

Solve problem of non-inverting logic

Due to its highDue to its high--performance, differential domino is very popularperformance, differential domino is very popularand is used in several commercial microprocessors!and is used in several commercial microprocessors!

Me

BB

CLKCLK

!A!A !B!B

AND/NANDAND/NAND



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Notes on Differential DominoNotes on Differential Domino

The inputs and their complements come from other

differential DR gates and thus all inputs are low during

precharge and make a conditional transition from 0 to 1. ExpensiveExpensive - but can implement any arbitrary function.

transition every single clock cycle (regardless of signal

statistics, since either OutOut or !Out!Out will transit from 0 to 1).

NonratioedNonratioed(even though it has a cross-coupled PMOS

pair)



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npnp--CMOS (Zipper)CMOS (Zipper)

1 11 0

InIn11

MpCLKCLK

OutOut11

InIn44

InIn

Me!CLK!CLK

PUN

0 00 1

Only 0 1 transitions allowed at inputs of PDNOnly 1 0 transitions allowed at inputs of PUN

22

InIn33

MeCLKCLK Mp!CLK!CLK

OutOut22(to PDN)(to PDN)

In4 and In5 must be from PDNIn4 and In5 must be from PDN



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NORA (No Race)NORA (No Race)

1 11 0

InIn11

MpCLKCLK

Out1Out1

InIn44

InIn

Me!CLK!CLK

PUN

0

00 1

Very sensitive to Noise!

InIn33

MeCLKCLK Mp!CLK!CLK

OutOut22(to PDN)(to PDN)

to otherto otherPDNsPDNs to otherto otherPUNsPUNs



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Note on npNote on np--CMOS and NORACMOS and NORA

DEC alpha uses np-CMOS logic (Dobberpuhl)

Have to size the PUNs to equalize the delay to that of

the PDNs

Reallydense layouts and very high speeddense layouts and very high speed(20% faster

t an om no w t t e correct s z ng

Reduced noise marginReduced noise margin (as with any dynamic gate)

More sensitive to noise

Increase complexityIncrease complexity

Have two clock signals to generate and route - CLK and !CLK



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npnp--CMOS Adder CircuitCMOS Adder Circuit

C2

Sum1!A

1

!A1

!B1

!B1 !A1!A1

!B1

!B1

!C1

!C1

!CLK

!CLK CLK

0 x

1 x0 x

1 x

1 x

0 x

B0 C0C0

C0

!C1

!Sum0B0A0

A0

B0

B0 A0A0

CLK

CLK !CLK

!CLK

0 x

1 x



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ADVANTAGEADVANTAGE11 ----MULTIPLE OUTPUT DOMINOMULTIPLE OUTPUT DOMINO


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ExampleExample

Multiple precharge trans.


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ADVANTAGEADVANTAGE22 COMPOUND DOMINOCOMPOUND DOMINO


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StyleStyle # Trans# Trans EaseEase Ratioed?Ratioed? DelayDelay PowerPower

44--input NANDinput NAND

How to Choose a Logic StyleHow to Choose a Logic Style

Must consider ease of design, robustness (noiseimmunity), area, speed, power, system clockingrequirements, fan-out, functionality, ease of testing

CPL*CPL* 12 + 2 2 no 4 3

dominodomino 6 + 2 4 no 2 2 + clk

DCVSL*DCVSL* 10 3 yes 1 4

* Dual Rail* Dual Rail

Current trend is towards an increased use of

complementary static CMOS: design support through

DA tools, robust, more amenable to voltage scaling.Dynamic logicNitin ChaturvediNitin Chaturvedi

6 dynamic logic

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