6 the dark art of cmp - entrepix | a cmp supplier of cmp ... · thinning of densely spaced plugs...

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IntroductionThe driving force in the semiconductor

industry continues to be relentless pursuitof higher performance and lower unitcosts. An impressive series of processinnovations, including chemical mechanicalplanarization (CMP), has enabled this trendfor nearly four decades. At various steps inprocessing a silicon integrated circuit (IC),surface topography from underlying layerscan cause yield-limiting problems for thenext process step. CMP emerged as thepremier method for achieving ultraflatsurfaces when they are most critical, thusenabling many of the advanced electronicdevices currently in production.

CMP became a mainstream process atand below the 0.35µm technology node.The first high-volume processes were oxideCMP for ILD planarization and tungsten(W) CMP for contacts and vias. Since thenthe number of materials being polished invarious CMOS process flows has steadilygrown, as shown in Figure 1.[1]

A complexity involved with CMP is thateach material generally requires a uniqueslurry, a properly designed pad, optimizedprocess settings for both polish and post-CMP clean, and other factors that must beindividually tailored to the application.Successful results are achieved only whenall the pieces of the puzzle fit together.

HistoryThe first widespread application of CMP

was the planarization of interlevel die-lectric oxide layers. The topographyresulting from lower levels of patternedfilms can create a very nonplanar ILDsurface, which creates severe difficultiesfor at least three subsequent processsteps: photo, metal deposition and metaletch.[2] The depth of focus (DOF) atphotolithography is a direct function of theillumination wavelength and sets an upperlimit on surface height variation that canbe accommodated and still maintain crispfeature definition. In order to print smallerfeatures, topography had to be reduced. A second problem was poor sidewall stepcoverage at the next metal deposition.

The Dark Art of CMP

Robert L. Rhoades – Entrepix, Inc.

Figure 1. Snapshots by Year of CMOS MaterialsPolished by CMP

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Finally, metal etch required excessiveoveretch for complete removal of metalstringers at the bottom inside corners. Allthree of these factors became virtuallyimpossible to solve with existing tech-niques at the 0.35 micron technologynode; thus oxide CMP was born.

The development of tungsten (W) CMPwas driven by different factors. The basicconcept for tungsten contacts, vias or localinterconnect is to etch features into anoxide layer which are then coated by a thin

barrier metal and filled with conformalCVD tungsten. Tungsten is removed fromthe top surface leaving inlaid metalfeatures that are electrically isolated fromeach other. Unfortunately, CVD Wdeposition processes are prone tochamber flakes, gas phase nucleation andother sources of particles or defects.Tungsten CMP solved two key issues: 1) particles, flakes and other defects weremechanically wiped from the surface, and 2) tops of plugs were left virtually coplanar

Figure 2. CMP Puzzle


with the oxide rather than recessed ashappened with etchback. This led tosubstantial yield improvements andenabled stacked vias in design rules formultilevel interconnect.

The third mainstream CMP process wasshallow trench isolation (STI) CMP. In theearly steps of IC manufacturing, transistorsmust be electrically isolated from eachother, which was previously done with atechnique known as LocOS (Local Oxidationof Silicon). STI enables transistors to beisolated at much closer spacings thusallowing further design rule shrinks.

As IC technology evolved toward the0.25 micron node, interconnect delays dueto resistance-capacitance (RC) timeconstants were rapidly becoming thelimiting factor for circuit speed rather thantransistor gate delay. With only threemetals (gold, copper and silver) havinglower resistivity than aluminum, choices forlowering R were limited. Copper emergedas the most tractable option even thoughplasma-based Cu etch failed. Rather thanetching lines as had been done fordecades with aluminum, patterning of Cuinterconnects is done with the dual

damascene process. Basic terms andfailure modes associated with Cu CMP areshown in Figure 4.[4]

To meet planarity requirements fordishing and erosion, most Cu processes areperformed in three stages: 1) bulkplanarization stopping just above thebarrier layer, 2) soft landing with highselectivity to barrier, then 3) barrierremoval and final surface finish. Thiseffectively turns one CMP process intothree different processes performed inseries. The first two stages often use thesame slurry (though not necessarily) andrequire a planarizing pad. The third stagerequires a different slurry and often adifferent pad which may be chosen fordefectivity performance if the barrierslurry is relatively nonselective.

Theory and Length ScalesMany theoretical models of CMP

are based on or derived from a simpleequation known as Preston’s Law, whichstates that removal rate is linearly pro-portional to the product of pressure andvelocity. This “law” provides a reasonablemodel for mechanical wear, but is not

…The Dark Art of CMP

Figure 3. SEM photos showing (a) cross section of a sloped-wall M1/M2 via made w/o CMP; (b) developmental M1/M2 via in same device using 2 levels of oxide CMP and 1 level of tungsten CMP;(c) interconnects enabled by multiple levels of CMP.[3]

X-section showing example ofmetal 2 to metal 1 via and metal 1

to silicon contact

A B C


adequate for CMP. It does not account for chemical effects, such as etching,reaction thresholds, depletion/saturation,temper-ature sensitivity or electro-chemistry (in metals). It also does notaccount for nonlinear fluid dynamics,particle-surface interactions, tribologicaleffects, time-dependent pad surface wear,pad conditioning, polymer properties, andmore.[5,6,7]

A recurring complexity of CMP ispattern density sensitivity. Simply stated,pattern density is the fraction of high areato total surface area. For oxide CMP, this isdriven by the underlying metal. For otherlayers, high may refer to field areasbetween recessed features. The rate atwhich high features are removed isproportional to the effective contactpressure which equals the averagepressure divided by the local pattern

density. The region considered “local” is a direct function of planarization lengthwhich is roughly the lateral distancerequired for relaxation of deflections in thepad surface. The impact of pattern densityvariation can be dramatic, as shown inFigure 5 for a typical oxide CMP process.The commercially available test wafer isbased on line-space patterns in 4 mm x 4 mm arrays with constant pitch andvarying linewidths.[8] Initial step height of all features was 8 kA and data pointswere taken at the center of each array.

All of the features were planarized bythe end of polish (step height near zero),but a substantial difference in oxideremaining was induced by the patterndensity variation. Oxide thickness remain-ing over the lines in the 80 percent arraywas just over 11 kA, while the oxideremaining over the 10 percent array was

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Figure 4. Cu CMP Terms and Common Failure Modes


less than 8 kA – a difference of over 3 kA!This difference is nearly equivalent to theblanket film removal rate for a period of100 seconds, which is how long the 10percent array was polished after reachinglocal planarity.

The relative sizes and lengths involvedin CMP may be easier to visualize througha scaled comparison. Imagine a world inwhich 1 micron is scaled up to 1 inch (2.54cm). A typical slurry particle (actualdiameter about 100nm) would be scaledup to 0.1 inches, or roughly the size of acommon BB or a large grain of sand. Theapproximate size of other relevant physicalCMP elements are shown in Figure 6. Withthis upscaled world in mind, it may beeasier to understand why CMP is consi-dered a dark art. It is like planarizing anairport with bumps ranging from

toothpicks to tool sheds by pressing itagainst a spinning polymer city floodedwith chemical soup and floating BBs.

Process IssuesVirtually any CMP module can be

described by a series of events.1. Deposit desired film or film stack onto

the device side of wafer2. Load unprotected wafer into rotating

carrier (device side down)3. Flow slurry (mixture of chemicals and

trillions of suspended particles) ontolarge diameter rotating polymer pad

4. Lower wafer onto pad and apply acontrolled pressure ranging fromroughly fifty to several hundred pounds

5. Polish until sufficient amount of the filmstack has been removed

6. Clean up mess left on wafer surface


Figure 5. Step Height as a Function of Oxide CMP Polish Time for Structures With Differing Pattern Densities


One challenge is that interactionsbetween process settings and outputmetrics are not simple to predict. They areseldom linear and they strongly depend onslurry, pad, film stack, process recipesettings, and design rules of devices beingpolished. However, certain trends generallyhold true, as summarized in Figure 7.

One of the biggest concerns in ICmanufacturing is killer defects. Over a spanof four decades, the industry has spentbillions of dollars and thousands of careersbattling the forces of defectivity. Slurrieshave trillions of particles that MUST beremoved before wafers leave the processbay. Numerous approaches have beenattempted for post-CMP cleaning, but themost popular involve immersion in amegasonic bath or double-sided scrubbingwith PVA brushes, or both. These processes

utilize post-CMP cleaning chemistriesformulated for the exposed materials andslurry particle type. Beyond slurry particles,wafers are vulnerable to other defectmechanisms during CMP. Particle sizedistribution must be tightly controlled inboth manufacturing and slurry handlingsystems to avoid large agglomerates thatcan scratch the surface. Chemistries of theboth slurry and post-CMP clean must becontrolled to avoid pitting or surfaceroughening. Buried defects that were initiallynot observable can be uncovered duringCMP which requires more trouble-shooting.

In addition to the general concerns, eachCMP process has unique issues. For oxideCMP, the polish begins and ends in thesame material, unlike most other CMPprocesses. This makes repeatability andcontrol important since variations in polish

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Figure 6. Table of Relative Sizes if 1 Micron Were Upscaled to 1 Inch


rate or uniformity translate directly intooxide thickness. Pad conditioning is key toprocess stability. Proper pad surfacetexture is required for optimal removal rateand uniformity, but establishing thistexture once at the beginning of pad life isnot sufficient. Each cycle tends to weardown the high points (called pad asper-ities), and polishing by-products tend toform a “glazing layer” on the pad. Padconditioning counteracts both of theseeffects, but overly aggressive conditioningcuts away more pad than necessary andartificially shortens pad life.

Tungsten CMP generally runs atrelatively aggressive settings. This leads to high pad surface temperatures andassociated thermal gradients which maycontribute to process instability. Failuremechanisms on device structures includeerosion and plug coring. Erosion is arraythinning of densely spaced plugs due tomechanical wear of the oxide stop layer.Coring is a term used to describe unde-sired etching of weak plug centers byslurry chemistry, which can lead to highcontact resistance or electrical opens

affecting both yield and potentiallyreliability of finished devices.

STI CMP is similar to oxide CMP in thatsilicon dioxide is the primary materialbeing polished, but with very differentperformance requirements. Successfulcompletion of the STI module requires thatCMP fully remove oxide over all nitridefeatures (active areas) without breakingthrough nitride anywhere. With nitridelayers typically only a few hundredAngstroms, this is a significant challenge,especially if attempted with traditionaloxide slurries with only about 3-to-1selectivity. Pattern density variationrenders this approach nearly impossible ifsmall isolated features and large or densestructures exist in the same die. Thepreferred solution today is slurriesspecifically formulated with extremely high selectivity to nitride.[9]

Copper CMP is the last mainstreamprocess to be considered and is arguablythe most complex. Cu is highly reactiveand has a tendency to scratch, corrode,etch or form a galvanic cell with othermetals in many aqueous chemistries. From


Figure 7. Output Metric Interactions With Process Recipe Settings


beginning to end of the polish sequence,the surface goes from being 100 percentCu to a blend of two metals to a com-posite surface with both metals and theunderlying dielectric exposed. All factorsthat could damage the Cu surface must becontrolled throughout the sequence.

Integration and Future DirectionsThe interconnect metal of choice for at

least a few more generations of advanceddevices appears to be copper, but withcontinued tightening of process metricssuch as dishing and erosion. According tothe ITRS roadmap, maximum allowable Culine thinning in an array is already less than15nm and is projected to be only 6nm bythe 32nm node.[10] Achieving this targetconsis-tently in manufacturing will requireslurries formulated to specific materials,pads with excellent surface texture control,and processes with razor-sharp endpointand/or high selectivity to a stop layer.

The dielectric film stack appears to bethe next battleground for improvinginterconnect speed. For most 65nmprocess flows, CDO-based materials arethe dominant choice for low-k dielectrics.However, they are not porous and theeffective k-value is > 2.5 in most cases. At the 45 nm node currently beingdeveloped, integration activities seemlargely focused on extending the second-generation modified CDO films, preferablywithout introducing porosity if it can beavoided. It remains to be seen how low theeffective k-value can be pushed and whatspeeds can be achieved through thisapproach. As the industry moves forwardinto the 32 and 22nm nodes, it is expectedthat devices will require ultralow-k (ULK)dielectric with k-value < 2.2 to achieve thedesired performance targets. Issues ofwater absorption and chemical retention

during CMP and post-CMP cleaning withporous ULK materials are driving mostintegration teams to include a capping orsealing layer. Unfortunately for CMP, allknown ULK materials have a strong trend of lower mechanical strength with lower k-values, primarily due to required porosity.Typical mechanical failure modes includedelamination, cracking, and inelasticdeformation. As the industry transitions tothese materials, the CMP process mustaccommodate mechanical fragility of ULKby moving toward lower pressure and lowershear processes. Most copper and barrierpolishing work for these applications is nowfocused at 2 psi and below, with sometargets as low as 0.5 psi.

Semiconductor manufacturers arerequired to manage the economic aspects oftheir business in addition to technology. Thegoal of delivering products to their custo-mers in spec, on time and at the lowestreasonable cost involves managing bothproduction capacity and new productdevelopment. When demand for any productramps, one solution to increasing output isoutsourcing to dedicated foundries foradditional wafer capacity. Commonly referredto as the “fab-lite” or “asset-lite” model, thisallows companies to increase wafer outputbeyond internal capacity limits duringperiods of high demand, while eliminatingrisks of carrying stranded capital duringperiods of weak demand. A similar approachcan be utilized for solving bottlenecks atspecific process steps, such as CMP. A viableoutsource provider can provide flexibleproduction capacity or execute engineeringprojects as needed. These external resourcescan provide the staff, expertise and the timeon process and metrology tools necessary toexecute projects that might otherwisecompete with available production resourcesin the fab.

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New Applications for CMPNow that CMP is established as main-

stream for advanced CMOS manufacturing,other technologies are attempting toleverage CMP to achieve the performancethey need. These applications representemerging growth areas and often holdsignificant planarization challenges of theirown. Analog, mixed signal, and even powerdevices are now investigating advantagesthat can be realized in their unique processflows. Advanced packaging concepts andthrough silicon vias (TSVs) represent twomore areas where planarization is key tosuccessful technology deployment.

MEMS (micro electro-mechanicalsystems) are frequently constructed withalternating polysilicon and oxide layers.Compared to CMOS, the topographyencountered in MEMS is generally muchlarger in all dimensions. Step heights up totens of microns and feature sizes of severalhundred microns are common. Polish timesare long, which exaggerates issues ofpattern density and process instability.Slurry manufacturers are developingslurries specifically to address the growingMEMS market.

The development of engineeredsubstrates and custom epitaxial layers hasaccelerated in recent years, especially SOI,SiGe strained layer structures, and variousIII-V and II-VI compound semiconductors.Many of these technologies require uniquenew polishing processes to achievesmooth, low-defect, device-ready wafers.

Direct wafer bonding is a growing trendthat encompasses efforts to bond virtuallyanything-on-anything. The technicalchallenge often arises in getting the twosurfaces smooth enough to achieve a goodbond, which generally means Ra valuesless than 1nm.

ConclusionsTechnology teams continue to find

more ways to leverage CMP as an enablingprocess for new materials and improveddevice integration. However, in order to besuccessful, process flows must meet bothtechnical and economic targets. Even withthe difficulties and uncertainties associatedwith some aspects of CMP, the planari-zation results are superior to any otherprocess currently available.

References1. Figure adapted from original, courtesy

of Cabot Microelectronics.2. M. Oliver, Chapter 2 in “Chemical-

Mechanical Planarization ofSemiconductor Materials,” Springer,2004 (M. Oliver, ed.)

3. SEM photos courtesy of Medtronic, Inc.(a,b) and Freescale Semiconductor, Inc. (c)

4. Figure adapted from original, courtesyof Fujimi Corporation.

5. E. Paul, J. Electrochem. Soc., vol.148,G355, 2001.

6. J.M. Steigerwald, S.P. Murarka, and R.J.Gutmann, “Chemical MechanicalPlanarization of MicroelectronicMaterials,” John Wiley & Sons, 1997.

7. R.K. Singh and R. Bajaj, MRS Bulletin,vol.27, No.10, 743, 2002.

8. D. Ouma, D. Boning, J. Chung, et al.,Proc. Int. Interconnect TechnologyConf., IEEE, Piscataway, N.J., 1998.

9. K.M. Robinson, K. DeVriendt, and D.R.Evans, Chapter 10 in “Chemical-Mechanical Planarization ofSemiconductor Materials,” Springer,2004 (M. Oliver, ed.)

10. ITRS Roadmap (Interconnect section),2005 version.



About the AuthorRobert Rhoades is the chief technology

officer for Entrepix, Inc. He has been anindustry leader in chemical mechanicalpolishing (CMP) for over 12 years. Dr.Rhoades earned his Ph.D. in electricalengineering from the University of Illinois.He holds over a dozen patents or patentapplications and has authored more than60 technical publications.

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