6277 - farnell · 2018. 12. 4. · 6277 8-bit serial-input, constant-current latched led driver 7...

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8-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER

The A6277x is specifically designed for LED-display applications.Each BiCMOS device includes an 8-bit CMOS shift register, accompa-nying data latches, and eight npn constant-current sink drivers. Twopackage styles and two operating temperature ranges are available.

The CMOS shift register and latches allow direct interfacing withmicroprocessor-based systems. With a 5 V logic supply, typical serialdata-input rates are up to 20 MHz. The LED drive current is deter-mined by the user’s selection of a single resistor. A CMOS serial dataoutput permits cascade connections in applications requiring additionaldrive lines. For inter-digit blanking, all output drivers can be disabledwith an ENABLE input high. In addition, a HIGH/LOW functionenables full selected current with the application of a logic low, or 50%selected current with the application of a logic high.

The first character of the part number suffix determines the deviceoperating temperature range. Suffix ‘E–’ is for -40°C to +85°C, andsuffix ‘S–’ is -20°C to +85°C. Two package styles are provided forthrough-hole DIP (suffix ‘–A’) or surface-mount SOIC (suffix ‘–LW’)applications. The copper lead frame and low logic-power dissipationallow the dual in-line package to sink 122 mA through all outputscontinuously over the operating temperature range (1.0 V drop,+85°C).

Note that the A6277EA (DIP) and the A6277ELW(SOIC) are electrically identical and share acommon terminal number assignment.

ABSOLUTE MAXIMUM RATINGSSupply Voltage, VDD ...................... 7.0 VOutput Voltage Range,

VO ............................ -0.5 V to +24 VOutput Current, IO ....................... 150 mAInput Voltage Range,

VI .................... -0.4 V to VDD + 0.4 VPackage Power Dissipation,

PD ..................................... See GraphOperating Temperature Range, TA

Suffix ‘S-’ ................ -20°C to +85°CSuffix ‘E-’ ................ -40°C to +85°C

Storage Temperature Range,TS ........................... -55°C to +150°C

Caution: These CMOS devices have inputstatic protection (Class 2) but are still suscep-tible to damage if exposed to extremely highstatic electrical charges.

6277

FEATURES■ To 150 mA Constant-Current Outputs■ Under-Voltage Lockout■ Low-Power CMOS Logic and Latches■ High Data Input Rate■ Similar to Toshiba TD62715FN■ High/Low Output Current Function Digital “Dim” Control

A6277ELW

REGISTER

LATCHES

5

10 11

12

13

14

156

7

8

9

16

POWERGROUND

POWERGROUND

HIGH/LOW(CURRENT)

OUT1

OUT 2

Dwg. PP-029-17A

OUT 0

OUT4

OUT6

OUT5

OUT3

OUT7

LOGICGROUND 1

2

3

17

19

4

18

20

SERIALDATA OUT

LOGICSUPPLY

SERIALDATA IN

OUTPUTENABLE

LATCHENABLE

CLOCK CK

VDD

OE

REXTI

REGULATOR

L

O

SUB SUB

SERIALDATA OUT2

1

FF

Selection GuidePart Number Pb-free* Package Packing Ambient Temperature (°C)

A6277EA-T Yes 20-pin DIP 18 per tube –40 to 85A6277ELW-T Yes 20-pin SOICW 37 per tube –40 to 85A6277ELWTR-T Yes 20-pin SOICW 1000 per reel –40 to 85*Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applica-tions because obsolescence in the near future is probable. Samples are no longer available. Status change: May 1, 2006. These variants include: A6277EA, A6277ELW, A6277ELWTR, A6277SA, A6277SLW, and A6277SLWTR.

115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000

62778-BIT SERIAL-INPUT,CONSTANT-CURRENTLATCHED LED DRIVER

2Copyright © 2001, 2003 Allegro MicroSystems, Inc.

50 75 100 125 150

2.5

0.5

0

AL

LO

WA

BL

E P

AC

KA

GE

PO

WE

R D

ISS

IPA

TIO

N IN

WA

TT

S

AMBIENT TEMPERATURE IN °°°°C

2.0

1.5

1.0

25

SUFFIX 'A', R = 55°C/WθJA

Dwg. GP-018-1

SUFFIX 'LW', R = 70°C/WθJA

FUNCTIONAL BLOCK DIAGRAM

MOS

BIPOLAR

LOGICGROUND

LATCHENABLE

OUTPUT ENABLE(ACTIVE LOW)

SERIAL DATA OUT

CLOCK

SERIALDATA IN

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

VDD LOGICSUPPLY

R

OUT 0 OUT 1Dwg. FP-013-7 OUT 2 OUT N

I REGULATOR

O

UVLO

POWERGROUND

POWERGROUND

SUB

HIGH/LOW(CURRENT)

FF

SERIAL DATA OUT

EXT

1

2

62778-BIT SERIAL-INPUT,

CONSTANT-CURRENTLATCHED LED DRIVER

www.allegromicro.com 3

TRUTH TABLE

Serial Shift Register Contents Serial Latch Latch Contents Output Output ContentsData Clock Data Enable EnableInput Input I1 I2 I3 ... IN-1 IN Output Input I1 I2 I3 ... IN-1 IN Input I1 I2 I3 ... IN-1 IN

H H R1 R2 ... RN-2 RN-1 RN-1

L L R1 R2 ... RN-2 RN-1 RN-1

X R1 R2 R3 ... RN-1 RN RN

X X X ... X X X L R1 R2 R3 ... RN-1 RN

P1 P2 P3 ... PN-1 PN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN

X X X ... X X H H H H ... H H

L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State

CLOCK and SERIAL DATA IN SERIAL DATA OUT

LATCH ENABLE and HIGH/LOWOUTPUT ENABLE (active low)

Dwg. EP-010-11

IN

VDD

Dwg. EP-010-12

IN

VDD

Dwg. EP-010-13

IN

VDDVDD

Dwg. EP-063-6

OUT



4

ELECTRICAL CHARACTERISTICS at TA = +25°C, VH/L = VDD = 5 V (unless otherwise noted).

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Supply Voltage Range VDD Operating 4.5 5.0 5.5 V

Under-Voltage Lockout VDD(UV) VDD = 0 to 5 V 3.4 – 4.0 V

Output Current IO VCE = 1.0 V, REXT = 160 Ω 100 120 140 mA(any single output)

VCE = 0.4 V, REXT = 470 Ω 34 42 48 mA

Output Current Matching ∆IO 0.4 V ≤ VCE(A) = VCE(B) ≤ 1.0 V:(difference between any REXT = 160 Ω – ±1.5 ±6.0 %two outputs at same VCE) REXT = 470 Ω – ±1.5 ±6.0 %

Output Leakage Current ICEX VOH = 20 V – 1.0 5.0 µA

Logic Input Voltage VIH 0.7VDD – – V

VIL – – 0.3VDD V

SERIAL DATA OUT Voltage VOL IOL = 1.0 mA – – 0.4 V

(SDO1 & SDO2) VOH IOH = -1.0 mA 4.6 – – V

Input Resistance RI ENABLE input, pull up 150 300 600 kΩ

LATCH & HIGH/LOW inputs, pull down 100 270 400 kΩ

Supply Current IDD(OFF) REXT = open, VOE = 5 V – 0.8 1.6 mA

REXT = 470 Ω, VOE = 5 V 3.5 6.5 9.5 mA

REXT = 160 Ω, VOE = 5 V 14 17 22 mA

IDD(ON) REXT = 470 Ω, VOE = 0 V 5.0 10 15 mA

REXT = 160 Ω, VOE = 0 V 20 27 40 mA

Typical Data is at VDD = 5 V and is for design information only.




RECOMMENDED OPERATING CONDITIONS

Characteristic Symbol Conditions Min. Typ. Max. Unit

Supply Voltage VDD 4.5 5.0 5.5 V

Output Voltage VO – 1.0 4.0 V

Output Current IO Continuous, any one output – – 150 mA

IOH SERIAL DATA OUT – – -1.0 mA

IOL SERIAL DATA OUT – – 1.0 mA

Logic Input Voltage VIH 0.7VDD – – V

VIL – – 0.3VDD V

Clock Frequency fCK Cascade operation – – 10 MHz

SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,REXT = 470 ΩΩΩΩΩ, IO = 40 mA, VL = 3 V, RL = 65 ΩΩΩΩΩ, CL = 10.5 pF.

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Propagation Delay Time tpHL CLOCK-OUTn – 350 1000 ns

LATCH-OUTn – 350 1000 ns

ENABLE-OUTn – 350 1000 ns

CLOCK-SERIAL DATA OUT1 – 40 – ns

Propagation Delay Time tpLH CLOCK-OUTn – 300 1000 ns

LATCH-OUTn – 400 1000 ns

ENABLE-OUTn – 380 1000 ns

CLOCK-SERIAL DATA OUT2 – 40 – ns

Output Fall Time tf 90% to 10% voltage 150 250 1000 ns

Output Rise Time tr 10% to 90% voltage 150 250 600 ns



6

TIMING REQUIREMENTS and SPECIFICATIONS(Logic Levels are VDD and Ground)

A. Data Active Time Before Clock Pulse(Data Set-Up Time), tsu(D) .......................................... 60 ns

B. Data Active Time After Clock Pulse(Data Hold Time), th(D) .............................................. 20 ns

C. Clock Pulse Width, tw(CK) ............................................... 50 nsD. Time Between Clock Activation

and Latch Enable, tsu(L) ............................................ 100 nsE. Latch Enable Pulse Width, tw(L) ................................... 100 nsF. Output Enable Pulse Width, tw(OE) ................................ 4.5 µsNOTE – Timing is representative of a 10 MHz clock.Significantly higher speeds are attainable.

— Max. Clock Transition Time, tr or tf .............................. 10 µs

Information present at any register is transferred to therespective latch when the LATCH ENABLE is high (serial-to-parallel conversion). The latches will continue to accept newdata as long as the LATCH ENABLE is held high. Applica-tions where the latches are bypassed (LATCH ENABLE tiedhigh) will require that the OUTPUT ENABLE input be highduring serial data entry.

When the OUTPUT ENABLE input is high, the outputsource drivers are disabled (OFF). The information stored in thelatches is not affected by the OUTPUT ENABLE input. Withthe OUTPUT ENABLE input low, the outputs are controlled bythe state of their respective latches.

CLOCK

SERIALDATA IN

LATCHENABLE

OUTPUTENABLE

OUTN

Dwg. WP-029-3

50%SERIAL

DATA OUT. 1

DATA

DATA

50%

50%

50%

C

A B

D E

LOW = ALL OUTPUTS ENABLED

pt

DATA

50%

pt

LOW = OUTPUT ON

HIGH = OUTPUT OFF

SERIALDATA OUT. 2

DATA50%

pt

OUTPUTENABLE

OUTN

Dwg. WP-030-1A

DATA10%

50%

pHLt

pLHt

HIGH = ALL OUTPUTS DISABLED (BLANKED)

ft rt

90%

F

50%




ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE

A6277xA A6277xLW

0 20

DUTY CYCLE IN PER CENT

100

0

Dwg. GP-062-17

AL

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UT

PU

T C

UR

RE

NT

IN m

A/B

IT

6040

20

40

60

10080

80

TA = +25°CVDD = 5 V

RθJA = 55°C/W

120

140VCE = 1 V

VCE = 2 V

VCE = 4 V

VCE = 3 V

0 20


100

0

Dwg. GP-062-15

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UT

PU

T C

UR

RE

NT

IN m

A/B

IT

6040

20

40

60

10080

VCE = 3 V

VCE = 4 V80

TA = +50°CVDD = 5 V

RθJA = 55°C/W

120

140VCE = 1 V

VCE = 2 V

0 20


100

0

Dwg. GP-062-14

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NT

IN m

A/B

IT

6040

20

40

60

10080

VCE = 4 V

80

TA = +50°CVDD = 5 V

RθJA = 70°C/W

120

140 VCE = 1 V

VCE = 2 V

VCE = 3 V

0 20


100

0

Dwg. GP-062-16

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UT

PU

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UR

RE

NT

IN m

A/B

IT

6040

20

40

60

10080

VCE = 4 V80

TA = +25°CVDD = 5 V

RθJA = 70°C/W

120

140

VCE = 2 V

VCE = 3 V

VCE = 1 V



8

0 20


100

0

Dwg. GP-062-13

AL

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NT

IN m

A/B

IT

6040

20

40

60

10080

VCE = 3 V

VCE = 4 V

80

TA = +85°CVDD = 5 V

RθJA = 55°C/W

120

140

VCE = 1 V

VCE = 0.7 V

VCE = 2 V

0 20


100

0

Dwg. GP-062-12

AL

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IN m

A/B

IT

6040

20

40

60

10080

VCE = 2 V

VCE = 3 V

VCE = 4 V

80

TA = +85°CVDD = 5 V

RθJA = 70°C/W

120

140

VCE = 1 V

VCE = 0.7 V

ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)

A6277xA A6277xLW

TYPICAL CHARACTERISTICS

0.5

Dwg. GP-063-1

1.0 2.01.5

VCE IN VOLTS

0

60

40

OU

TP

UT

CU

RR

EN

T IN

mA

/BIT

20

0

TA = +25°CREXT = 470 Ω




TERMINAL DESCRIPTION

Terminal No. Terminal Name Function

1 LOGIC GROUND Reference terminal for control logic.

2 SERIAL DATA IN Serial-data input to the shift-register.

3 CLOCK Clock input terminal for data shift on rising edge.

4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.

5 HIGH/LOW Logic low for 100% of programmed current level;(CURRENT) logic high for 50% of programmed current level.

6 POWER GROUND Ground.

7-14 OUT0-7 The eight current-sinking output terminals.

15 POWER GROUND Ground.

16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all outputdrivers are turned OFF (blanked).

17 SERIAL OUT2 CMOS serial-data output (on clock falling edge).

18 SERIAL OUT1 CMOS serial-data output (on clock rising edge)to the following shift-registers.

19 REXT An external resistor at this terminal establishes the output current for all sinkdrivers.

20 LOGIC SUPPLY (VDD) The logic supply voltage. Typically 5 V.

The products described here are manufactured under one or moreU.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time totime, such departures from the detail specifications as may berequired to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user iscautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical componentsin life-support devices or systems without express written approval.

The information included herein is believed to be accurate andreliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights ofthird parties which may result from its use.



10

The load current per bit (IO) is set by the external resistor(REXT) as shown in the figure below.

Package Power Dissipation (PD). The maximum allow-able package power dissipation is determined as

PD(max) = (150 - TA)/RθJA.The actual package power dissipation is

PD(act) = dc(VCE • IO • 8) + (VDD • IDD).

When the load supply voltage is greater than 3 V to 5 V,considering the package power dissipating limits of thesedevices, or if PD(act) > PD(max), an external voltagereducer (VDROP) should be used.

Load Supply Voltage (VLED). These devices are de-signed to operate with driver voltage drops (VCE) of 0.4 Vto 0.7 V with LED forward voltages (VF) of 1.2 V to4.0 V. If higher voltages are dropped across the driver,package power dissipation will be increased significantly.To minimize package power dissipation, it is recom-mended to use the lowest possible load supply voltage orto set any series dropping voltage (VDROP) as

VDROP = VLED - VF - VCEwith VDROP = Io • RDROP for a single driver, or a Zenerdiode (VZ), or a series string of diodes (approximately

0.7 V per diode) for a group of drivers. If the availablevoltage source will cause unacceptable dissipation andseries resistors or diode(s) are undesirable, a regulatorsuch as the Sanken Series SAI or Series SI can be used toprovide supply voltages as low as 3.3 V.

For reference, typical LED forward voltages are:White 3.5 – 4.0 VBlue 3.0 – 4.0 VGreen 1.8 – 2.2 VYellow 2.0 – 2.1 VAmber 1.9 – 2.65 VRed 1.6 – 2.25 VInfrared 1.2 – 1.5 V

Pattern Layout. This device has separate logic-groundand power-ground terminals. If ground pattern layoutcontains large common-mode resistance, and the voltagebetween the system ground and the LATCH ENABLE orCLOCK terminals exceeds 2.5 V (because of switchingnoise), these devices may not operate correctly.

Dwg. EP-064

VLED

V DROP

VF

VCE

Applications Information

300 500 700 1 k 2 k

CURRENT-CONTROL RESISTANCE, R EXT IN OHMS

100

0100

Dwg. GP-061-1

OU

TP

UT

CU

RR

EN

T IN

mA

/BIT

5 k200 3 k

20

40

60

80

VCE = 0.7 V120

140




A6277EADimensions in Inches

(controlling dimensions)

Dimensions in Millimeters(for reference only)

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.2. Lead spacing tolerance is non-cumulative3. Lead thickness is measured at seating plane or below.4. Supplied in standard sticks/tubes of 18 devices.

0.0140.008

0.300BSC

Dwg. MA-001-20 in

0.430MAX

20

1 10

0.2800.240

0.210MAX

0.0700.045

0.015MIN

0.0220.014

0.100BSC

0.005MIN

0.1500.115

11

1.0600.980

0.3550.204

7.62BSC

Dwg. MA-001-20 mm

10.92MAX

20

1 10

7.116.10

5.33MAX

1.771.15

0.39MIN

0.5580.356

2.54BSC

0.13MIN

3.812.93

11

26.9224.89



12

A6277ELWDimensions in Inches(for reference only)

Dimensions in Millimeters(controlling dimensions)

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.2. Lead spacing tolerance is non-cumulative.3. Supplied in standard sticks/tubes of 37 devices or add “TR” to part number for tape and reel.

0° TO 8°1 2 30.020

0.013

0.0040 MIN.

0.01250.0091

0.0500.016

Dwg. MA-008-20 in

0.050BSC

20 11

0.29920.2914

0.4190.394

0.51180.4961

0.09260.1043

0° TO 8°1

20

2 30.510.33

0.10 MIN. Dwg. MA-008-20 mm

1.27BSC

110.320.23

1.270.40

7.607.40

10.6510.00

13.0012.60

2.652.35

6277 - farnell · 2018. 12. 4. · 6277 8-bit serial-input, constant-current latched led driver 7...

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