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EE 382V Spring 2015

VLSI Physical Design Automation

Prof. David Z. Pan

dpan@ece.utexas.edu

Office: POB 5.434

Lecture 1. Introduction

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What is this course for?

1. Understandable to everyone

2. Understandable to intended audience

3. Understandable to experts only, such as the speaker

4. Understandable to nobody, including the speaker

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• VLSI CAD (also known as EDA – electronic design automation) students, in particular for chip implementation (physical design)

• Circuit designers to understand how tools work behind the scene

• Process engineers to tune process that is more circuit/physical design friendly

• Mathematical/Computer Science majors who want to find tough problems to solve– Lots of VLSI physical design problems can be formulated into

combinatorial optimization problems– Actually, most CAD problems are NP-complete -> heuristics

Intended Audience

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Course Objectives

Obtain a general understanding of IC designs. Understand the process of VLSI layout design Study the basic algorithms used in layout

design of VLSI circuits. Learn about the physical design automation

techniques used in the best-known academic and commercial layout systems.

Get know recent research topics and problems.

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• Lecture Hours: MW 9:00-10:30am; Location: SZB380• Instructor: David Pan

– Email: dpan@ece.utexas.edu (best way to reach me)– Office: POB 5.434– OH: MW 1:30-2:30pm & by appointment.

• TA: Subhendu Roy, OH on T/Th 2-4pm• Class web page

– http://www.ece.utexas.edu/~dpan/EE382V_PDA

• Prerequisites– Basic understand of algorithms (EE360C)– Basic understand of VLSI (EE460R)– or consent of instructor

Course Logistics

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• Recommended books (not required)– S. K. Lim, Practical Problems in VLSI Physical Design Automation,

Springer, 2008 – A. B. Kahng, J. Lienig, I. L. Markov, J. Hu, VLSI Physical Design:

From Graph Partitioning to Timing Closure, Springer 2011– C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of

Algorithms for Physical Design Automation, Auerbach Publications, 2008

– S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific, 1999

• Algorithm book (for your reference)– T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein Introduction to

Algorithms, MIT Press, 2009 (3rd edition) – Selected papers from the literature.

Course Reader

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• Class participation: 10%– Class attendance expected (unless legitimate reasons)– Class interaction welcomed (do ask questions)

• Homework: 25%– Several home works to help you master basic concepts and

hone your problem solving ability

• Midterm: 25%– March 28 (ISPD week)

• Project: 40%– Gain direct experience and in depth study of a PD topic– Very important

Grading Policy

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• Introduction • Partitioning • Floorplanning • Placement • Global Routing • Detailed Routing • Clock and Power Routing • Emerging topics

Course Outline

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Physical Design Automation Interlock

Automation Techniques VLSI Physical Design

Graph algorithms Partition

Graph algorithms mathematical programming

Placement

Shortest path

Mathematical programming

Greedy algorithm

Routing

The most important thing often is to find the right problem formulation

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Pad Metal1 Via Metal2

I/O

Data Path

ROM/

RAM

PLA

A/D Converter

Random logic

Basic Components In VLSI Circuits

• Devices– Transistors– Logic gates and cells– Function blocks

• Interconnects– Local signals– Global signals– Clock signals– Power/ground nets

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System Specification

Chip

Manual

Automation

Large number of devices

Optimization requirements for high performance

Time-to-market competition

Power (and other) constraints

VLSI Design Cycle

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System Specification

Functional Design

Logic Design

Circuit Design

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))

VLSI Design Cycle

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Physical Design

Fabrication

Packaging

VLSI Design Cycle (cont.)

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Physical design converts a circuit description into a geometric description. This description is used to manufacture a chip. Conventional physical design cycle consists of

1 Partitioning

2Floorplanning

3Placement

4Routing

5Compaction

Physical Design

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Physical Design Process

Design Steps:Partition & ClusteringFloorplan & Placement

clk

clk clk

a

a

aPin Assignment

Global RoutingGlobal RoutingDetailed Routing

Methodology:Divide-and-Conquer

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Physical Design Cycle

Physical DesignCircuit Design

(a)

(b)

(c)

(d)

Partitioning

Floorplanning&

Placement

Routing

Compaction

Fabrication

cutline 2

cutline 1

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More than 100 million transistors

Performance driven designs

Power-constrained designs

Time-to-Market

Design cycle

High performance, high cost

…...

Complexities of Physical Design

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History 101 of Physical Design

• Born in early 60’s (board layout)• Passed teenage in 70’s (standard cell place and route)• Entered early adulthood in 80’s (over-the-cell routing)• Declared dead in late 80’s !!!• Found alive and kicking in 90’s• Physical Design (PD) has become a dominant force in

the overall design cycle– Due to the deep submicron scaling – Expand vertically with logic synthesis and interconnect

optimization, analysis…. => Design closure!– IC “Implementation” tool is about 1/3 of the overall EDA market

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Why Physical Design still Relevant?

• Many existing solutions are still very suboptimal– E.g., placement

• Interconnect dominates – No physical layout, no accurate interconnect

• More new physical and manufacturing effects pop up– Crosstalk noise, …– Manufacturability, reliability, …

• More vertical integration needed• Physical design is the KEY linking step between

higher level optimization and lower level modeling

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• This course is on core physical design (that covers every major step in details)

• More basics

• Different from my other graduate course “Optimization Issues of VLSI CAD”

• More crosscutting topics, such as DFM, interconnect, low power, reliability …

PD Courses in Context

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Moore’s Law

• The minimum transistor feature size decreases by 0.7X every three years (Electronics Magazine, Vol. 38, April 1965)

• Consequences of smaller transistors:– Faster transistor switching– More transistors per chip

• True for almost 50 years! • This year is Moore’s Law’s 50th anniversary!• More Moore, but facing lots of red brick walls

– Need smarter and more powerful CAD tools than ever

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Technology Trend and Challenges

Source:ITRS

Interconnect determines the overall performance In addition: noise, power => Design closure Furthermore: manufacturability => Manufacturing closure

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Placement Challenge

• Placement, to large extend, determines the overall interconnect

• If it sucks, no matter how well you interconnect optimization engine works, the design will suck

• Placement is a very old problem, but still have lots of room for improvement – Mixed-size (large macro blocks and small standard cells)– Optimality study shows that placement still a bottleneck– Not even to mention performance driven, and coupled with

buffering, interconnect optimizations, and so on

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Comparison with Optimal

– Capo: Based on recursive min-cut (UCLA-UMich)– Dragon: Recursive min-cut + SA refinement at each level (NWU-UCLA)– mPL: multi-level placer (UCLA)

There is significant room for improvement in placement algorithms: existing algorithms are 50-150% away from optimal!

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FloorPlacer (Mix-mode Placement)

- Many macros- data paths + dust logic- I/O constraint (area I/O or wirebond)

(source: IBM)

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Optical Proximity Correction (OPC)

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OPC-Aware Routing

More OPC friendly

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• Three types– Literature survey (one person): at most 80% out of 40% for

the total project grade– Implementation/comparison of existing PD algorithms

(typically 2-person team)– Explore new ideas (typically 2-person team)

• Project and term paper outline– Introduction and motivation– Problem statement and/or formulation– Previous works (exhaustive search)– Your approach (new ideas)– Experimental results (implement your idea and show it works

or explain why if it does not)– Summary, conclusion and future work

Class Project

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• Rough milestones for class project– Proposal by Feb. 18:

• Project team and initial proposal on what topic to work on

– First report by Mar. 11 (before spring break):• Project proposal with initial literature review

• And your ideas, plan of attack, and framework

– Second report by April 15• Comprehensive literature review

• Initial implementation results or findings

– Final project report and presentation• TBD, around the final week

– Conference submission deadlines in Spring 2015• ICCAD deadline (abstract: April 17; full paper: April 24)

• ASPDAC deadline (around early July)

Class Project

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• Possible topics– ISPD 2015 Contest topics: www.ispd.cc – ICCAD 2014 Contest topics: www.iccad.com– Suggest your own research topics

• We will talk more later

Class Project

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• A. Rajaram, D. Z. Pan and J. Hu, "Improved Algorithms for Link Based Non-tree Clock Network for Skew Variability Reduction", Proc. International Symposium on Physical Design (ISPD), San Francisco, CA, April 2005.

• M. Cho, S. Ahmed and D. Z. Pan, "TACO: Temperature Aware Clock Optimization", Proc. ACM/IEEE Int'l Conference on Computer-Aided Design (ICCAD), November, 2005 (covered by EE Times on June 19, 2006)

• Avijit Dutta, Jinkyu Lee and David Z. Pan, “Partial Functional Manipulation Based Wirelength Minimization”, Proc. International Conference on Computer Design (ICCD), Oct. 2006

• Samuel I. Ward et. al., "Keep it Straight: Teaching Placement how to Better Handle Designs with Datapaths", Proc. ACM International Symposium on Physical Design (ISPD), Napa Valley, CA, March, 2012 (Nominated for Best Paper Award)

Some Previous Class Projects

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• Please check the web site for a set of references, papers and links (will be updated frequently)– EE Times (www.eetimes.com) for recent trend/development– IEEE Explorer– ACM Digital Library– Google Scholar– ……

• MOOC!– If you need to make up some knowledge (e.g., Cormen’s

algorithm book/class)

Resources

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VLSI CAD Conferences

• Strong in Physical Design– DAC: Design Automation Conference– ICCAD: Int’l Conference on Computer-Aided Design– ASP-DAC: Asia & South Pacific Design Automation Conference– ISPD: Int’l Symposium on Physical Design

• Other Conferences– DATE: Design Automation and Test in Europe– ISLPED: Int’l Symposium on Low Power Electronics & Design– ISQED: Int’l Symposium on Quality Electronic Design– ISCAS: Int’l Symposium on Circuits and Systems– ICCD: Int’l Conference on Computer Design– ……

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VLSI/CAD Related Journals

• IEEE TCAD– IEEE Transactions on CAD of Integrated Circuits and

Systems

• IEEE TVLSI– IEEE Transactions on VLSI Systems

• ACM TODAES– ACM Transactions on Design Automation of Electronic

Systems

• IEEE TCAS (I and II)– IEEE Transactions on Circuits and Systems

• Integration, the VLSI Journal