6 G S E R D E S , P O W E R F U L D S P B L O C K S , M A C O C O M M U N I C A T I O N E N G I N E S

The LatticeECP4™ is the next generation mid-range FPGA with 6G SERDES, built-in communication engines, 4X more powerful DSP blocks, and high speed memory interfaces including DDR3. The low cost LatticeECP4 offers 66% more logic and signal processing resources than the previous gen-eration LatticeECP3™ FPGAs. The low power LatticeECP4 family is perfect for a wide range of applications, such as wireless and wireline communication, video processing, security and surveillance, industrial networking, storage, and computing.

The LatticeECP4 offers up to 250K LUTs of logic capacity and 10.6 Mbits of memory for system integration, cascadable high-performance DSP blocks for signal processing, high-speed memory interfaces including DDR3 at 1066 Mbps, and up to 1.25 Gbps LVDS performance for ADC/DAC and im-plementing high speed serial I/Os. The LatticeECP4 further enables you to build high speed systems with proven 6Gbps low power SERDES that are designed to support a number of protocols – PCI Express 2.1, Ethernet (10GbE, GbE, SGMII, XAUI & RXAUI) Serial RapidIO 2.1, and low-latency CPRI.

To accelerate the design of LatticeECP4 powered systems, Lattice will offer a number of generic and application-specific development kits, an expanding portfolio of free reference designs, and a set of economical IP suites.

FPGA Fabric Features and Capabilities Low Power, Low Cost FPGA Fabric

•Lowpower65nmprocesswith4-inputlook-uptable(LUT) fabric

•Logicdensitiesfrom30Kto250KLUTs•Upto10.6MbitsofEmbeddedBlockRAM(EBR)and

600Kbits of distributed RAM High Speed Embedded SERDES

•Up to 16 channels with data rates from 155Mbps to 6Gbps•Lessthan175mWpowerperchannelat6Gbps•SupportsPCIExpress2.1,Ethernet(10GbE,GbE,

XAUI, RXAUI, SGMII), Serial RapidIO 2.1, CPRI, SMPTE Flexible GIGA sysIO™ Buffers

•LVCMOS33/25/18/15/12,PCI•SSTL33/25/18/15&HSTL15&HSTL18•LVDS,Bus-LVDS,RSDS,MLVDS&LVPECL•1066MbpsDDR3•Upto1.25GbpsLVDS

Wide Range of Package & User I/O Options•Upto512userI/Opins•Provenlowcostwire-bondfpBGApackages•Highperformanceflip-chippackages•Densitymigrationacrossalldensities•Pb-free/RoHS-compliant

sysCLOCK™ PLL and DLL•8DLLsand8PLLsperdevice

LatticeECP4 FamilyLow Cost, Low Power FPGA with Premium Communication Engines

HIGH SPEED I/O Supports DDR3 memory (1066Mbps) interface Up to 1.25Gbps differential I/Os Supports built-in Clock Data Recovery (CDR)

MACO™ COMMUNICATION ENGINES Popular communication protocols Flexible system planner software tool Seamless SERDES, PCS & fabric interface

LatticeECP4 Features and Benefits

ADVANCED CONFIGURATION OPTIONS Configure with SPI boot Flash or parallel burst

mode Flash Protect your designs with 128-bit AES Dual-boot provides backup configuration copy TransFR™ I/O support updates while system operates

EMBEDDED SERDES 6G operation with less than 175mW power per

channel Built-in pre-emphasis and equalization Supports PCIe, Ethernet (GbE, XAUI, RXAUI &

SGMII), SMPTE, Serial RapidIO, CPRI and JESD204A Quad-based architecture with mix and match of

different protocols within a quad Single-channel granularity for 3G/HD/SD SDI Supports low latency variation CPRI links for

multi-hop RRH applications

www.latticesemi.com/ecp4

CASCADABLE DSP WITH ALU Booster logic supports unique DDR mode Pre-adder logic supports efficient symmetric FIR

filter implementation 576 cascadable 18x18 multipliers for high

performance filter and wide arithmetic functions Implement rounding and truncation functions

with 54-bit cascadable arithmetic logic unit

SERDES/PCSQuad 1

SERDES/PCSQuad 2

SERDES/PCSQuad 3

SERDES/PCSQuad 4

POWER sysDSP Blocks deliver 4X improvement in data throughput. Run DSP blocks at 2X speed (500MHz).

Pre-Engineered Source Synchronous Support implements DDR3 at 1066Mbps and generic differential interfaces up to 1.25Gbps.

JTAG

On-Chip Oscillator

sysCLOCK PLLs & DLLs for clock management.

sysMEM Embedded Block RAM (EBR) provides 18kbit dual port RAM.

Configuration Logic supports dual boot, encryption and TransFR updates.

GIGA sysIO Buffers support LVCMOS, HSTL, SSTL, LVDS and more.

Programmable Function Unit (PFU)perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions.

Embedded 6Gbps SERDES and MACO Communication Engines support CPRI, PCIe 2.1, SRIO, GbE/SGMII, 10G MACs.

S/S/Pd

MACO MACO MACO MACO

LatticeECP4 EBR SRAM (Mbits)

sysMEM™ CONFIG OPTIONS

LatticeECP4 Architecture

PROGRAMMABLE FUNCTION UNIT (PFU) BLOCK DIAGRAM

Architecture OverviewLatticeECP4 FPGAs utilize Lattice’s next generation of cost optimized transceiv-ers and a low power, low cost 65nm processFPGAarchitecture.Buildingonthe successful LatticeECP3 FPGA family, LatticeECP4 devices deliver high-perfor-mance SERDES blocks, MACO Commu-nicationEngines,POWERsysDSPblocks,embedded RAM, distributed memory, sysCLOCK PLLs, DDR3 memory interface, and GIGA sysIO buffers. LatticeECP4 devices provide a low cost, low power programmable solution for a wide variety of wireless, wireline and video processing applications.

LatticeECP4 BLOCK DIAGRAM

Carry Chain

Carry Chain

LUT4FF

FFLUT4

LUT4FF

FFLUT4

LUT4FF

FFLUT4

ToRouting

FromRouting

Slice 3

Slice 2

Slice 1

Slice 0

FF

FF

LUT4

LUT4

DUAL-BOOT AND 128-BIT AES ENCRYPTION

sysCLOCK PLL

PRE-ENGINEERED SOURCE SYNCHRONOUS INTERFACES

DDR3 (1066 Mbps) 7:1 / 8:1 LVDS, ADC/DAC

EMBEDDED CLOCK DATA RECOVERY

Single Port Dual Port Pseudo-Dual Port

16384 x 1 16384 x 1 16384 x 1

8192 x 2 8192 x 2 8192 x 2

4096 x 4 4096 x 4 4096 x 4

2048 x 9 2048 x 9 2048 x 9

1024 x 18 1024 x 18 1024 x 18

512 x 36 — 512 x 36

LatticeECP4SPI Configuration

Memory

DecryptionEngine

128-bit Key

FPGALogic

ReadDataSector 0

Sector 1

Control

Configuration A

Configuration B[[

PhaseFrequencyDetector /VoltageControl

Oscillator

Divi

der

Divi

der

Internal Feedback

ClockInput

Reset

ControlSignals

ClockFeedback

Clock Outputs

Divider

Lock Detect

Divider

Divider

Divider

Tri-StateRegister

Block

OutputRegister

Block

ISICorrection

DQS/Strobe Delay & Transition Detect& Write Clock Generation

8:1Gearbox

8:1Gearbox

FPGAFabric

InputRegister

Block

4

6

10

8

2

0

12

(Mbi

ts)

LUTs33K 95K47K 130K 190K 250K

UP TO10.6Mb

PLLCLKAlign

TrackingLogic IP

MonitorDDRRxN

PxP

VCO

RecoveredClock

Phase10

Adjust +/-

Rx Data

Premium Features in a Mid-Range FPGA

4X MORE POWERFUL sysDSP BLOCKS ~7X more performance (GMACs) reduces cost Unique pre-adder and booster logic to process 4X signals

through a DSP block Mainstream multi-antenna system (4x4 MIMO 40MHz)

realization at lower cost and power High-performance motion detection and tracking at

lower cost and power

LatticeECP4 MULTI-PROTOCOL STACK

Supports commonly used Ethernet protocols: 10 Gigabit Ethernet, 1 Gigabit Ethernet, SGMII, XAUI, RXAUI

PCI Express 2.1, SRIO 2.1 and CPRI

6Gbps SERDES WITH EMBEDDED PCS

Reliable,LowPowerSERDESinLowCostWire-bondPackages

4 to 16 SERDES Channels From 155Mbps to 6Gbps Data Range

MACO COMMUNICATION ENGINES

Hard-wired Intellectual Property blocks 4 to 16 SERDES organized in quads of 4 SERDES each PCI Express 2.1, 10 Gigabit Ethernet, Tri-Speed Ethernet

MAC (plus 2.5Gbps EMAC), and SRIO 2.1 90% lower power and cost

PCIExpress

SerialRapidIO GbE / SGMII XAUI Supported

Protocols

EmbeddedSERDESandPhysicalCodingSub-Layers(PCS)

MACOComm.Engines

ChannelAlignment

Rx LinkSynchronize

8b/10b

RX StateMachine

State MachineSoft Logic

ChannelAlignment

Rx LinkSynchronize

8b/10b

LTSSMFraming

PCIe PHYSoft Logic

Rx LinkSynchronize

8b/10b

Rx / Tx10G MAC

Rx Link Synchronize

8b/10b

Clock ToleranceCompensation

Auto Negotiation

GbE & SGMIIState Machine

Tx Rx Tx Rx Tx Rx Tx Rx

LatticeECP4 SERDES

Rx / TxTri-Speed MAC

ChannelAlignment

Clock ToleranceCompensation

XAUI State Machine

Clock ToleranceCompensation

Clock ToleranceCompensation

SERDES AND MACO COMMUNICATION ENGINES

Device# of

SERDES Channels

# of MACO Communication Engines

PCIe SRIO Tri-Speed MAC** 10G MAC

ECP4-250 16 1 1 12 2*ECP4-190 12 1 1 8 1*ECP4-130 8 1 1 4 –ECP4-95 8 1 1 4 –ECP4-50 4 1 – – –ECP4-30 4 1 – – –

* Each unused 10G MAC can be used as 4 additional Tri-Speed MACs.** Supports 2.5G Ethernet.

ECP4-30/50

PCIe 2.1 x4

Quad 1

ECP4-250

PCIe 2.1 x4

SRIO x4

Two10Gb MAC

12 Tri-SpeedMACs

Quad 4

Quad 3

Quad 2

Quad 1

ECP4-190

PCIe 2.1 x4

SRIO x4

10Gb MAC

8 Tri-SpeedMACs

Quad 3

Quad 2

Quad 1

ECP4-95/130

PCIe 2.1 x4

SRIO x44 Tri-Speed

MACs

Quad 2

Quad 16Gbps

SERDES

MACOComm

Engines

Pipeline Registers

ALU

OutputRegisters

Multipliers

Input Registers

250MHz

250MHz

500MHz

500MHz

∑ ± & + ⊕

==

250MHz

250MHz

+/- +/-

DSPCoreLogic

DSPCoreLogic

Pre-AdderLogic

BoosterLogic

Pre-AdderLogic

BoosterLogic

Pipeline Registers

ALU

OutputRegisters

Multipliers

Input Registers

250MHz

250MHz

500MHz

500MHz

∑ ± & + ⊕

==

250MHz

250MHz

+/- +/-

Copyright © 2011 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), Lattice Diamond, LatticeCORE, LatticeECP4, Reveal, sysCLOCK, sysCONFIG, sysDSP, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

November 2011Order #: I0220

Applications Support 1-800-LATTICE (528-8423)+1-503-268-8001techsupport@latticesemi.com

latticesemi.com

LatticeECP4 Family (FPGAs with SERDES, MACO Blocks, DSPs & Source Synchronous I/O)

Parameter ECP4-30 ECP4-50 ECP4-95 ECP4-130 ECP4-190 ECP4-250

LUT4s (K) 33K 47K 95K 128K 183K 241K

Embedded Memory (Mbits) 1.18 1.18 4.13 4.13 5.90 10.62

DSP Block 18x18 Multipliers 64 64 224 224 480 576

MACO Communication Engines 1 1 2 2 3 4

Maximum Available I/O 224 224 392 392 456 512

High Speed Serial I/Os6Gbps SERDES Channels 4 4 8 8 12 16

1.25Gbps CDRs 18 18 32 32 36 40

Packages & I/O / SERDES Combinations

Wire-bondPackaging6G-SR (Short Reach)

484-ball fpBGA (23 x 23 mm) 224/4 224/4

648-ball fpBGA (27 x 27 mm) 224/4 224/4 360/4 360/4

868-ball fpBGA (31 x 31 mm) 392/8 392/8

Flip ChipPackaging6G-LR (Long Reach)

676-ball fcBGA (27 x 27 mm) 224/4 224/4 392/4 392/4 392/4

900-ball fcBGA (31 x 31 mm) 392/8 392/8 456/8 512/8

1152-ball fcBGA (35 x 35 mm) 456/12 512/16

Lattice Diamond Design Software

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low power Lattice FPGA architectures. New features include the System Planner tool which allows LatticeECP4-specific MACO Commu-nication Engines and IP cores to be pre-placed for accurate and efficient resource utilization. Also added are support for the new DSP architecture, Power Calculator options for controlling LVDS outputs and SERDES channels for better accuracy, and Reveal™ hardware debugger support for controlling SERDES registers.

Design Made Simple with Advanced Design Software and IP

DIAMONDDESIGN SOFTWARE

LATTICE

Intellectual Property

Lattice offers an expanding portfolio of LatticeCORE™ IP cores to support the easy integration of commonly used functions. Lattice also offers IP Suites, a collection of related IP cores for select applications/markets at very attractive prices. In addition, Lat ticeCORE Connections Partners offer a wide range of IP. For a complete list of IP options, please visit www.latticesemi.com/ip.

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