7-1 chapter 7 - memory principles of computer architecture by m. murdocca and v. heuring © 1999 m....
TRANSCRIPT
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7-1 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring
Chapter 7: Memory
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7-2 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Chapter Contents
7.1 The Memory Hierarchy
7.2 Random Access Memory
7.3 Chip Organization
7.4 Commercial Memory Modules
7.5 Read-Only Memory
7.6 Cache Memory
7.7 Virtual Memory
7.8 Advanced Topics
7.9 Case Study: Rambus Memory
7.10 Case Study: The Intel Pentium Memory System
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7-3 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Memory Hierarchy
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7-4 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Functional Behavior of a RAM Cell
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7-5 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Simplified RAM Chip Pinout
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7-6 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Four-Word Memory with Four Bits per Word in a 2D Organization
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7-7 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Simplified Representation of the Four-Word by Four-Bit RAM
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7-8 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
2-1/2D Organization of a 64-Word by One-Bit RAM
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7-9 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by
Eight-Bit RAM
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7-10 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM
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7-11 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Single-In-Line Memory Module
• Adapted from(Texas Instruments, MOS Memory: Commercial and Military Specifications Data Book, Texas Instruments, Literature Response Center, P.O. Box 172228, Denver, Colorado, 1991.)
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7-12 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A ROM Stores Four Four-Bit Words
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7-13 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Lookup Table (LUT) Implements an Eight-Bit ALU
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7-14 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Placement of Cache in a Computer System
• The locality principle: a recently referenced memory location is likely to be referenced again (temporal locality); a neighbor of a recently referenced memory location is likely to be referenced (spatial locality).
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7-15 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
An Associative Mapping Scheme for a Cache Memory
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7-16 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Associative Mapping Example• Consider how an access to memory location (A035F014)16 is
mapped to the cache for a 232 word memory. The memory is divided into 227 blocks of 25 = 32 words per block, and the cache consists of 214 slots:
• If the addressed word is in the cache, it will be found in word (14)16 of a slot that has tag (501AF80)16, which is made up of the 27 most significant bits of the address. If the addressed word is not in the cache, then the block corresponding to tag field (501AF80)16 is brought into an available slot in the cache from the main memory, and the memory reference is then satisfied from the cache.
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7-17 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Replacement Policies
• When there are no available slots in which to place a block, a replacement policy is implemented. The replacement policy governs the choice of which slot is freed up for the new block.
• Replacement policies are used for associative and set-associative mapping schemes, and also for virtual memory.
• Least recently used (LRU)
• First-in/first-out (FIFO)
• Least frequently used (LFU)
• Random
• Optimal (used for analysis only – look backward in time and reverse-engineer the best possible strategy for a particular sequence of memory references.)
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7-18 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Direct Mapping Scheme for Cache Memory
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7-19 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Direct Mapping Example• For a direct mapped cache, each main memory block can be
mapped to only one slot, but each slot can receive more than one block. Consider how an access to memory location (A035F014)16 is mapped to the cache for a 232 word memory. The memory is divided into 227 blocks of 25 = 32 words per block, and the cache consists of 214 slots:
• If the addressed word is in the cache, it will be found in word (14)16 of slot (2F80)16, which will have a tag of (1406)16.
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7-20 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Set Associative Mapping Scheme for a Cache Memory
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7-21 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Set-Associative Mapping Example
• Consider how an access to memory location (A035F014)16 is mapped to the cache for a 232 word memory. The memory is divided into 227 blocks of 25 = 32 words per block, there are two blocks per set, and the cache consists of 214 slots:
• The leftmost 14 bits form the tag field, followed by 13 bits for the set field, followed by five bits for the word field:
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7-22 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Cache Read and Write Policies
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7-23 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Hit Ratios and Effective Access Times• Hit ratio and effective access time for single level cache:
• Hit ratios and effective access time for multi-level cache:
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7-24 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Direct Mapped Cache Example• Compute hit ratio and
effective access time for a program that executes from memory locations 48 to 95, and then loops 10 times from 15 to 31.
• The direct mapped cache has four 16-word slots, a hit time of 80 ns, and a miss time of 2500 ns. Load-through is used. The cache is initially empty.
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7-25 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Table of Events for Example Program
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7-26 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Calculation of Hit Ratio and Effective Access Time for Example Program
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7-27 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Neat Little LRU Algorithm• A sequence is shown for the Neat Little LRU Algorithm for a cache
with four slots. Main memory blocks are accessed in the sequence: 0, 2, 3, 1, 5, 4.
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7-28 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Overlays• A partition graph for a program with a main routine and three
subroutines:
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7-29 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Virtual Memory• Virtual memory is stored in a hard disk image. The physical
memory holds a small number of virtual pages in physical page frames.
• A mapping between a virtual and a physical memory:
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7-30 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Page Table• The page table maps between virtual memory and physical
memory.
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7-31 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Using the Page Table
• A virtual address is translated into a physical address:
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7-32 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Using the Page Table (cont’)
• The configuration of a page table changes as a program executes.
• Initially, the page table is empty. In the final configuration, four pages are in physical memory.
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7-33 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Segmentation
• A segmented memory allows two users to share the same word processor code, with different data spaces:
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7-34 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Fragmentation
• (a) Free area of memory after initial-ization; (b) after fragment-ation; (c) after coalescing.
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7-35 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Translation Lookaside Buffer• An example TLB holds 8 entries for a system with 32 virtual pages
and 16 page frames.
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7-36 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
3-Variable Decoder
• A conventional decoder is not extensible to large sizes because each address line drives twice as many logic gates for each added address line.
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7-37 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Tree Decoder - 3 Variables• A tree decoder is more easily extended to large sizes because
fan-in and fan-out are managed by adding deeper levels.
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7-38 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Tree Decoding – One Level at a Time
• A decoding tree for a 16-word random access memory:
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7-39 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Content Addressable Memory – Addressing
• Relationships between random access memory and content addressable memory:
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7-40 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Overview of CAM
• Source: (Foster, C. C., Content Addressable Parallel Processors, Van Nostrand Reinhold Company, 1976.)
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7-41 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Addressing Subtrees for a CAM
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7-42 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Block Diagram of Dual-Read RAM
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7-43 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Rambus Memory• Rambus technology on the Nintendo 64 motherboard (top left
and bottom right) enables cost savings over the conventional Sega Saturn motherboard design (bottom left). (Photo source: Rambus, Inc.)
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7-44 Chapter 7 - Memory
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Intel Pentium Memory System