7-things that we should know about op-amp design
DESCRIPTION
7-things that we should know about Op-amp Design. Natsem India Design’s Pvt. Ltd. 7-things that we should know about Op-amp Design. T. Srinivas. Staff Engineer Data Converters Group. 2. Fear of Op-amp. In Analog Circuit Design Course. Design Systems. Objective. - PowerPoint PPT PresentationTRANSCRIPT
1
7-things that we should know about Op-amp DesignNatsem India Design’s Pvt. Ltd.
2
7-things that we should know about Op-amp Design
T. SrinivasStaff EngineerData Converters Group.
3
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
Objective
• Op-amp is a fundamental part of Analog Circuit Design.
• Our aim is to increase your familiarity with Op-amp Design and…
Fear of Op-amp In Analog Circuit Design Course Design Systems
4
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
Contents
1. Small Signal Model of MOSFET.2. Current Mirrors.3. Gain Bandwidth Product of an Op-amp.4. Stability of an Op-amp.5. Slew-rate of an Op-amp.6. Offset of an Op-amp.7. Noise of an Op-amp.
Conclusion
5
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
THGSDSDSTHGSn
DS
THGSDSDSTHGSnDS
VVVifVVVL
WKI
VVVifVVDSVVL
WKI
)1(2
22
D
S
GTriode Region:
Saturation Region:
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4
VGS [V]
IG [A
]
0.0E+00
1.0E-04
2.0E-04
3.0E-04
4.0E-04
5.0E-04
6.0E-04
7.0E-04
0 1 2 3 4
VGS [V]
IDS
[A]
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
3.5E-05
4.0E-05
4.5E-05
5.0E-05
0 0.5 1 1.5 2 2.5 3
VDS [V]
IDS [A]
VGS1
VGS2=VGS1+0.1
VGS3=VGS2+0.1
6
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
Regions of OperationStrong inversion
VGS> VTH
Weak inversionVGS < VTH
Triode regionVDS < VGS -VTH
SaturationVDS > VGS -VTH
CTatmVq
kTVt
eeL
WII VtVnVtVSODS
DSGS
0
//
278.25
1
DSDS
THGSoxDS VVVVL
WCI
2
22 THGS
oxDS VV
LWCI
7
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
• For Designing Amplifiers, MOSFET Operating in Saturation Region is preferred [IDS depends on Input!].
• To achieve -100dB THD Vin < (VGS- VTH)*40V.
• The small signal model that we show is valid for MOSFET in Saturation Region and for Vin<< VDSAT.
THGSDSDSTHGSn
DS
THGSDSDSTHGSnDS
VVVifVVVL
WKI
VVVifVVDSVVL
WKI
)1(2
22
D
S
GTriode Region:
Saturation Region:
2m1X
2
mXConst.
2
22 inn
inTHDCnTHDCn
DS VL
WKVVVL
WKVVL
WKI
D
S
GVin
VDC
VGS=VDC+Vin
8
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
• This signal model is sufficient for first-cut hand calculations.
22 THDC
nDS VV
LWKI
VDS = VDD – IDS*R
D
S
G
VDC
R
VDD
VDC + vin
VDS = VDD – IDS*R – Iin*R inDC Vgm
inTHDCn
I
THDCn
inDS VVVL
WKVVL
WKiI*
2
2
R
g m*V
in
vout= - gm*vin*RG
S
D
vin
RgvvAC m
in
outGain *
OXGSDSDS
DSds WLCc
IIVr
32&1
CGS rds
Eff
9
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
Intrinsic Gain
rDs
g m*V
in
vout= - gm*vin*rDS
G
S
D
vin
LWV
Lwhere
V
Ig
I
VVL
WKrgGain
DSAT
DSAT
DS
m
DS
THGSn
DSm
&1)(
1
*
D
S
G
• To Increase Gain reduce VDSAT or increase length of MOSFET.
10
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
Intrinsic Bandwidth
CGSrDs
g m*V
in
G
S
D
vin
Iin
Iout
223
***
LV
Cg
gCvgIoutCvI
requirednotisMOSFETIIWhen
DSAT
GS
mT
mGST
inmGSinin
outin
Gain-Speed Product = LL
223
• To Increase Bandwidth increase VDSAT or decrease the length of MOSFET.
11
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.Gain
0
100
200
300
400
500
600
700
800
900
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDSAT[V]
Gai
n
Bandwidth
0.00E+00
2.00E+10
4.00E+10
6.00E+10
8.00E+10
1.00E+111.20E+11
1.40E+11
1.60E+11
1.80E+11
2.00E+11
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDSAT[V]
Ban
dwid
th (r
ad/s
ec)
Gain-Bandwidth Product
0.00E+00
1.00E+12
2.00E+12
3.00E+12
4.00E+12
5.00E+12
6.00E+12
7.00E+12
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDSAT[V]
GB
W (r
ad/s
ec)
L=0.5um
L=1.0um
L=1.5um L=0.5um
L=1.0um
L=1.5um
L=0.5um
L=1.0um
L=1.5um
12
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
1. Small Signal Model of MOSFET.
211 ||* DSDSm rrgGain
Example 1:VDD
VinVDC
VOUT
M1
M2 g m2*
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
2.2 2.3 2.4 2.5 2.6 2.7 2.8
VDC[V]
G
rDS1
g m1*
Vin
S
vin
rDS2
AC Gain vs. DC Gain
0
5
10
15
20
25
30
35
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
Vin [V]
Gai
nDC Gain
AC Gain
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Not Again. It doesn’t make any sense.
These are the Basic Building Blocks of Analog IC design.
VDD
10uAVOUT
M2M1
10uA
0uA0V
10uA1V
0uA
Let (W/L)1=(W/L)2 VT=0.8V, gDS=0
VOUT = 0.0V IDS2 = 0VOUT = 0.1V IDS2 = 7.5uAVOUT = 0.2V IDS2 = 10uAVOUT = 1.0V IDS2 = 10uA
Let (W/L)2=2*(W/L)1
VOUT = 1.0V IDS2 = 20uA
VOUT = 0.0V IDS2 = 0VOUT = 0.1V IDS2 = 6.75uAVOUT = 0.2V IDS2 = 9uAVOUT = 1.0V IDS2 = 9uA
M2
VDD
10uAVOUT
M1
gDS1=1e-6 S & gDS2=0;
1uA
9uA
1V
If gDS1 = gDS2 =1e-6;
IOUT=10uA VOUT= ???
VOUT=2V IOUT=???
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Small Signal AnalysisVDD
10uAVOUT
M2M1
rIN rOUT
g m2*
Vin
g m1*
Vin
G
rDS1
S
vin rDS2rIN
VOUT
rOUT
111 mDSmIN gggg
= 0
2DSOUT gg
Due to CGS we have a Pole Hereg m
2*V
in
g m1*
Vin
G
rDS1
S
vin rDS2
VOUT
CGS1 CGS2
221
1 T
GSGS
m
CCgPole
15
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Better Current Mirror Large Output resistance.VDD
VOUT
M1
M2
M3
M4
V1
V2
V1
1. M1 – M3 is the Current Mirror.
2. M4 – M2 helps in achieving high resistance.
3. Requires high turn on voltage. VOUT > V1+VDSAT2
122 .. DSDSmOUT rrgr
V1=VGS3
V2=VGS3 + VGS4
VDD
1. M1 – M3 is the Current Mirror.
2. M4 – M2 helps in achieving high resistance.
3. VOUT > V3 + VDSAT2 > 2*VDSAT
122 .. DSDSmOUT rrgr
VOUT
M1
M2
M3
M4M5
I1 I1
V1
V2
V3 V3
V1=VGS3
V2=VGS5
V3=V2 – VGS4 > VDSAT
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Wide Swing Current Mirror.There are Two Questions that we should answer.
1) How should we generate V2.
2) We know V3 = VDSAT, what is the exact value of ‘’.
VDD
VOUT
M1
M2
M3
M4M5
I1 I1
V1
V2
V3 V3
0.00E+00
1.00E+07
2.00E+07
3.00E+07
4.00E+07
5.00E+07
6.00E+07
0 0.5 1 1.5 2
Alpha
Resi
stan
ce (o
hms)
= 1.5 is fine
If M1 – M4 are of same size, for = 1.25, (W/L)5 = 1/5 (W/L).
1/5 (W/L)
W/L
W/L
W/L
W/L
W/L
17
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Example 2:
VDC
R
VDD
Vin
VOUT
RgGain m *Replace the R with MOSFET and Build an
1) Amplifier with Gain = 50
2) Amplifier with Gain of 3 (Kn=3*Kp).
VDD
Vin
VOUT
M1
M2M3
21
1
DSDS
m
gggGain
1) If gm=100*gDS Gain = 50.
2) Gain varies with Process.
VDD
Vin
VOUT
M1
M2
2
1
m
m
ggGain
1) If (W/L)2=(W/L)1 Gain = 3.
2) Gain varies with Process.
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
2. Current Mirrors.
Example 3:VDD
M2 (W/L)=2
M3 (W/L)=1
M4 (W/L)=1
10uA
20uA
150uA
M1 (W/L)=???
VGS4 + VGS3 = VGS2 + VGS1
(W/L)1 = 15.
The above loop formed by Gate-Source voltages is known as Trans-linear loop.
VDD
M2 2*(W/L)
M1 (W/L)
(a) (b)
MB1 (W/L)
MB1 (W/L)
VOUT = ?10uA
VOUT will near to VDD
M2 in Triode region
M1 in Saturation Region
19
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
3. Gain Bandwidth Product of an Op-amp.
1st order Low Pass FilterR
C
VIN VOUT
RCtINOUT
ININ
INOUT
eVtV
thenInputstepDCs
VVIf
sVsRC
sV
/1)(
,
)(1
1)(
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1 10 100 1000 10000 100000
freq
mag(VOUT)
Phase (VOUT)
0
0.2
0.4
0.6
0.8
1
1.2
3.00E-03 3.20E-03 3.40E-03 3.60E-03 3.80E-03 4.00E-03
time(sec)
[vol
ts]
VIN
VOUT
sec/1ln1)(
)()(
radTs
BW
VTsVV
OUT
OUTOUT
20
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
3. Gain Bandwidth Product of an Op-amp.
Op-amp in Feed-back.
+ -VIN VOUT
GBWAs
A0
0
1
)()(
11
)(
)(
11
11)(
)(
0
2
..
10
0
00
0
GBWAifVtV
eA
AVtV
thens
VsVIf
AFor
GBWsA
AsVsV
INOUT
Source
GBWt
Source
INOUT
ININ
IN
OUT
sec/1ln1 radTs
GBW
Amplifier GBW required to settle in the given time (Ts) and with in given error ().
21
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
3. Gain Bandwidth Product of an Op-amp.
Example 4:
+ -VIN VOUT
GBWAs
A0
0
1
Design a Amplifier with Gain of 4, operating at 100MHz and it should settle with 10-bit accuracy for a full-scale output of 1V.
99975.0
9995.02111
1
21
11..
0
0
2
1
SourceSource
eA
ASource
GBWt
Source
sec510025.04 nTsMHzfGain CLK
GHzGBWdBKA
184160
22
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
4. Stability of an Op-amp.
• We use simple design technique to deal with stability issues.
• This approach is sufficient to deal with most of the circuits and systems.
VIN = 1V
VOUT
I Designed an Oscillator.
Phase Margin is not enough.
Poles are not in the right location.
Lets Change some W/L’s and see.
23
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
4. Stability of an Op-amp.Two-Stage Amplifier
VN VP
VDD
M1 M2
M3 M4
M5
I1 I2
VOUT
CC
CL
Poles
g mi. v I
N
g dsi
sC1
g mo.
v1
g dso
sCL
v1sCC VOUTvIN
55
514221
;;;
DSdsommo
GSDSDSdsimmmi
ggggCCgggggg
)(.)(
)()(
)()()(.)(
)()(
112
112
1
CCCCCCsCgsggsCgg
sVsV
CCCCCCsCgCCgCCgsggsCgg
sVsV
CLCLCmodsidso
Cmomi
IN
OUT
CLCLCmoCdsoLCdsidsidso
Cmomi
IN
OUT
V V*gm5
VOUTVOUT=0
24
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
4. Stability of an Op-amp.Two-Stage Amplifier
C
mo
CLL
mo
C
mi
dsodsi
momi
IN
OUT
momi
CLCL
mi
C
mo
C
dsodsi
CLCL
dsodsi
Cmo
mo
C
dsodsi
momi
IN
OUT
Cgz
CCCCCgf
Cgf
ggggAWhere
ffAs
fAs
zsA
sVsV
ggCCCCCCAs
gCAs
gCsA
ggCCCCCCs
ggCgs
gCs
gggg
sVsV
111
210
21
02
1
0
10
11020
0
112
&/
,,1
1
)()(
)(1
1
1
1
)()(
VIN
VOUT
21
02
1
0
10
1
1
ffAs
fAs
zsA
VP
VN
Op-amp in Feedback should be stable.
25
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
4. Stability of an Op-amp.Two-Stage Amplifier- Condition for Maximally flat response.
VIN
VOUT
21
02
1
0
10
1
1
ffAs
fAs
zsA
VP
VN
21
2
1
0
0
21
02
1
0
0
01
..1
11)(
)(
1
1&:1
ffs
fsA
AsVsV
ffAs
fAs
AA
AFrequencyHighVeryatisZAssumeCase
IN
OUT
Equate it to 2nd order Butterworth equation.
C
mi
C
mi
L
mo
nn
nn
CgBandwidthand
Cg
Cg
ffffwfw
ws
ws
ffs
fs
.2.2
.2.11;
.12
21
1
..1
1
1221
2
1
2
21
2
1
CLL
mi
C
mo CCCg
Cg
fz
*55
*5 21
To satisfy Assumption, We use the following rule of thumb.
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
4. Stability of an Op-amp.
Example 5:
VIN
VOUT
21
02
1
0
0
1ffAs
fAs
A
VP
VN
Design a Amplifier with Gain of 2, operating at 1MHz and when 1V input is applied output should settle with in 2V ± 2mV. [A0=1e7]
sec/663.27**2
sec/663.2731
1ln1
sec5.01,5.02
12
1
radefCgf
radeeTsC
gf
TsMHzfGain
L
mo
C
mi
CLK
0.0
0.5
1.0
1.5
2.0
2.5
0.0E+00 1.0E-07 2.0E-07 3.0E-07 4.0E-07 5.0E-07
Time [sec]
Out
[V]
-6.0E-03
-5.0E-03
-4.0E-03
-3.0E-03
-2.0E-03
-1.0E-03
0.0E+00
1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50
Mx [f2=Mx*beta*f1)
Erro
r[V]
27
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
VIN = 2V
VOUT = 2V
VDD = 5V
M1 M2
M3 M4
M5
I1 I2
VOUT
CC
CL
2V2V
4V
VIN = 3V
3V2V
3.8
3V3V
4V
2V
3V
VOUT = 3V
Linear system
Slew-rate limited
1V
2V
3V
A Slew-rate limited system will cause non-linearity.
28
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
• Often in switched capacitor circuits, output stage current limitation leads to op-amp slewing.
• In continuous time circuits where we have to drive resistor loads, output stage current limitation leads to non-linearity.
VIN = 2V
1
2
1 2
VOUT
VIN = 2V
Output Stage current limited
Output Stage can supply huge current
29
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
• Class-AB output stage should be used when driving resistor loads and some switched capacitor circuits.
• Class-AB input stage can be employed to reduce power.
VPVN
VDD = 5V
M1 M2
M3 M4
M11
I1
VOUTCC
CL
I2 I2
M6
M5
CC
M7M8
M9 M10
M12
Two-stage op-amp with class-AB output stage
30
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
Design Considerations for Slewrate (Switched capacitor Circuits).
.2
&)(
DifffullyforVVgI
GBWSR
CgGBW
CISRSlewrate
DSATDSAT
m
C
m
C
TCLK
TCLK/2
TSettleTSlew
settleslewCLK
CLKCLK TTT
fT
2&1
SRVTthenTTif
swingoutputMaximumVTSR
SWGCLKCLKslew
SWGslew
22
.
1ln1
2)1(
1ln1
GBWT
GBWT
CLK
settle
DSAT
SWG
DSAT
SWG
DSATSWG
VV
VV
getweVGBW
SRngsubstitutiVSR
GBWThus
1ln
1ln11
31
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
Example 6:1 2
1
2 1
VIN
VOUT
2
1 CL
CS
CF
VDD = 5V
M1 M2
M3 M4
I1
I2 I2
M6M5
M7 M82.5V
Design a Amplifier with Gain of 2 for 10-bit ADC, operating at clock frequency of 1MHz with a Maximum input amplitude of 1V. Assume CF=1pF and CL=1pF.
32
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.
Example 6:
CL
CF
CPCS
vIN
vOUT
gm*v
1
g DS
v1
FSP
FPSLLeff
FSP
F
m
Leff
m
F
F
S
IN
OUT
CCCCCCCC
CCCCWhere
gC
s
gCs
CC
svsv
)(&
1
1
)()(
Leff
F
settle
F
m
Leff
m
ptIN
ININ
CC
TGBWiserrorwithsettletorequiredGBW
CgzGBW
CgpWhere
ezp
CFCSVtVoutthen
sVSvIf
.1ln
.1''
&.
11)()( .
33
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.Example 6:
MHze
GBWusVe
SRthususT
mVVAssume
pFCpFCmADCbitVVVInpMax
pFCCAssumepFCCGain
CLK
DSAT
FS
SWG
LeffPFS
1365.0*517.0**2
7*3&/2.85.0*483.0
2487.0&1
483.066.612.7
66.6100
;3/11,297.010,21.
6.10,2*22
6
What is this
-1.0E-03-9.0E-04-8.0E-04-7.0E-04-6.0E-04-5.0E-04-4.0E-04-3.0E-04-2.0E-04-1.0E-040.0E+00
0 0.2 0.4 0.6 0.8 1
Vin [V]
Erro
r in
Out
put [
V]
34
National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.Example 6:Op-amp Can’t supply Infinite current.
vIN
CL
CF
CPCS
vOUT
gm*v
1
g DS
v1
MHzGBWusVSRnewThusV
VCCC
CCVV
CLVCFVknowWeat
CPAssume
SWG
INFSL
FSINOUT
14&/953.04.24.02
4.0||
||)0(
0)(,0)(,0
;0
2
-3.0E-04
-2.5E-04
-2.0E-04
-1.5E-04
-1.0E-04
-5.0E-05
0.0E+00
0 0.2 0.4 0.6 0.8 1Vin [V]
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
5. Slewrate of an Op-amp.Example 7:
Below op-amp should be designed for a Slewrate of 6V/us, what should be the input stage tail current if the op-amp is folded cascode op-amp.
‘VIP, VIN’ forms fully differential signals (2VPP) with ‘VCM’ as common mode.
VCM=1V
VIP
VIN
10pF
10pF
1pF
1pF
Parasitic Caps.
Minimum Tail Current = 12uA.
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6. Offset of an Op-amp.
1. Systematic Offset:
20uA 100uA
VDD = 5V
M1 M2
M3 M4
M5
VOUT
CC
CL
5.3u/1.5u10*15u/1.5u
15u/1.5u
10uA 10uA
2.5V
Case 1: VDSAT and Length of M3-M4 & M5 are same.
Offset=48uV
Case 2: VDSAT of M3-M4 & M5 is same but Length is different
Offset=715uV
10*5u/0.5u40*15u/1.5u
Case 3: Length of M3-M4 & M5 is same but VDSAT is different
Offset=718uV
0.00E+00
1.00E-04
2.00E-04
3.00E-04
4.00E-04
5.00E-04
6.00E-04
7.00E-04
8.00E-04
Case1 Case2 Case3
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
6. Offset of an Op-amp.
2. Random Offset : Due to Process Variations
100uA
VDD = 5V
M1 M2
M3 M4
M5
VOUT
CC
M6 M7
V4
V2
V5
V7
20uA
Process steps like Photolithography, Etching and Deposition are not uniform.
Values of V1,V2, V3 depends on the sigma of the process. Normally they will be in the order of ‘mV’.
Proper layout [Common-Centroid Layout, proximity matching] techniques can reduce the mismatch, thus Offset.
Can a designer play a role in reducing the over-all Offset.
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6. Offset of an Op-amp.
2. Random Offset : Due to Process Variations
V5=(gm7*V7/gm5)
V7
100uA + gm7*V7
VDD = 5V
M1 M2
M3 M4
M5
VOUT
CC
M6 M7
20uA
VIN
Input Referred Offset Due to: VB2 & V5
100uA
VIN + V5/A1
5
775
1
*1
m
m
gg
VVA
OffsetreffredInput
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
6. Offset of an Op-amp.
2. Random Offset : Due to Process VariationsInput Referred Offset Due to: V2 & V4
2
442 *
m
m
ggVVOffsetreffredInput
VDD = 5V
M1 M2
M3 M4
M5
VOUT
CC
M6 M7
V4
20uA
VIN
10uA + gm4*V4
VIN+(gm4/gm2)*V4
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
6. Offset of an Op-amp.
2. Random Offset : Due to Process Variations
2
442
75
75
12
442
*
1*
m
m
mm
m
ggVVOffsetreffredInputTotal
VggV
AggVVOffsetreffredInputTotal
Design M1-M2 (Differential Pair) and M3-M4 (Current Mirror) Carefully.
• Decrease gm4 (For given ‘I’ Increase VDSAT for Current Mirrors).
• Increase gm2 (For given ‘I’ Decrease VDSAT for Differential pair).
To reduce V2 and V4, use Large devices (Large L and Large W). Mismatch is inversely proportional to the Area of the MOSFET.
)(mVBWLAVX
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
Types of “Noise”• Interference
– Cross talk, Clock Coupling…– Supply Noise.Taken Care by proper design (Shielding,
Differential circuits, etc…)
• Device Noise– Thermal Noise (Fundamental).– Process related (1/f noise).
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
Thermal Noise:• Dissipative elements (resistors, MOSFET’s, …)• Random fluctuations of v(t) of i(t).• White noise with zero mean.
Resistor MOS Noise (Strong inversion)
*
R
22 4 VfkTRvn
2nv
2ni
22
22
3838
AfkTgi
AfgggkTi
mn
mbdsmn
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
kT/C Noise (Resistor):
rms
out
nout
n
VCkT
CkTRCRC
CRkTVout
f
RCf
RCkTRffVVout
RCkTRfv
sRCfV
HzVkTRv
222tan.2
21
124)(
114)(
11)(
/4
0
12
2
02
22
2
0
2
22
22
22
R
*
R2
nv
C C
2outv
100n
F
1K 100K
Case 1: Case 2:
1.0E-14
1.0E-13
1.0E-12
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-03 1.0E-01 1.0E+01 1.0E+03 1.0E+05 1.0E+07
Freq [Hz]
Noi
se D
esni
sty
[V-s
qrt(
Hz)
]
100n
F
1K
100KTotal Noise=200nV
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7. Noise of an Op-amp.
kT/C Noise (Op-amp):VDD = 5V
M1M2
M3 M4
M5
VOUT
CC
MB1 MB2
VPVN in1
2 in22
in42in3
2
Noise Analysis is Similar to offset Analysis
We can neglect the noise due to M5 & MBX.
Assume gm1=gm2 & gm3=gm4
Calculating the input referred noise.
HzVgg
gmkTv
g
kTg
g
kTg
g
kTg
g
kTgv
HzVkTgi
m
mn
m
m
m
m
m
m
m
m
n
mn
/113
16
38
38
38
38
/38
2
1
32
22
4
22
3
22
1
22
22
22
vn2
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
kT/C Noise (Op-amp):
vn2
A(s) Vout
1
32
1
1
3
12
0
22
2
1
1
3
12
22
2
1341
4
13
161)(
1
13
161
)(1)()(
m
m
C
m
C
m
m
m
m
C
m
m
mn
gg
CkTVout
gC
gg
gkT
ffVoutVout
gC
gg
gkT
vsA
sAfVout
1
0
0
1)(
m
C
gCAs
AsA
For =1, CC=10pF and gm1=gm3=80uS
Noise at the output VoutRMS=32uV.
1/f - noise is suppressed by assigning kf=0
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
10 100 1000 10000 100000 1000000 1E+07 1E+08 1E+09
freq [Hz]
Out
put N
oise
Des
nity
[V/s
qrt(H
z)]
Output Noise
Total Noise=40uV
Caution: RHS Zero is neglect for calculations, for a poor design it will increase the total output - noise drastically.
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
1/f Noise (‘Fake’ Noise):
• Caused by traps in semiconductor material– Due to contamination or crystal defects
• Has a 1/f power spectral density
• Figure of Merit is called ‘Kf’ and Kf=A/ToxB.• Kf is process dependent.• For TOX>900A, NMOS(Kf) > PMOS(Kf). So PMOS is less
noisy.
2fi
lo
hi
OX
Dff
f OX
DffTOTAL
OX
Dff
ff
CI
LK
ff
CI
LK
i
ff
CI
LK
i
hi
lo
ln222
22
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
7. Noise of an Op-amp.
1/f Noise (‘Fake’ Noise):
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
0.01 0.1 1 10 100 1000 10000
freq (Hz)
Nois
e De
ssity
[A/s
qrt(H
z)]
1V
1V
W/L
W/L=35u/1u
W/L=70u/2u
W/L=140u/1u
Kf=1.36e-27, IDS=500uA
flo=1Hz, fhi=1MHz, Tox=1250A
W/L=140u/1u
nArmsiff
CI
LK
i fTOTALlo
hi
OX
DffTOTAL 65ln2
2
IRMS=40nA
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CONCLUSION
• I hope the topics covered would be useful as a starting point and help you to extend the concepts to system level issues.
• I express my gratitude to following people:– Inventors of Google.– My Professors at IIT Madras.– For Natsem India and RVCE.– For SANYO Japan.
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National Semiconductor Corporation Confidential7-things that we should know about Op-amp DesignData Converters Group, India.
About Author
Area of Interest:Analog/Mixed-signal Integrated Circuit Design, with focus on Data converters.
Education:M.Tech, Microelectronics and VLSI Design, IIT Madras, Chennai, 2001.B.Tech, Electronics & Communications, S.V University, Tirupati, 1999.
Work Experience Associated with SANYO LSI, India (Feb ‘01 - April ‘05). Associated with Natsem, India (May ‘05 - Present).
Design Experience:Multi-stage rail-to-rail operational amplifiers, Switched capacitor Circuits.Architectures for 20-bit/24-bit ADC/DAC.
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