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Overlay Control Strategy for 45/32nm RD and Production Ramp Up

Tuan-Yen Yua;Jun-Hung Lina;Yong-Fa Huanga;Chien-Hao Chen a;Chun-Chi Yua; Chin-Chou Kevin Huangb;Chien-Jen Huangb, David Tienb

a United Microelectronics Corp. (UMC); Tainan,Taiwan, R.O.C.

b KLA-Tencor Corporation; 1 Technology Drive, Milpitas, CA 95035, U.S.A.

ABSTRACT The tight overlay budgets required for 45nm and beyond makes overlay control a very important topic. High order overlay control (HOC) is becoming an essential methodology to remove the immersion induced overlay signatures. However, to implement the high order control into dynamic APC system requires FA infrastructure modification and a stable mass production environment. How to achieve the overlay requirement before the APC-HOC system becomes available is important for RD environment and for product early ramp up phase. In this paper authors would like to demonstrate a field-by-field correction (FxFc) or correction per exposure (CPE) methodology to improve high order overlay signature without changing current APC-linear control system. Keywords: overlay metrology, high order, FxFc, CPE, APC, process control.

1. INTRODUCTION High order overlay component has been becoming a significant factor in 45nm or beyond for overlay control1-4. Lithography engineer could improve the high order overlay component by implementing scanner high order alignment or zone alignment while wafer was on scanner stages. However, scanner throughput reduction is the price to be paid. Many studies have been pointing to high order control (HOC) to satisfy the tighter overlay control in the mass production environment. Automatic process control (APC) then is essential requirement for production HOC. However, to implement APC-HOC requires (1) mature process condition and (2) extensive modifications of factory automation (FA) system. The critical production ramp-up phase is not mature (by definition), and extensive FA modifications are always painful. In this paper, the authors demonstrate a methodology that is effective, independent of these two conditions. The field-by-field correction (FxFc) or so called correction per exposure (CPE) method has been shown to produce significant overlay control results5, without any APC or FA changes from traditional linear control. The simplest FxFc method is to use raw overlay data from every field of the wafer and generating a FxFc lookup table, then send and store the lookup table into scanner for a period of time until the FxFc table is out of date. Problems for this “raw overlay data” are: (1) it requires all fields to be measured, (2) it includes linear systematic component which is to be corrected by the current APC, and (3) it requires high frequency update in a range from every few lots to once per week. To search for improvement for the “raw overlay data” FxFc problems, authors investigated an alternative FxFc method by analyzing non-linear high order signature instead of the “raw overlay data.” The alternative “non-linear high order signature” FxFc method still requires every field in the wafer to be measured. The authors’ goal is to (1) provide a significant and reliable correction for production lots, (2) as early as possible in the production ramp cycle, (3) while maintaining current APC-linear correction system, and (4) minimizing the frequency of updating the FxFc lookup table. While investigating the feasibility of “non-linear high order signature” FxFc method, two fundamental questions must be answered: (1) the number of lots required to generate a reliable signature lookup table, and (2) the frequency with which the lookup table must be refreshed/updated. These questions will be answered in this paper through a systematic long term data study.

Metrology, Inspection, and Process Control for Microlithography XXIV, edited by Christopher J. Raymond, Proc. of SPIE Vol. 7638, 76382K · © 2010 SPIE · CCC code: 0277-786X/10/$18 · doi: 10.1117/12.846569

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2. WAFER PROCESS AND METROLOGY SETUP Wafers from front end of line (FEOL) critical layer based on 32nm technology node and processed in a 1.35NA immersion scanner. Multiple wafers were measured in each lot. Overlay data was measured by KLA-Tencor Archer system with every field in the wafer for a time period of more than 2 months. Overlay mark was positioned at four corners of the field and it was a grating based AIM mark. Figure 1 shows the metrology setup conditions.

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Figure 1: Lots measured from time period of > 2 months, multiple wafers per lot, all fields per wafer, four corners per field. AIM overlay mark measured by KLA-Tencor Archer system.

3. DATA PROCESSING PROCEDURE 3.1 Daat Collection Strategy

Data was collected over more than two months’ time, to encompass multiple scanner PM’s. Multiple wafers per lot were measured, to make sure that both chucks of dual-stage scanner were represented (each chuck is known to have its own signature1). To simplify the data presentation throughout this paper, only data from the odd chuck is presented.

3.2 Source of Variance Analysis

There are many factors co-mingled together into a single overlay value dataset. The first step is to perform source of variance (SOV) analysis to understand the major overlay non-linear contributors. Detailed description of the SOV analysis method can be found from other references2, 4, which will not be covered in this paper. By utilizing KLA-Tencor KT-Analyzer, one can rapidly perform the SOV analysis. Instead of searching overlay problem from linear residual value and residual vector plot, the SOV technique allows one to promptly characterize overlay control problems and decide a course of action. Linear overlay residual for each wafer was decomposed into 3 major contributors through SOV: wafer non-linear systematic component, field non-linear systematic component, and un-modeled random component as shown in Figure 2 which covered Y-directional overlay linear residual for a duration of between two scanner-PMs. (Y-directional data is shown because it is larger than X-directional error and therefore provides larger opportunity for improvement. See also Fig. 6 for comparison with X-directional data). Since only 4 points are available in each field, field overlay was well modeled by 3 field terms: field translation, magnification and rotation terms. Hence field level component contributed only a very little portion in the linear residual. It was obvious that wafer level component and un-modeled component were the two major linear residual contributors. Although un-modeled random component was a significant factor for improving overlay in this case, its improvement usually has to be accomplished from hardware upgrade or repair which is outside the scope of this study. The remaining significant portion for linear residual improvement then was the wafer level non-liner systematic component, which is the scope of this paper.



Figure 2: Y-directional linear overlay residual was decomposed into three major components: Wafer and Field non-

linear systematic components and un-modeled random component. The wafer non-linear systematic component is the target component to be improved by the FxFc method.

3.3 Calculate common wafer level signature

The SOV plot shows a significant linear overlay residual was contributed by wafer level component. The next question is how to reduce the wafer level component. High order process control (HOPC) is commonly considered as an effective method for production. In many cases, the HOPC requires data from approximately only 1/3 of all the fields. Comparing to the FxFc method, the HOPC method provides a better throughput for metrology. However, the HOPC is limited to high order signature that can be mathematically modeled and usually is a polynomial equation up to 5th order. In contrast, the FxFc method considers overlay data modeling individually for each field. Usually overlay in each field is modeled by two translation terms or adding additional four field magnification and rotation terms. Since the FxFc does not need mathematical bondage between neighboring fields and treats each field as individual modeling, it once has a nick name called “super high order correction.” As one can guess the price to pay for this method is its throughput slow down from metrology concern.

By knowing the advantages and disadvantages between the HOPC and FxFc methods, maybe the best approach for production overlay control is to utilize the advantages of each method. In the other words, if one can characterize and correct the static common overlay signature which extends beyond the HOPC modeling capability by FxFc method and perform dynamic lot-to-lot overlay control by the HOPC method, overlay should achieve the optimal performance.

Before the APC-HOPC becoming available, implement FxFc method is the first step for high order component improvement. One can calculate the wafer level FxFc overlay signature by using raw overlay data. However, the raw data method includes linear component which is supposed to be taking care by the APC-linear control and could results double correction. To avoid double linear correction, the author removed linear components from each lot and considered only on the non-linear overlay signature as shown in Figure 3a. By taking average of all lots signature at the same field, one can obtain the common wafer signatures as shown in Figure 3b. This common signature was then converted into a FxFc lookup table and stored into scanner as a static correction file.

Definitely it is not practical in production to gather a large number of lots to generate a common signature. Then the question becomes: how many lots are required to generate a reliable common signature? The answer will be answered in the next section. Without a handy utility, it seems a very time consuming job to obtain the common non-linear wafer signature. Fortunately K-T Analyzer provides an easy to use FxFc feature that allows user to perform such an analysis and common signature creation in just like steps 1-2-3 as shown in Figure 4.

3.4 Correction simulation

The final step in the data process is to perform simulation to estimate the FxFc improvement. By removing the common signature, one expects to see the overlay linear residual to be improved. Once the common signature no longer valid the results of FxFc correction could turn the linear residual to be worse. In such a case, it indicates it is time to update the common signature.

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Figure 3a: Lot-to-lot overlay linear residual signature as shown in a composite plot.

Figure 3b: Red vectors represent the common wafer level non-linear signature by taking the average of all the lots in each field.

Figure 4: FxFc lookup table can be easily generated by using K-T Analyzer’s FxFc file creator. The above figure shows how a FxFc file was generated by the linear residual method, from an average of four lots.



4. RESULTS As mentioned in earlier section, two fundamental questions have to be answers in implementing the FxFc static high order correction method: (1) How many lots to be enough for getting the optimal FxFc lookup table? (2) How frequent the FxFc lookup table has to be update? The following results will provide the answer for this study case. 4.1 FxFc signature from different lot combination

Common signature can be created simplify from one single wafer. However, it will be too risky to use just one single wafer to present a common signature for a long term static overlay correction. It would be more statistically robust to characterize common signature by multiple wafers per lot. Wafers in each lot were sorted into odd and even chucks to distinct the difference between the two stages. The common non-linear wafer signatures shown in Figure 5 were from odd chuck only. It can also be observed from Figure 5 between the four signature plots that signatures in wafer edge fields were subjected to more fluctuation than the wafer center fields. However, when the signatures averaged from more lots, it showed even the wafer edge fields getting converged or stabilized.

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Figure 5: Common non-linear wafer signatures were generated based on (a) 1st lot after scanner PM (b) 1st 2 lots after scanner PM, (c) 1st 3 lots after scanner PM (d) 1st 4 lots after scanner PM. Signatures in wafer edge fields subjected more fluctuation than wafer center fields.



4.2 How many lots to be enough for getting optimal common signature

Figure 6 shows the wafer non-linear systematic component improvement by removing the common signatures. FxFc lookup table created from first lot after scanner PM provided wafer level overlay improvement for approximately 50%. As expected, FxFc file obtains from averaging multi-lots gave better static correction results. It was obvious that common signature generated from average of 3 lots was sufficient to provide optimal improvement for wafer level non-linear component. Figure 7 shows a nearly 70% y-directional wafer non-linear systematic improvement could be achieved by removing the common signature from simulation.

Figure 6: Wafer non-linear systematic component improvement by removing common signatures generated from increasing lots. It shows Y-overlay improvement stabilized by using common signature from the average of first 3 lots after PM.

Figure 7: Wafer y-direction non-linear systematic component was significantly improved in the simulation for near 70% after removing common signature which was created from averaging first 3 lots.

Wafer level non-linear component improvement

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4.3 The frequency of FxFc update

The second question for implementing the FxFc method is how long the FxFc lookup table can stand for good or how frequent the FxFc file has to be updated? From Figure 8 one can find out that FxFc common signature file could stay for good for a long period before expired after next scanner PM was conducted. An up to 3nm positive linear residual improvement was observed for applying the static correction using the common signature FxFc file. However, once the scanner PM was conducted, the common signature became invalid and provided non-improvement but made the overlay results even worse.

As expected the scanner PM could potentially change common wafer overlay signature, a new updated FxFc file was required to provide positive improvement. Figure 9 shows similar improvement by using updated common signature file as earlier period. Further more, one can observed the scanner PM helped the reduction of un-modeled random component as well.

Figure 8: FxFc common signature file stayed good until expired after scanner PM. (Positive = improvement, Zero = No Improvement, Negative = Degradation.)

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Figure 9: By updating new FxFc common signatures, wafer y-direction non-linear systematic residual was improved as observed as expected.

5. SUMMARY The static “non-linear high order” FxFc correction methodology was proofed to provide effective overlay improvement. In some cases, it could provide up to 3nm linear residual improvement. Common signature FxFc file from an average of minimum first 3 lots would provide most effective correction results and it would stay good for positive improvement until expired after next PM. The above recommendations on correction frequency may need to be varied based on the technology and specific wafers process conditions. However, this study provides a systematic approach for evaluating the efficiency of FxFc methodology and the determination of number of lots for obtaining common signature and updating frequency.

REFERENCES

[1] Bo Yun Hsueh, George KC Huang, Chun-Chi Yu, Chin-Chou Kevin Huang, Chien-Jen Huang, James Manka, and David Tien, “Sampling Strategy: Optimization and Correction for High Order Overlay Control for 45nm Process Node,” Proc. SPIE 2009, 7272-121

[2] Bo Yun Hsueh, George KC Huang, Chun-Chi Yu, Jerry Hsu, Chin-Chou Kevin Huang, Chien-Jen Huang, and David Tien, “High order correction and sampling strategy for 45nm immersion lithography overlay control,” Proc. SPIE 2008, 6922-99.

[3] Yu-Hao Shih, George KC Huang, Chun-Chi Yu, Mike Adel, Chin-Chou Kevin Huang, Pavel Izikson, Elyakim Kassel, Sameer Mathur, Chien-Jen Huang, David Tien, Yosef Avrahamov, “45nm design rule overlay metrology on immersion lithography processes,” Proc. SPIE 2007, 6518-106.

[4] Chin-Chou K. Huang and David Tien, “Overlay goes high order”, Microlithography World, (Dec, 2008). [5] B. Eichelberger, K. O’Brien, J. Manka, J. Robinson, D. Tien, A. Minvielle, L. Singh, J. Schefske, J. Reiss, E. Kent,

and T. Manchester, “Advanced modeling strategies to improve overlay control for 32nm lithography processes,” Proc. SPIE 2009, 7272-115.

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