796 ieee transactions on components and … contact micro-springs in ... eugene m. chow, member,...

796 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 29, NO. 4, DECEMBER 2006

Pressure Contact Micro-Springs inSmall Pitch Flip-Chip Packages

Eugene M. Chow, Member, IEEE, Christopher Chua, Member, IEEE, Thomas Hantschel,Koenraad Van Schuylenbergh, and David K. Fork, Member, IEEE

Abstract—This work investigates electrical pressure contactsbased on a micro-spring with orders of magnitude smaller pitchand force than conventional pressure contacts. The springsare beams which curl out of the surface and can be used forwafer-scale testing and packaging. They are fabricated with stan-dard wafer-scale thin film techniques and have been previouslydemonstrated on active silicon integrated circuits. Single springsand their electrical contacts are characterized with force versuscompression and compression versus resistance measurements.Flip-chip packages with hundreds of micro-springs were assem-bled with 20- m pad pitch and 40- m spring pitch. Each springoperates with a force of approximately 0.01 g and contacts a goldpad. These packages are shown to have stable resistance valuesduring both in-situ thermocycle (0 C to 125 C) and humiditytesting (60 C at 95% RH). Spring electrical contacts inside thepackage are shown not to degrade during environmental testingthrough measurements of four-wire resistance and electrical iso-lation structures. High-speed glitch measurements are performedto confirm that the pressure contact does not have intermittentopens during thermocycling. These results suggest that a low-forcesolder-free pressure spring contact is a viable technology for nextgeneration flip-chip packaging.

Index Terms—Flip-chip, gold contacts, high-density, micro-spring, pressure contact, reliability, solder-free, spring, wafer-scaletesting.

I. INTRODUCTION AND MOTIVATION

WHILE flip-chip is leading high performance packaging,there are still many challenges for the technology. Cur-

rent flip-chip interconnects, such as solder balls, gold bumps,and conductive adhesives, all have very limited compliance.Without adequate compliance, thermal expansion mismatcheswithin the package between the silicon integrated circuit (IC)and the package substrate leads to failures during thermocycletesting. This is particularly important for large die flip-chipon organic board applications such as memory. Processorsare moving towards low-k dielectrics which can be damagedby thermal expansion mismatches, increasing the demand forcompliance. Interposers and added thermal expansion matched

Manuscript received March 21, 2005; revised December 12, 2005. This workwas recommended for publication by Associate Editor B. Courtois upon evalu-ation of the reviewers’ comments.

E. M. Chow, C. Chua, and D. Fork are with the Palo Alto ResearchCenter (PARC), 3333 Coyote Hill Road, Palo Alto, CA 94304 USA (e-mail:[email protected]).

T. Hantschel is with IMEC, Leuven B-3001 Belgium.K. Van Schuylenbergh is with the Department of Physics, University of

Antwerp, Wilrijk B-2610 Belgium.Digital Object Identifier 10.1109/TCAPT.2006.885959

layers help to reduce the relative movement near the flip-chipinterconnects, but they also increase package height and size.The demands of lead-free solder and the associated high reflowtemperature exacerbates the problem.

Other challenges for flip-chip include pitch, testing, andknown-good-die. Increases in the number of signals and con-tinuing die size shrinks have increased the demand for higherpin counts and smaller pitch in markets such as display driverICs for chip-on-glass and microprocessors for chip-in-package.Chip testing and thus the cost of known-good-die remainsexpensive, as the industry relies on expensive probe cards thatcannot probe an entire wafer. Finally, the recent popularityof portable electronics has driven more integration and moremultichip system-in-package solutions [1], [2]. The economicsof multi-chip integration would greatly benefit from a re-work-able interconnect technology, which current approaches suchas solder do not readily offer.

We are developing a spring-based flip-chip interconnect toaddress these challenges. A metal cantilever with a designedstress gradient is released to form a curved beam that acts asa conductive spring. The inherent compliance of the spring ab-sorbs thermal mismatches and mitigates associated problemssuch as low-k dielectric failure. The added compliance can in-crease reliability for the same chip size, or accommodate largerthermal runout and package larger chips. A compliant springon each pad enables new testing schemes such as wafer-scaletesting of a circuit wafer full of springs against pads on a flatsubstrate connected to the test hardware. After testing, the wafercan be singulated and chips with spring tips can be soldered toa board. We previously demonstrated this concept in a memorychip configuration and showed that a chip packaged directly toa printed circuit board can pass standard thermocycle, humidity,shock, and vibration testing [3]. The spring fabrication processuses standard wafer-scale thin-film metallization techniques andprovides top layer signal reroute. The process is low tempera-ture and compatible with active silicon circuitry [4]. The springscan have significantly tighter pitches than other compliant pack-aging approaches such as plated wire bonds or polymer bumps[5]–[7].

A further simplification is to not use solder in the assemblyand use solder-free pressure contacts instead. This enables ex-tremely small pitches, as we previously demonstrated pitchesas small as 6 m [8], [9]. In addition, package rework is sim-plified, as the inteconnects are more readily separated from thepad. Such micro-springs also have potential as micro-connec-tors. Micro-springs have already been shown to work as tem-porary pressure contacts, as probe cards based on our spring

1521-3331/$20.00 © 2006 IEEE

CHOW et al.: PRESSURE CONTACT MICRO-SPRINGS 797

technology are already commercially available [10]. Others alsofabricated lithographically defined metal springs for probe cardapplications, though efforts have focused on dual spring frit-ting approaches to break through the native pad metal oxides,making tighter pitch more difficult [11], [12].

This work studies the reliability of low force pressure con-tacts on gold pads for use as permanent flip-chip interconnects.The reliability of gold contacts has been studied with frettingtests [13]–[15], but for large forces ( 50 gmf) and with onlysingle contacts. In packages, the reliability of gold to gold pres-sure contacts has been measured but with high force (30–400gmf) and large pitch technologies 250 m pitch [16], [17].Low force springs are attractive because they are inherentlysmaller, more readily scalable to large pin counts, and requireless package adhesion force. Low force ( 0.1 gmf) pressurecontacts have been studied, but primarily in terms of contactresistance and with single springs [11], [18], [19]. We recentlyshowed that a single pair of springs at 0.1 gmf can slideagainst a gold pad and not have any intermittent contact resis-tance increases for over 10 000 cycles [20]. With single springsthough, it is difficult to obtain statistically significant resultsas well as perform environmental testing. For flip-chip appli-cations it is important to study packages with many contactsin parallel. In our previous work we characterized packagesand showed that stable resistance values can be obtained forsprings on 22 m pitch using pressure contacts on gold padsduring thermal cycling experiments between 30 C–125 C[21]. However, this work did not include four-wire resistancemeasurements nor high speed glitch testing, and a concernwith pressure contacts is that intermittent contact or slightresistance increases can occur during the wear associated withenvironmental testing.

In this paper we address these concerns through the ex-perimental investigation of a high-density flip-chip packageusing hundreds of micro-spring pressure contacts. In Section II,we describe the fabrication of the metal micro-springs andthe assembly of a test vehicle flip-chip package. Section IIIdescribes the mechanical and electrical characterization ofindividual springs. In Section IV, the package characterizationand reliability testing are described.

II. FABRICATION AND ASSEMBLY

The springs are fabricated with standard wafer-scale thin-filmdeposition techniques. The starting substrate for the springprocess could be an active silicon circuit wafer from a foundry.In a previous report we demonstrated the IC compatibility of thespring process by fabricating springs on a BICMOS wafer [4].For this test vehicle, a chip with daisy chain and test structuresis fabricated on four-inch Corning 1737 glass substrates. Thissubstrate has the same thermal expansion coefficient as siliconbut is optically transparent which aids inspection and assembly.

First, a sacrificial layer of titanium is deposited by sputtering.The sacrificial layer should etch selectively compared to thespring material and substrate, as well as provide strong adhe-sion. Next, a gold seed layer for subsequent plating is sputtered.The spring metal is then deposited by plating through a litho-graphically defined photoresist mask in the shape of the springand the metal traces for signal reroute on the chip [Fig. 1(a)].

Fig. 1. Schematic of spring fabrication process flow.

Fig. 2. SEM image of a spring chip used for packaging tests. There are 200springs in each of 4 rows. The spring anchors are staggered on a 40 �m pitch.The spring tips are on a 20 �m pitch.

The spring metal has multiple layers of different stress levels toprovide a stress gradient with tensile layers on top. As reportedpreviously, the spring metal layers can be sputtered MoCr layerswhich are deposited at different pressures [22]. In this project,we use electroplated nickel layers with different stresses to pro-vide the gradient, similar to other approaches [23]. Plating ispotentially lower cost than sputtering and more easily scaled tolarge substrates.

A second photoresist mask is patterned with photolithog-raphy to define release regions around the springs and to protectthe signal reroute traces against the release etchant. The springsare then released by etching away the sacrificial layer whichallows the spring to rise off the wafer to relieve its internalstress [Fig. 1(b)]. An alloy is then deposited around the spring,followed by electroplated nickel hardened gold [Fig. 1(c)]. Thealloy provides mechanical strength and stiffness, and the goldprovides protection against oxidation and increased conduc-tivity. There are 800 springs per package and the final springsare each 180- m long, 14- m wide, and 5- m thick. Figs. 2and 3 show fabricated arrays of springs from a test vehicle chip.The springs are interleaved so that springs pointing in the samedirection have a pitch of 40 m and the pads they contact areon a 20- m pad pitch. The spring wafers are then diced with awafer saw into chips for assembly into packages. The springchip size is 3 mm 10 mm, a typical size of a driver chip forLCD display applications. The spring tips are 57 m tall, withthe height varying gradually for up to 5 m from one chipend to the other.

Pad chips consisting of gold metal lines and pads are fab-ricated on a separate glass wafer. The pads are laid out on a


Fig. 3. Magnified SEM image of the spring tips. The tips are on a 20-�m pitch.

Fig. 4. Image of a completed package. The small spring chip in the center isaligned and adhered to the larger pad chip.

20- m pitch to match the spring tips. The pad chip patternincludes test structures for measuring daisy chain continuity,four-wire resistance, and electrical isolation. The test signalsare routed from the spring tips to 1-mm pads along the pe-riphery of the package for contact to the reliability equipment.The pad chip measures 11 mm 22 mm.

To assemble the packages, a small amount of UV-curableacrylic adhesive is placed on the pad chip. The spring chip isheld over the pad chip with a vacuum chuck and aligned to thepad chip while optically imaging through the glass. The chipsare then compressed against each other, pushing the springsthrough the acrylic adhesive. The assembled packages arefilled and the springs are surrounded by the acrylic adhesive.The spring tips scrub against the pads as they compress, toexpose clean tip and pad surfaces for the pressure contact. Oncealigned, the package is exposed with UV light at predominantly365 nm. The light exposure cures the adhesive. The assemblyprocess uses a microscope and a force gauge combined in acustom setup. Knowledge of the spring mechanical stiffness(see next section) allows correlation between the assembledpackage force and the vertical compression of the springs.A typical compression force is about 8 g for 800 springs,where each spring is compressed about 20 m. Figs. 4 and 5show the completed package. Figs. 6 and 7 show cross sectionmicrographs of a sliced package.

To enable measurements on individual springs, the springwafer includes test chips which are not intended to be packaged.These test chips have a single spring on one corner which is usedfor force measurements and a three spring structure on anothercorner for electrical resistance measurements.

Fig. 5. Schematic view of a package cross section. The springs form a pressurecontact against the gold pads of the pad chip. An adhesive holds the chip downand protects the contact from the environment.

Fig. 6. Image of a package cross section.

Fig. 7. Closeup image of a package cross section, corresponding to the squarein Fig. 6.

III. SPRING CHARACTERIZATION

The single-spring test chips are used to measure the mechan-ical properties of the springs. In a custom setup, described indetail elsewhere [24], the force as a function of compression isexperimentally measured. A single spring is compressed againsta silicon chip, which sits on a high-resolution force scale, al-lowing smooth repeatable sliding and a direct measurement ofthe vertical spring force. The system has a position and force res-olution of about 0.5 m and 1 mgf, respectively. The force wasobserved to be linear with compression, with a force of 0.01 gmfat 20- m compression. This linear response is expected for themajority of the compression [25]. A typical force-displacementmeasurement is given in Fig. 8.

In order to test for plastic deformation, the spring is re-peatedly compressed and retracted, while the maximumdisplacement of each compression is gradually increased. Theabsolute vertical position of the base of the spring is continuallymeasured, allowing a measurement of the change of the spring


Fig. 8. Measured force versus displacement for a single spring.

height. The relaxed spring height is observed to not changeduring this compression sequence, suggesting the spring re-mains in the linear elastic regime. However, our ability to alignthe test chip in the force setup allows us to measure a maximumcompression of about 33 m for these springs. Without mea-suring the force, the springs are compressed ten times throughthe full height of the springs (57 m) until the spring is rolledout flat against the chip. Again the relaxed spring height doesnot change within the accuracy of the height measurement,suggesting the spring is compliant at room temperature throughits entire compression range.

The spring test chip also has the structure schematicallyshown in Fig. 9 for measuring electrical resistance. Threesprings are compressed a measured distance while a four-wireresistance measurement is performed. Current is forced throughthe device under test, spring B, and returned through springC. The voltage is measured between spring A and spring B.The voltage sense wire runs directly to the base of spring B tocancel the resistance of the wires to the current source. SpringA is closer to spring B (150 m) while spring C is farther fromspring B (300 m). The observed resistance is thus the sum ofa single spring body resistance, the contact resistance betweenspring tip and the pad, and the spreading resistance in the padbetween spring tips A and B. Measurements on pad surfaceswith various sheet resistances indicate that observed spreadingresistance corresponds to about one square of pad resistance.

The test chip is aligned to a gold pad and compressed untilall three springs are visually in contact with the pad and eachcompressed about 3–5 m. This is done before starting the elec-trical measurement to minimize the chance of arcing across asmall air gap and thereby damaging the spring tip or pad sur-face. The springs are then compressed while recording the re-sistance. The resistance is observed to decrease with increasingcompression and plateau at about 0.54 after approximately20 m of compression (Fig. 10). We are not able to directlydecouple the contact resistance from the spring body resistance,but subtracting the body resistance calculated from the spring di-mensions and measured sheet resistances suggests a contact re-sistance of 100 m or below, in line with the 50–150 m valuesfound in literature for this contact area and force [26]. This indi-cates that the metallization along the body of the spring is dom-inating the resistance. The initial resistance decrease is likely

Fig. 9. Schematic of a four-wire test structure for measuring the electrical re-sistance of an individual spring. A small but non-zero voltage dV exists, hencesome spreading resistance is also captured.

Fig. 10. Measured resistance of multiple scrubs during compression of thesingle spring structure against a gold pad.

Fig. 11. Closeup of plateau region in Fig. 10. The resistance decreases slightlywith each successive scrub.

correlated to a decrease in contact resistance, where the tip andpad gold mate with a larger effective contact area as the force in-creases. The measurement is repeated many times with the samespring (Fig. 11), showing a slight decrease of the plateau regionresistance value. This is also likely due to gradual increases inthe effective contact area caused by the scrubs. Three differentsamples were tested and all had similar curves, with the plateauvalue ranging between 0.54 and 0.56 .


Fig. 12. Package test structure schematic. The pad numbers are labeled, as wellas the location of the four-wire test structures (4R) and the isolation test struc-tures (IS).

Fig. 13. Schematic of the four-wire resistance test structure (4R) used insideof a package. The device under test consists of two springs, their correspondingspring-pad contacts, and connecting traces on each of the spring and pad chips.To test the top left 4R in Fig. 12, the pin assignments would be I � (11), V �(10), V + (9), and I + (8).

IV. PACKAGE CHARACTERIZATION

Flip-chip packages were assembled and subjected to environ-mental testing to study the reliability of the electrical contact.The test package includes six four-wire resistance structures andtwo isolation structures (Fig. 12) spaced throughout the chip.The four-wire structure is schematically depicted in Fig. 13.Current is forced through a daisy chain of springs and theircorresponding metal traces on the spring chip and the corre-sponding pads and traces on the pad chip. The voltage is probedon the pad chips of two neighboring springs. The measured re-sistance is thus the sum of: two springs, their pad-tip contacts,the spring chip trace between the springs, and the associated padchip trace.

The isolation test structure (Fig. 14), consists of two neigh-boring springs, at 40- m pitch, which are electrically isolatedfrom each other because the metal trace on the spring chip whichnormally connects the anchors of the two springs is omitted.Leads on the pad chip facilitate an IV curve. As the voltagebetween the two springs is ramped up, the leakage current ismeasured between the springs through the adhesive, as well asbetween neighboring traces on the surface of the pad and springchips.

The test packages were thermocycled in a commercial oven(Sigma Systems M18) to qualify their reliability. The tempera-ture was cycled between 0 C and 125 C with 45 min dwellsfor 460 cycles. Fast cooling and heating rates 40 C minenabled a total cycle time of only 100 min. The four-wire resis-tance structures were measured before and after thermocycling,while isolation structures were measured after thermocycling.

Fig. 14. Schematic of the isolation structure (IS) used in package.

TABLE ITHERMOCYCLING RESULTS FOR PACKAGE SAMPLE A. THE RESISTANCES

WERE MEASURED AT ROOM TEMPERATURE. CONSULT FIG. 12FOR PIN NUMBER LOCATIONS

In addition, in-situ high speed glitch detection was performedwith an event detector (AnaTech STD Event Detector). Duringthermocycling the event detector sources 1 mA of current andmeasures the voltage across a single long daisy chain of hun-dreds of springs. A typical resistance of the entire daisy chain,which includes 796 springs and associated metal traces, is about450 . An event is defined as an increase in resistance over the2000- threshold with a duration of greater than 200 ns.

Humidity tests were also performed. Packages were placedin a commercial humidity chamber (ESPEC SH-241) for 500 hat 60 C and 95% relative humidity. Four wire resistance mea-surements were made before and after humidity testing. The iso-lation test structures were measured after the tests. No in-situglitch detection was performed during the testing.

Resistance measurements after thermocycling packageSample A are given in Table I. Typical IV curves are givenin Fig. 15. The pressure contacts did not show any resistanceincrease during the environmental test, as instead they de-creased about 6% from their initial values. This slight decreaseis possibly due to scrubbing of the spring tip against the pad,which would clean the pad of any residue or possibly increasethe effective contact area by wearing down the tip. One ofthe test structures was not testable because it had an open.Visual inspection identified a particle trapped under a springpreventing the tip from mating with its pad.

Glitch detection measurements showed no events during the460 thermocycles. In Sample A, the isolation test structure, inaddition to the one bad resistance test structure, were shuntedwith a soldered wire before this test, producing a single con-tinuous daisy chain of 698 springs. In Sample B, the isolationtest structures were shunted to form a continuous chain of796 springs. A glitch in any one spring contact would cause


Fig. 15. Linear current versus voltage measurements for the four-wire resis-tance test structure taken at room temperature (Sample A, pin A = 9, pin B =10).

TABLE IIHUMIDITY TEST RESULTS FOR PACKAGE SAMPLE C. THE RESISTANCES

WERE MEASURED AT ROOM TEMPERATURE, BEFORE AND AFTER BEING

STORED AT 60 C AND 95% RELATIVE HUMIDITY FOR 120 h, 240 hAND 500 h RESPECTIVELY. REFER TO FIG. 12 FOR PIN LOCATIONS.

UNIFORMITY IS BETTER THAN 5%

the resistance of the entire chain to glitch. These two chips,each with hundreds of low force pressure contacts, showed noglitches during the 460 thermocycles.

The humidity test results are given in Table II. The initialand final four-wire resistance values are very uniform, with lessthan 5% variation across the corners and middle of the chip.During the humidity tests no resistance increase was observed.This package, Sample C, had a slightly different pad layoutthan Samples A and B; still with the same 40- m spring pitchand 20- m pad pitch. The metal traces on the pad between thesprings are much longer, producing about one additional ohm inthe four-wire test structures compared to Samples A and B.

Leakage current between the center springs in Fig. 14 wasmeasured after environmental testing. Continuity measure-ments were performed on adjacent chains to insure that thesprings in the isolation test structure were in contact withtheir pads. For example, to measure isolation structure pin18–19 (see Fig. 12), two-wire resistance measurements wereperformed on daisy chains pin 17–18 and pin 19–20 to confirmelectrical continuity. Then the isolation structure was measuredby ramping up the voltage across pins 18–19. Fig. 16 shows asample result for Sample A (thermocycle tested) and Sample D(humidity tested). The current is initially below the noise flowof the measurement system (Keithley 2410 Source MeasureUnit). The leakage current then increases to just under 100 pAat 250 V. These measurements were performed in room tem-perature air and humidity. This suggests that an isolation of

Fig. 16. Measured leakage current across isolation test structures after envi-ronmental testing.

well over 500 G at 250 V is maintained after thermocycle andhumidity testing.

V. DISCUSSION

The single spring tests show the springs can be used for elec-trical testing, as they can repeatedly contact a pad and give thesame resistance. This operation mode is similar to testing a com-plete circuit wafer prior to chip singulation, using a wafer-sizeflat contactor, or to pressing a chip against a flat contactor forelectrical testing to confirm known-good-die status before pack-aging. To reduce the risk of packaging bad chips in a multi-chipmodule, the chip could be held in place on the module sub-strate and the entire module system electrically tested; all be-fore gluing the chip to the substrate [7]. The springs have asignificant amount of compliance 50 m , compared tosolder balls, which simplify alignment to another non-planar ornon-parallel substrate. The compliance also helps to compensatefor spring lift-height nonuniformity, which can be about 5 macross the ends of a chip. As long as all springs are compressedover 20 m all springs should make good electrical contact.

The pressure contacts appeared very reliable in packagesdespite operating at only 0.01 gmf. Gold to gold contacts areknown to be very reliable for connector applications at themacroscale. These micro-springs are operating at similar orgreater pressures than macroscopic connectors, as a force ofabout 0.01 gmf ( 0.1 mN), and a contact area of approximately10 m , gives a pressure of 10 MPa, which is the same pressureas a 1 kg force on a 1 mm . This helps to explain why thepressure contacts in the packages did not show gradual orintermittent increases in resistance during thermocycle andhumidity testing.

The gap between the surface of the spring substrate and thatof the pad substrate can change slightly with thermal cycling dueto the thermal expansion properties of the cured adhesive. Thepercentage change in the gap thickness is DT, where is thethermal expansion coefficient of the cured adhesive and DT isthe maximum temperature range of the thermal cycling test. Thethermal expansion coefficient of the acrylic adhesive is 1 10per C, so during a 125 C heating the acrylic adhesive expandsabout 1%. The springs have a linear force-compression relation-ship in this range (see Fig. 8), so the maximum possible springforce change is about 1%. The adhesive strength is significantlystronger ( 100 kg force) than the total spring force ( 0.008 kg


force). During thermocyling the adhesive gets even stronger, sothroughout the temperature range used in the thermal cycle, thepackage integrity is not compromised.

Adequatecomplianceis importantformakingreliablepressurecontacts in packages, as operating well below the yield point iscritical to maintaining force. We found that if we used weakerthin films with less compliance, packages which had good con-tactsat roomtemperature failedafter justa fewthermocycles.Thesprings reported here are elastic through their entire compressionrange(57 m)at roomtemperature.Separate testsshowedthat thespring liftheights changed less than 5% after being compressed30 m while being annealed at 135 C for 48 h.

Other concerns for reliability at the microscale include thinfilm corrosion or stiction. Gold is naturally very corrosion resis-tant, but these packages have not yet been subject to industrialcorrosion tests. The spring tip and pad, however, is encased inacrylic adhesive, which provides protection against gases andmoisture. The absence of intermittent opens suggests that stic-tion problems due to cold or hot welding were not observed.These tests used 1 mA of current, which is more than ade-quate for LCD driver applications. However, higher current testswould be important to perform for applications such as micro-processors.

Current work includes exploring higher force springs. Suchsprings would have the potential to make reliable pressure con-tacts on rough gold surfaces, such as printed circuit boards. Thespring resistance of 0.54 , while adequate for many applica-tions, should be reduced for high current or high frequency ap-plications. Future designs are addressing these markets.

VI. CONCLUSION

These results suggest that a compliant, low force (10 mgf),pressure contact can make reliable electrical contact to a goldpad. Packages with very fine pad pitch (20 m) were demon-strated, an important step for future generations of flip-chippackaging.

ACKNOWLEDGMENT

The authors wish to thank the staff of the PARC process lineand especially L. Wong and V. Geluz-Aguilar for aiding in fab-rication and assembly.

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[23] K. Kataoka, S. Kawamura, T. Itoh, K. Ishikawa, H. Honma, and T.Suga, “Electroplating Ni micro-cantilevers for low contact-force ICprobing,” Sens. Act. A, vol. A103, pp. 116–121, 2003.

[24] E. M. Chow, T. Hantschel, K. Klein, D. K. Fork, C. L. Chua, L. Wong,and K. Van Schuylenbergh, “Micro-spring force characterization andapplications in integrated circuit packaging and scanning probe MEMSmetrology,” in Proc. IEEE Int. Solid-State Sensors Actuators Conf.,Boston, MA, 2003, pp. 408–411.

[25] J. M. Haemer, S. K. Sitaraman, D. K. Fork, F. C. Chong, S. Mok, D.L. Smith, and F. Swiatowiec, “Flexible micro-spring interconnects forhigh performance probing,” in Proc. 50th Electron. Comp. Technol.Conf., Las Vegas, NV, 2000, pp. 1157–1163.

[26] S. C. Bromley and B. J. Nelson, “Performance of microcontacts testedwith a novel MEMS device,” in Proc. 47th IEEE Holm Conf. Elect.Contacts, 2001, pp. 122–127.


Eugene M. Chow (M’02) received the B.S. degreein engineering physics from the University of Cal-ifornia, Berkeley, in 1995, and the M.S. degree inelectrical engineering, the M.S. degree in manage-ment science and engineering, and the Ph.D. degreein electrical engineering from Stanford University,Stanford, CA, in 2001.

At Stanford, he researched MEMS, focusing onthrough wafer electrical interconnects in silicon,atomic force piezoresistive cantilever arrays, anddeep plasma etching. He is currently a Research

Staff Member in the Electronic Materials and Devices Lab, Palo Alto ResearchCenter (formerly Xerox PARC), Palo Alto, CA, where he focuses on MEMSand solid state device research, such as microsprings for integrated circuitpackaging, thin film transistor and MEMS integration, large area printedorganic electronics, and novel printing concepts.

Christopher Chua (M’97) received the B.S. de-gree in physics and the M.S. degree in electricalengineering from the Massachusetts Institute ofTechnology, Cambridge, in 1990 and the Ph.D.degree in optoelectronic devices from CornellUniversity, Ithaca, NY, in 1996.

He joined the Palo Alto Research Center (PARC),Palo Alto, CA, as a Research Associate workingon vertical-cavity surface-emitting lasers. He iscurrently a Senior Member of Research Staff atPARC working on high density interconnects and on

semiconductor light emitters.

Thomas Hantschel received the M.S. degree inelectrical engineering from the Dresden Universityof Technology, Dresden, Germany, in 1995, andthe Ph.D. degree in science from the University ofLeuven, Leuven, Belgium, in 2000.

He was a Postdoctoral Researcher at the PaloAlto Research Center (PARC), Palo Alto, CA, in2001 where he worked on interconnects. He joinedPARC and was a Member of the Research Stafffrom 2002 to 2004 working on stressed-metal tech-nology, MEMS, AFM, plating, and sputtering. He

is currently an Operational Manager of the Materials Characterization Group,IMEC, Leuven, Belgium. His current interests are in materials characterization,nanoprobing, diamond probe technology, and nanostructures.

Koenraad Van Schuylenbergh received the M.S.degree degree in microelectronics, the M.S. degreein biomedical engineering, and the Ph.D. degree inmicroelectronics engineering from the KatholiekeUniversiteit Leuven, Leuven, Belgium, in 1988,1989, and 1998, respectively. His Ph.D. dissertationwas on EM optimization of RF inductors, miniatur-ized wireless telemetry, mixed-mode IC design, andhigh reliability circuit packaging.

He was a Member of the Research Staff at the PaloAlto Research Center (PARC), Palo Alto, CA, until

recently, where he worked on RF MEMS for wireless communication, fine pitchinterconnects, low noise electronics for X-ray imagers, and analog control oflarge numbers of sensors and actuators. He is now with the Medical ElectronicsLaboratory, University of Antwerp, Wilrijk, Belgium. He is the author or co-au-thor of 77 papers and 13 U.S. patents.

David K. Fork (M’92) received the B.S. degree(with highest honors) in physics and the M.S. degree(with highest honors) in electrical engineering fromthe University of Rochester, Rochester, NY, in1987 and the Ph.D. degree in applied physics fromStanford University, Stanford, CA, in 1991.

He is a Principal Scientist at the Palo Alto Re-search Center (formerly Xerox PARC), Palo Alto,CA. He has studied and worked since 1988 at thePalo Alto Research Center, primarily on thin filmelectronic materials and devices. His research activi-

ties have included complex oxide epitaxial thin films, laser crystallized displaymaterials, organic electroluminescent devices, semiconductor LEDs and lasers,electronic imaging systems, and microelectromechanical systems. He holds 52issued U.S. patents and has authored over 100 publications. Recently he lead aNIST ATP consortium developing self-assembled spring contacts for electronicpackages and probes (70NANB8H008). He is presently working on diversetopics in solar energy, self-assembly, and electronic printing.

796 ieee transactions on components and … contact micro-springs in ... eugene m. chow, member,...

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