8 7 6 5 4 3 2 1 schem,mlb,m1 - assistenza pc ... x.xx xx dimensions are in millimeters third angle...

TABLE_TABLEOFCONTENTS_ITEM























































ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

12345678

12345678

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DRAWING

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL























Schematic / PCB #’s

SCHEM,MLB,M101/06/2006

FireWire Port Power (MASTER)(MASTER)41 45

FIREWIRE CONTROLLER (M42)08/29/200540 44

Yukon Power Control (MASTER)(MASTER)39 43

Ethernet Connector (MASTER)(MASTER)38 42

ETHERNET CONTROLLER M4210/12/200537 41

PATA Connector (MASTER)(MASTER)36 38

Mobile Clocking (MASTER)(MASTER)35 37

Clock Termination (MASTER)(MASTER)34 34

CLOCKS M4210/12/200533 33

DDR2 VRef (MASTER)(MASTER)32 32

Memory Vtt Supply (MASTER)(MASTER)31 31

Memory Active Termination (MASTER)(MASTER)30 30

DDR2 SO-DIMM Connector B (MASTER)(MASTER)29 29

DDR2 SO-DIMM Connector A (MASTER)(MASTER)28 28

M1 SMBus Connections (MASTER)(MASTER)27 27

SB Misc (MASTER)(MASTER)26 26

SB Decoupling M4211/16/200525 25

SB: 4 OF 4 M3811/16/200524 24

SB: 3 OF 4 M3811/16/200523 23

SB: 2 of 4 (M38)09/08/200522 22

SB: 1 OF 4 M3811/16/200521 21

NB Config Straps (MASTER)(MASTER)20 20

NB (GM) Decoupling (MASTER)(MASTER)19 19

NB Grounds (MASTER)(MASTER)18 18

NB Power 2 (MASTER)(MASTER)17 17

NB Power 1 (MASTER)(MASTER)16 16

NB DDR2 Interfaces (MASTER)(MASTER)15 15

NB Misc Interfaces (MASTER)(MASTER)14 14

NB PEG / Video Interfaces (MASTER)(MASTER)13 13

NB CPU Interface (MASTER)(MASTER)12 12

CPU ITP700FLEX DEBUG M4210/12/200511 11

CPU MISC1-TEMP SENSOR M4210/07/200510 10

CPU Decoupling & VID (MASTER)(MASTER)9 9

CPU 2 OF 2-PWR/GND M4211/16/20058 8

CPU 1 OF 2-FSB M4211/16/20057 7

Signal Aliases N/AN/A6 6

Functional / ICT Test N/AN/A5 5

BOM Configuration N/AN/A4 4

Power Block Diagram N/AN/A3 3

System Block Diagram N/AN/A2 2

79 M1 Net Properties(MASTER)104

(MASTER)

78 Revision HistoryN/A100

N/A

77 LVDS Interface Pull-downs(MASTER)99

(MASTER)

76 M1 Specific Connectors(MASTER)98

(MASTER)

75 External Display Connector(MASTER)97

(MASTER)

74 Internal Display Connectors(MASTER)94

(MASTER)

73 ATI M56 Video Interfaces (MASTER)93(MASTER)

72 ATI M56 GPIO/DVO/Misc (MASTER)91(MASTER)

71 GDDR3 Frame Buffer B (MASTER)90(MASTER)

70 GDDR3 Frame Buffer A (MASTER)89(MASTER)

69 GPU Straps (MASTER)88(MASTER)

68 ATI M56 Frame Buffer I/F (MASTER)87(MASTER)

67 ATI M56 Core Power (MASTER)86(MASTER)

66 GPU (M56) Core Supplies (MASTER)85(MASTER)

65 ATI M56 PCI-E (MASTER)84(MASTER)

64 PBus-In & Battery Connectors (MASTER)82(MASTER)

63 Power Aliases (MASTER)81(MASTER)

62 3.3V G3Hot Supply & Power Control (MASTER)80(MASTER)

61 3.3V / 1.05V Power Supplies(MASTER)79

(MASTER)

60 1.8V Supply(MASTER)78

(MASTER)

59 2.5V & 1.2V Regulators(MASTER)77

(MASTER)

58 5V / 1.5V Power Supply(MASTER)76

(MASTER)

57 IMVP6 CPU VCore Regulator(MASTER)75

(MASTER)

56 TPM11/16/200567

M38

55 Sudden Motion Sensor (SMS)(MASTER)66

(MASTER)

54 Fan Connectors(MASTER)65

(MASTER)

53 ALS Support(MASTER)64

(MASTER)

52 SPI BOOTROM11/16/200563

M42

51 Current & Voltage Sensing (MASTER)62(MASTER)

50 Thermal Sensors (MASTER)61(MASTER)

49 LPC+ Debug Connector 07/20/200560M42

48 SMC Support (MASTER)59(MASTER)

47 SMC 10/07/200558M38

46 PCI-E Connections (MASTER)57(MASTER)

45 Left I/O Board Connector (MASTER)55(MASTER)

44 External USB Connector (MASTER)52(MASTER)

43 Internal USB Connections (MASTER)49(MASTER)

01/06/06418829PRODUCTION RELEASEDA ?

051-6941 A1 104

SCHEM,MLB,M1

Date(.csa) SyncContentsPage Page(.csa) SyncContents Date

ABBREV=DRAWINGTITLE=M1_MLB

LAST_MODIFIED=Fri Jan 6 18:57:50 2006

42 FireWire Ports (MASTER)46(MASTER)Table of Contents N/A

N/A1 1

PCBF,MLB,M1 CRITICAL820-1881 PCB1

SCHEM,MLB,M1 CRITICAL051-6941 SCH1

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER



III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT


12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

P.38

P.42

P.44

P.76

P.36

P.50

SensorsTemperature

PWM/Tach

SMBus x5

P.54Connectors

Fan

SMS

TPM

P.56

PCIe x16

RJ45 (Ethernet)

1394a (FireWire)

Connector

ConnectorFW

P.41Port Power

P.37

P.40

Controller

ControllerFW323-06 FireWire

PCI

P.39

PCIe x1

ENET Yukon Gig-E Yukon Power

SENSOR

DVI-I/DL Connector w/TV-Out Support

INVERTERCONNECTOR

LCD Panel

Camera

HDD/IR/BTConnector

Connector

ODDConnector

Geyser KB /TP Connector

Right USB 2.0Connector

P.43

P.43

P.74

P.75

P.74,77

ControllerCK410 Clock

P.33-34

Battery SMBusConnector

P.64

16BITS66MHZ

PATA

SMC SMBus

P.27

SB SMBus

P.27

P.52

USB x2

USB

SATA

USB

USB

SMBus

BootROM

P.47-48

SPI

SMC

H8S/2116

LPC 33MHZ

P.51

Analog

P.55

Sensors

Connector

LPC

P.49

Debug

ALSP.53,76

ICH7-M

P.21-26

609 BGA

USB

USBSB

P.12-20

DMI x4

PWM

Dual-Channel TMDS

Dual-Channel LVDS

S-Video/Composite GPU

P.70-71128MB/256MBFrame Buffer

GDDR3

ATI M56P

P.65-69,72-73

P.10

THERMALCPU

(Yonah)Core Duo

945GM

1466UFCBGA

NB

P.7-9

FSB

CH.B

CH.A

479 BGA

CPU DebugITP700FLEX

Connector

PCIe x1

PCIe x1

Azalia (HD-Audio)

PowerSupplies

P.57-64,66

P.32

BUFFERDDR2 VREF

Left I/O &Audio BoardConnector

P.45

P.30-31P.29

J2900

J2800

P.11

DDR2 SO-DIMM B

DDR2 SO-DIMM ALower Connector

Upper Connector

P.28

DDR2 VTT& REGULATOR

System Block Diagram

A

2 104

051-6941

SYNC_MASTER=N/A SYNC_DATE=N/A

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DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(ISL6269)

1.25V - 0.8V

1.1V - 0.95VQ7947

Q7945

Q7845

Q7770

Q7720

Q7615

Q7610

PP3V3_S5U7530

FWPWR_EN_L

PM_SLP_S3BATT

PM_SLP_S3BATT

NC

PM_SLP_S3BATT

Q4300

3.3VPP3V3_S3AC

ODD_PWR_EN_L (SB GPIO14)

PP5V_S0_IDE_ODD5V

Q3820

PP3V3_S03.3V

PM_SLP_S3_LS5V

ConnectorLIO Power

J8200

PPBUS_G3H

U7900

3.3V

PM_SLP_S4_L

ConnectorLIO Flex

J5500

PPDCIN_G3H18.5V - 9V

12.6V - 9V

ENABLE

3.425G3Hot

(LT3470)

PP3V42_G3H3.425V

U8000

5.0V

1.8VPP1V8_S0

PM_SLP_S3_LS5V_L

PM_SLP_S3_LS5V_L

1.2VPP1V2_S0

PPBUS_S5_FWPORT

12.6V - 9V

Q4565

0.9VPP0V9_S0

(BD3533FVM)S0

0.9V (Vtt)

U3100

PM_SLP_S3_L

PGOOD

(ISL6269)

ENABLE

S3

U7800

1.8V

NC

1.8VPP1V8_S3

Inverter

Connector

J5500

ENABLE

ENABLE

PM_SLP_S3_LS5V_L

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

PM_SLP_S3_LIMVP_PWRGD_IN/ALL_SYS_PWRGD

S0

RSMRST_PWRGD

IMVP_VR_ONIMVP_PWRGD_IN

ENABLES

CPU VCore

(ISL6262)S0

"IMVP6"

VR_PWRGOOD_DELAY

PGOOD

SMC_PM_G2_ENABLEPM_SLP_S3_L

1.5V

5V

U7600ENABLES

PGOOD

S5/S0

(LTC3728)

NCSMC_PM_G2_ENABLE

PP5V_S55.0V

PP1V5_S0

PP5V_S35.0V

PP5V_S0

PP3V3_S33.3V

U7700ENABLE

PGOOD

S3

2.5V

(LTC3411)

PP2V5_S32.5V

PP2V5_S02.5V

PP1V2_S31.2V

U7750ENABLE

1.2V

PGOOD

S3

(LTC3412)

NC

ENABLE

GPU VCore

PGOOD

(ISL6269)

S0PPVCORE_S0_GPU

U7950

1.05V

PGOOD

PP1V05_S01.05V

PPVCORE_S0_CPU

ENABLE

3.3V

S5

(ISL6269)

PGOOD

1.5V

NC

U8500

PM_SLP_S3_L

5V/1.5V

Power Block DiagramSYNC_MASTER=N/A SYNC_DATE=N/A

A051-6941

3 104

www.vinafix.vn

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

630-7402 is placeholder for PCBA,MLB_BST,HY256,M1 (EEE:UNJ)

Bar Code Label / EEE #’s

Module Parts

"Better" BOM

"Best" BOM630-7401 is placeholder for PCBA,MLB_BTR,HY128,M1 (EEE:UNH)

M1,BST,HY256 (UNUSED)

M1,BTR,SAM128

M1,BTR,HY128 (UNUSED)

M1,BST,SAM256

BOMOPTION Groups

EEE_TYY[EEE:TYY]1826-4393 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM

4 U8900,U8950,U9000,U9050 CRITICAL333S0350 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA VRAM_256_SAMSUNG

CPU_BTRIC,M1 BTR,479 BGA337S3267 1 CRITICALU0700

BOOTROM_FINALIC,EFI,BOOTROM FINAL,M1341S1813 1 CRITICALU6301

BOOTROM_DEVELU6301341S1812 IC,EFI,BOOTROM DEVELOPMENT,M1 CRITICAL1

IC,SMC,HS8/2116 SMC_BLANK338S0274 U58001 CRITICAL

SMC_PRGRMIC,PRGRM,SMC,M1341S1843 CRITICAL1 U5800

338S0268 1 U4400 CRITICALIC,FW32306,1394A LINK,BGA,129P

338S0270 1 U4101 CRITICALIC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

U84001 IC,ATI,M56P,GRPHSCTRL,880BGA,LF CRITICAL338S0309

U1200IC,945GM,SOUTHBRIDGE338S0269 1 CRITICAL

IC, TPM, 28-PIN TSSOP CRITICAL1 U6700341S1789

U2100IC,SB,652BGA343S0385 1 CRITICAL

IC,EEPROM,SERIAL IIC,8KBIT,SO81341S1797 CRITICALU4102

CRITICALIC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE1353S1235 U7530

CRITICAL1826-4393 [EEE:UNJ] EEE_UNJLBL,P/N LABEL,PCB,28MM X 6 MM

359S0101 IC,CY28445-5,CLOCK GEN,68PIN QFN U33011 CRITICAL

M1_COMMON3 RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M1_COMMON2 ITP,INVERTER_BUF,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3,MEMVTT_EN_PU

M1_COMMON1 BOOTROM_FINAL,ENET_LOM_DISABLE,ENETPWR_S3AC,GPU_BB_CTL,GPUTHM_A_GPU,HSTHMSNS_HAS

EEE_UNK,M1_COMMON,CPU_BTR,VRAM_SAM128PCBA,MLB_BTR,SAM128,M1630-7403

EEE_TYY,M1_COMMON,CPU_BST,VRAM_SAM256630-7254 PCBA,MLB_BST,SAM256,M1

1826-4393 EEE_UNHLBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL[EEE:UNH]

CPU_BSTIC,M1 BST,479 BGA337S3268 1 CRITICALU0700

VRAM_256_HYNIX333S0351 CRITICAL4 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050

CRITICAL1 EEE_UNK[EEE:UNK]LBL,P/N LABEL,PCB,28MM X 6 MM826-4393

U8900,U8950,U9000,U90504333S0354 CRITICAL VRAM_128_SAMSUNGIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

333S0358 CRITICAL4 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_128_HYNIX

VRAM_HY256 GPU_MEM_256M,GPU_MEM_HYNIX,VRAM_256_HYNIX

VRAM_HY128 GPU_MEM_HYNIX,VRAM_128_HYNIX

VRAM_SAM128 VRAM_128_SAMSUNG

VRAM_SAM256 GPU_MEM_256M,VRAM_256_SAMSUNG

M1_COMMON COMMON,M1_COMMON1,M1_COMMON2,M1_COMMON3

104

SYNC_DATE=N/ASYNC_MASTER=N/A

051-6941

BOM Configuration

A

4

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU FSB NO_TESTs

Power Supply NO_TESTsEXPOSED_VIANO_TEST

NO_TEST

FUNC_TEST

for Functional Test points.are not on the proper sidesince these test pointsFUNC_TEST property removed

FUNC_TEST

should have a via with 10-mil soldermaskEXPOSED_VIA property indicates that the net

EXPOSED_VIA

Misc EXPOSED_VIA NetsEXPOSED_VIA

FUNC_TESTFUNC_TEST

FUNC_TEST

FUNC_TEST

LPC+ Debug Connector

Fan Connectors

Left I/O Data Connector

Camera Connector

FUNC_TEST

FUNC_TEST

FUNC_TEST

Other Func Test Points

Current Sense Calibration

2 TPs per

8 TPs, 2 with each of above TP pairs

Functional Test PointsBattery Digital Connector

Left ALS Connector

Left I/O Power Connector

Request for at least 10 GND test points

called out separately in these notes.NOTE: 10 additional GND test points are

FUNC_TEST

opening for use as engineering probe point.

Thermal Diode Connectors

Functional / ICT TestSYNC_DATE=N/ASYNC_MASTER=N/A

5 104

A051-6941

=PP5V_S0_ISENSECALTRUE

=PP1V8_S3_REGTRUE=PP1V5_S0_REGTRUE

TRUE PPVCORE_S0_GPUTRUE PPVCORE_S0_CPU

TRUE EXCARD_CLKREQ_L

TRUE ISENSE_CAL_EN

HSTHMSNS_DX_PTRUETRUE HSTHMSNS_DX_N

TRUE =PPBUS_G3H_LIO_CONNTRUE GND

PCIE_WAKE_LTRUE=SMBUS_LIO_SB_SDATRUE=SMBUS_LIO_SB_SCLTRUE=SMBUS_LIO_SMC_SDATRUE

PCIE_CLK100M_MINI_NTRUE=SMBUS_LIO_SMC_SCLTRUE

PCIE_CLK100M_MINI_PTRUE

=PCIE_MINI_D2R_NTRUE=PCIE_MINI_D2R_PTRUE

=PCIE_MINI_R2D_PTRUETRUE =PCIE_MINI_R2D_NTRUE =PP5V_S3_CAMERA

TRUE =USB2_CAMERA_N

TRUE SYS_ONEWIRE

TRUE LIO_P3V3S0_EN_L

TRUE SMC_BATT_ISET

EXCARD_OC_LTRUEACZ_RST_LTRUE

LTUSB_OC_LTRUE

TRUE GND_BATT

TRUE GND

TRUE =PP1V05_S0_REG

TRUE SMC_ONOFF_LTRUE PM_SYSRST_L

TRUE =SMBUS_ATS_SCLTRUE GND

TRUE =USB2_CAMERA_P

RSFSTHMSNS_D_NTRUERSFSTHMSNS_D_PTRUE

TRUE GNDTRUE LTALS_OUT

ALS_GAINTRUE=PP3V3_S3_LTALSTRUE

TRUE =SMBUS_ATS_SDA

TRUE FWH_INIT_L

TRUE PM_SUS_STAT_L

TRUE SMC_TCK

TRUE SMC_NMI

TRUE SV_SET_UP

TRUE =PCIE_EXCARD_R2D_N

TRUE SMC_TDI

TRUE INT_SERIRQ

TRUE LPC_AD<2>TRUE PCI_CLK_PORT80_LPC

LPC_AD<3>TRUE

=PP5V_S0_FAN_LT

FAN_RT_PWM

FAN_LT_TACHFAN_LT_PWM

FAN_RT_TACH

SB_CLK100M_SATA_PTRUESB_CLK100M_SATA_NTRUE

DMI_N2S_P<1..0>TRUEDMI_N2S_N<1..0>TRUE

FSB_DSTBP_L<3..0>TRUE TRUE

FSB_HITM_LTRUEFSB_LOCK_LTRUEFSB_REQ_L<4..0>TRUE

FSB_BNR_LTRUEFSB_BREQ0_LTRUEFSB_D_L<63..0>TRUE

TRUE FSB_ADSTB_L<1..0>TRUETRUE FSB_ADS_L

FSB_A_L<31..3>TRUE

TRUE PCIE_CLK100M_EXCARD_P

ACZ_BITCLKTRUETRUE SMC_TMS

TRUE LPC_AD<0>

TRUE LPC_FRAME_LTRUE PM_CLKRUN_LTRUE BOOT_LPC_SPI_L

TRUE DEBUG_RST_L

TRUE =PP5V_S0_LPCPLUS

ACZ_SDATAIN<0>TRUE

TRUE LPC_AD<1>

TRUE SMC_TX_L

TRUE SMC_RST_L

TRUE SMC_RX_L

GND_AUDIOTRUEGND_AUDIO_PWRTRUE

TRUE =PP3V42_G3H_LIOTRUE PP5V_S0_AUDIO_PWR

TRUE SMC_TRST_L

TRUE SMC_MD1SMC_TDOTRUE

TRUE SMC_SYS_ISETTRUE LIO_BATT_ISENSE

LIO_DCIN_ISENSETRUETRUE LIO_P3V3S3_ENTRUE SMC_BATT_TRICKLE_EN_L

TRUE MINI_CLKREQ_LTRUE SMC_EXCARD_CP

LIO_PLT_RESET_LTRUETRUE SMC_EXCARD_PWR_EN

TRUE ACZ_SYNC

TRUE =USB2_LT_PTRUE =USB2_LT_N

TRUE =USB2_EXCARD_PTRUE =USB2_EXCARD_N

=PCIE_EXCARD_R2D_PTRUE

=PCIE_EXCARD_D2R_PTRUE

TRUE SMC_ADAPTER_EN

TRUE =SMBUS_BATT_SDA

TRUE SMC_BS_ALRT_LTRUE =SMBUS_BATT_SCL

=PCIE_EXCARD_D2R_NTRUE

TRUE PCIE_CLK100M_EXCARD_N

TRUE PP5V_S0_AUDIO

=PP5V_S5_LIOTRUETRUE =PPDCIN_G3H_LIO

=PP1V5_S0_LIOTRUE

TRUE SMC_BC_ACOKTRUE SMC_BATT_CHG_EN

ACZ_SDATAOUTTRUE

TRUE =PP3V3_S5_LPCPLUS

P1V05S0_COMPTRUE

P1V8S3_FSETTRUE

P2V5S3_MODETRUE

IMVP6_RBIASTRUE

P1V05S0_FSETTRUE

IMVP6_COMPTRUE

P5VS5_RUNSSTRUE

P2V5S3_SHDNRTTRUE

P3V3S5_FSETTRUEP3V3S5_COMPTRUE

P1V2S3_RTTRUE

P1V8S3_COMPTRUE

P1V2S3_RUNSSTRUE

P1V5S0_RUNSSTRUE

FSB_DBSY_LTRUE

P3V42G3H_FBTRUE

GPUVCORE_FSETTRUE

FSB_HIT_LTRUE

TRUE FSB_DSTBN_L<3..0>TRUE

GPUVCORE_COMPTRUE

GPUBBP_ADJTRUE

TRUE FSB_DRDY_LFSB_DINV_L<3..0>TRUE TRUE

56

56

51

49

56

56

56

56

56

49

56

48

63

45

48

48

79

63

48

47

76

49

48

49

49

49

49

49

79

79

79

79

79

79

79

79

79

79

79

49

49

49

47

49 79

49

49

49

49

49

48

48

79

47

64

48

48

79

79

79

79

79

79

60

63

45

64

37

45

45

45

45

45

45

46

46

46

46 63

43

47

62

47

45

45

45

61

47

26

43

43

76

47

76

43

48

47

48

49

49

46

48

47

47

49

47

63

34

34

22

22

12

12

12

12

12

12

12

12

12

12

45

45

48

47

47

40

47

49

63

45

47

48

48

48

63

49

49

48

47

51

51

62

47

45

47

45

47

45

45

45

45

45

46

46

45

64

48

64

46

45

63

63

63

47

47

45

63

62

59

62

12

12

12

12

12

51

58

63

63

34

50

50

63

23

27

27

27

34

27

34

45

45

45

45 43

6

45

45

45

6

21

6

64

51

43

23

27

6

50

50

53

6

63

27

21

23

47

47

23

45

47

23

21

34

21

54

54

54

54

54

21

21

14

14

7

7

7

7

7

7

7

7

7

7

34

21

47

21

21

23

22

26

49

21

21

47

47

47

45

45

45

45

47

47

47

45

45

45

45

45

34

45

26

45

21

6

6

6

6

45

45

41

27

47

27

45

34

45

45

45

45

45

45

21

49

61

60

59

57

61

57

58

59

61

61

59

60

39

58

7

62

66

7

7

66

66

7

7

www.vinafix.vn

IN OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Chassis connection to be made at the mounting hole southwest of the USB connector

Chassis connection to be made at the mounting hole northwest of the DVI connector

Chassis connection to be made at the mounting hole east of the LVDS connector

USB Port "D" = Camera

USB Port "F" = IR Receiver

USB Port "C" = Left USB 2.0 Port

USB Port "G" = Bluetooth (M13P)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "B" = Trackpad (Geyser)

USB Port "E" = ExpressCard

USB Port "H" = Reserved (PCI-E Mini Card)

Trace deleted to make room for other diffpairs over RAM connector.

NOTE: NB_CFG<13..12> require test access

Ethernet Power Management Support

NOTE: BOM options "USB_G_OC_PU" and"ENET_LOM_DISABLE" are mutually-exclusive.

HOLE-VIA-P5RP251

ZT0600

HOLE-VIA-P5RP251

ZT0601

HOLE-VIA-P5RP251

ZT0602

SHLD-SM-LFOG-503040

3

2

1

SH0600

5%1/16WMF-LF402

ENET_LOM_DISABLE

021

R0600

SYNC_DATE=N/ASYNC_MASTER=N/A

6 104

A051-6941

Signal Aliases

SB_GPIO30 ENET_LOM_DIS_L

MAKE_BASE=TRUENO_TEST=TRUE

NC_ENET_CTRL25 ENET_CTRL25


NC_ENET_CTRL12 ENET_CTRL12

MAKE_BASE=TRUEALS_GAIN =RTALS_GAINMAKE_BASE=TRUETP_SMC_RSTGATE_L SMC_RSTGATE_L


NC_SB_XOR_V4 TP_SB_XOR_V4


NC_SB_XOR_W3 TP_SB_XOR_W3


NC_SB_XOR_U5 TP_SB_XOR_U5


NC_SB_XOR_V3 TP_SB_XOR_V3


NC_SB_XOR_T5 TP_SB_XOR_T5

MAKE_BASE=TRUETP_SB_SUS_CLK SUS_CLK_SB

MAKE_BASE=TRUETP_NB_CFG<13..12> NB_CFG<13..12>

MAKE_BASE=TRUETP_NB_CFG<17> NB_CFG<17>






NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_B_A<15..14> MEM_B_A<15..14>NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_A_A<15..14> MEM_A_A<15..14>

=USB_BT_P

TP_CPU_APM0_L

TP_USB2_HNMAKE_BASE=TRUE

TP_USB2_HPMAKE_BASE=TRUE

USB_H_N

USB_H_P

USB2_EXCARD_NMAKE_BASE=TRUE

=USB2_CAMERA_P

=GND_CHASSIS_LCD2

GND_CHASSIS_INVERTER

MAKE_BASE=TRUEVOLTAGE=0VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

NC_CPU_A36_LMAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_APM1_LMAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_APM0_LNO_TEST=TRUEMAKE_BASE=TRUE

TP_CPU_HFPLL

NC_CPU_EXTBREFMAKE_BASE=TRUENO_TEST=TRUE

MAKE_BASE=TRUEUSB2_LT_N

USB2_LT_PMAKE_BASE=TRUE

=USB_TRACKPAD_P

USB_D_P

USB_IR_NMAKE_BASE=TRUE

USB_IR_PMAKE_BASE=TRUE

=USB_IR_N

=USB_BT_N

USB_F_N

MAKE_BASE=TRUEUNUSED_USB_D_OC_L

TP_CPU_SPARE4

TP_CPU_SPARE1

TP_CPU_SPARE2

TP_CPU_SPARE0

TP_CPU_EXTBREF

TP_CPU_APM1_L

TP_CPU_A39_L

TP_CPU_A38_L

TP_CPU_A36_L

TP_CPU_A37_L

TP_CPU_A35_L

TP_CPU_A34_L

TP_CPU_A33_L

TP_CPU_A32_L

NC_CPU_SPARE4NO_TEST=TRUEMAKE_BASE=TRUE

NC_CPU_SPARE1NO_TEST=TRUEMAKE_BASE=TRUE

NC_CPU_SPARE2MAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_SPARE0MAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_HFPLLMAKE_BASE=TRUENO_TEST=TRUE








GND_CHASSIS_LVDS


=GND_CHASSIS_LCD3=GND_CHASSIS_LCD4

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD1

MAKE_BASE=TRUEUSB2_RT_N

USB2_RT_PMAKE_BASE=TRUE

=USB2_RT_P

=USB2_RT_N

USB_A_P

USB_A_N

USB_A_OC_L

USB_B_P

USB_B_N

USB_B_OC_LMAKE_BASE=TRUEUNUSED_USB_B_OC_L

USB_C_P

USB_C_OC_L

USB_C_N

RTUSB_OC_LMAKE_BASE=TRUE

=RTUSB_OC_L

MAKE_BASE=TRUEUSB_TRACKPAD_P

MAKE_BASE=TRUEUSB_TRACKPAD_N=USB_TRACKPAD_N

=USB2_LT_P

USB_D_N

USB_D_OC_L

USB_E_OC_LMAKE_BASE=TRUEEXCARD_OC_L

USB_E_N

USB_G_N

USB_G_P

MAKE_BASE=TRUEUSB2_CAMERA_P

USB2_CAMERA_NMAKE_BASE=TRUE

=USB2_CAMERA_N

MAKE_BASE=TRUEUSB2_EXCARD_P

USB_BT_PMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_BT_N

=USB2_EXCARD_N

=USB2_EXCARD_P USB_E_P

=USB2_LT_N

USB_F_P=USB_IR_P

MAKE_BASE=TRUELTUSB_OC_L

=GND_CHASSIS_RTUSB=GND_CHASSIS_FW_PORT1=GND_CHASSIS_FW_EMI=GND_CHASSIS_ENET

MIN_LINE_WIDTH=0.5 mmVOLTAGE=0VMAKE_BASE=TRUE

GND_CHASSIS_DVI_TOPMIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI4=GND_CHASSIS_DVI2

=GND_CHASSIS_DVI1GND_CHASSIS_DVI_BOT



76

48

47

43

45

45

43

45

45

45

45

22 37

37

37

5 53

47

21

21

21

21

21

23

14

14

14

14

14

14

14

29

28

76

7

22

22

5

74

7

43

22

76

76

22

7

7

7

7

7

7

7

7

7

7

7

7

7

7

74

74

74

74

44

44

22

22

22

22

22

22

22

22

22

44

43

5

22

22

22 5

22

22

22

5

5

5 22

5

22 76

5

44

42

42

38

75

75

75

75

75

www.vinafix.vn

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

A7*

RSVD14RSVD15

BCLK1BCLK0

RSVD20

RSVD17RSVD18

RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*TMS

TDO

TDITCK

PREQ*PRDY*

BPM3*

BPM1*BPM2*

BPM0*

HITM*

HIT*

TRDY*RS2*

RS1*

RS0*RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*DRDY*

DEFER*

BPRI*

BNR*ADS*

RSVD11

RSVD6

RSVD7RSVD8

RSVD1

RSVD2RSVD3

RSVD4RSVD5

RSVD9

RSVD10

SMI*

LINT0LINT1

STPCLK*

IGNNE*

FERR*A20M*

ADSTB1*

A30*A31*

A27*A28*

A29*

A26*

A25*A24*

A22*A23*

A21*

A20*A19*

A18*

A17*

REQ4*REQ3*

REQ1*REQ0*

REQ2*

ADSTB0*

A14*A15*

A16*

A13*

A12*A11*

A10*

A9*A8*

A6*

A5*

A4*A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1

ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*D60*

D59*

D58*D57*

D56*

D55*D54*

D52*D53*

D51*

D50*D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45*D46*

D44*D43*

D42*

D41*D40*

D39*

D38*D37*

D36*

D35*D34*

D33*D32*

BSEL2

DSTBN1*

BSEL0

BSEL1

TEST2

TEST1

DINV1*DSTBP1*

D31*

D30*

D29*

D26*

D27*

D28*

D24*

D25*

D23*

D21*

D22*

D20*

D19*

D18*

D16*

D17*

DINV0*

DSTBP0*DSTBN0*

D15*

D14*D13*

D12*D11*

D10*

D9*D8*

D7*

D6*D5*

D4*

D3*D2*

D1*D0*

GTLREF

NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU IS HOTAND CPU VR TO INFORM

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GNDPLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".COMP0,2 CONNECT WITH ZO=27.4OHM, MAKELAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TOPM_THRMTRIP#

STUB)

SPARE[7-0],HFPLL:ROUTE TO TP VIA AND

0.1" AWAY

1%54.9MF-LF4021/16W2

1R0702

681/16W5%

402MF-LF2

1R0704

1KMF-LF402

1%1/16W2

1R0705

2.0KMF-LF402

1%1/16W2

1R07061%402

54.921R0719

27.421R0718

1% 402

54.921R0717

27.4402

21R0716

NOSTUFF

402

0 21R0730

1/16W5%

402MF-LF

1K

NOSTUFF

2

1R0707511/16W5%

402MF-LF2

1R0712

402MF-LF1/16W1%54.9

2

1R0703

1%402

54.921R0720

54.9

4021%21

R0721

1%402

54.921R0722

OMIT

CPUYONAH

BGA

AB6

G2

AB5

C7

A25A24

AB3AA6AC5

D5

A3

B2V3T2N5M4

AA3AB2

C24

AA4

C23D22AF1C1D3F6D2

T22

B25

C3

AA1

G3F4F3B1

L5J3K2H2K3

D21

AC1AC2

H4

B4C6

B3

C4

D20

E4G6

A5

F21H5

E1

C20

F1

G5

AC4AD1AD3AD4

E2

A21A22

V4

L2

H1

J1N2M1K5M3L4

Y1W2

J4

Y4W5W3T3T5R4U2Y5U4

A6

W6R3U5Y2

R1P1P4L1P2P5N3

U0700

OMIT

BGAYONAHCPU

D25

C26

D7D6

AE6

A2AD26

AE24

Y25

N25

G22

AD23

W24

M24

H23

D24B5E5

AC20

V23

M26

J26

G24K24E23

AF26AF22AF25AE25

E25

AD21AE21AD24AF23AE22AD20AC25AB21AA21AB22

G25

AC23AC22

AA24AC26Y22Y26AA26Y23W22AB25

F23

U22U25U23W25V26V24AB24AA23

N24T25

H22

L26R24T24P23P22P25M23L23L22L25

E26

R23P26K25N22

H25K22F26H26J23J24

F24E22

V1U1U26R26

C21B23B22

U0700

CPU 1 OF 2-FSBSYNC_MASTER=M42

7

A051-6941

104

SYNC_DATE=11/16/2005

FSB_BPRI_LFSB_BNR_LFSB_ADS_L

CPU_PSI_LFSB_SLPCPU_LCPU_PWRGD

CPU_DPRSTP_LCPU_DPSLP_LFSB_DPWR_L

CPU_COMP<2>CPU_COMP<3>

CPU_COMP<1>CPU_COMP<0>

FSB_DSTBP_L<3>FSB_DSTBN_L<3>

FSB_DINV_L<3>

FSB_D_L<63>FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>FSB_D_L<59>FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>

FSB_D_L<52>FSB_D_L<53>

FSB_D_L<51>FSB_D_L<50>FSB_D_L<49>FSB_D_L<48>FSB_DINV_L<2>

FSB_DSTBN_L<2>FSB_D_L<47>

FSB_DSTBP_L<2>


FSB_D_L<44>FSB_D_L<43>FSB_D_L<42>FSB_D_L<41>FSB_D_L<40>FSB_D_L<39>FSB_D_L<38>FSB_D_L<37>FSB_D_L<36>FSB_D_L<35>FSB_D_L<34>FSB_D_L<33>FSB_D_L<32>

CPU_BSEL<2>

FSB_DSTBN_L<1>

CPU_BSEL<0>CPU_BSEL<1>

CPU_TEST2CPU_TEST1

FSB_DINV_L<1>FSB_DSTBP_L<1>

FSB_D_L<31>FSB_D_L<30>FSB_D_L<29>



FSB_D_L<23>




FSB_DINV_L<0>FSB_DSTBP_L<0>FSB_DSTBN_L<0>FSB_D_L<15>FSB_D_L<14>FSB_D_L<13>FSB_D_L<12>FSB_D_L<11>FSB_D_L<10>FSB_D_L<9>FSB_D_L<8>FSB_D_L<7>FSB_D_L<6>FSB_D_L<5>FSB_D_L<4>FSB_D_L<3>FSB_D_L<2>FSB_D_L<1>FSB_D_L<0>

CPU_GTLREF

FSB_A_L<7>

TP_CPU_SPARE1TP_CPU_SPARE2

FSB_CLK_CPU_NFSB_CLK_CPU_P

TP_CPU_SPARE7

TP_CPU_SPARE4TP_CPU_SPARE5TP_CPU_SPARE6

TP_CPU_SPARE3

TP_CPU_SPARE0

TP_CPU_EXTBREF

PM_THRMTRIP_LCPU_THERMD_NCPU_THERMD_PCPU_PROCHOT_L

XDP_DBRESET_LXDP_TRST_LXDP_TMSXDP_TDOXDP_TDIXDP_TCK

XDP_BPM_L<4>XDP_BPM_L<3>XDP_BPM_L<2>

XDP_BPM_L<0>

FSB_CPURST_LFSB_LOCK_LCPU_INIT_LFSB_IERR_LFSB_BREQ0_L

FSB_DRDY_LFSB_DEFER_L

TP_CPU_HFPLL

TP_CPU_A37_LTP_CPU_A38_LTP_CPU_A39_L

TP_CPU_A32_LTP_CPU_A33_LTP_CPU_A34_LTP_CPU_A35_LTP_CPU_A36_L

TP_CPU_APM0_LTP_CPU_APM1_L

CPU_SMI_L

CPU_INTRCPU_NMI

CPU_STPCLK_LCPU_IGNNE_LCPU_FERR_LCPU_A20M_LFSB_ADSTB_L<1>

FSB_A_L<30>FSB_A_L<31>

FSB_A_L<27>FSB_A_L<28>FSB_A_L<29>



FSB_A_L<21>FSB_A_L<20>FSB_A_L<19>FSB_A_L<18>FSB_A_L<17>FSB_REQ_L<4>FSB_REQ_L<3>

FSB_REQ_L<1>FSB_REQ_L<0>

FSB_REQ_L<2>

FSB_ADSTB_L<0>


FSB_A_L<13>FSB_A_L<12>FSB_A_L<11>FSB_A_L<10>FSB_A_L<9>FSB_A_L<8>

FSB_A_L<6>FSB_A_L<5>FSB_A_L<4>FSB_A_L<3>

XDP_TCK

XDP_TDI

XDP_TMS

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

FSB_DBSY_L

XDP_BPM_L<1>

=PP1V05_S0_CPUFSB_TRDY_LFSB_RS_L<2>

FSB_HIT_LFSB_HITM_L

XDP_BPM_L<5>

FSB_RS_L<1>FSB_RS_L<0>

63

63

63

63

11

11

11

11

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

48

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79 9

9

9

79

9

79

79

79

12

12

79

57

79

79

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

21

26

11

11

11

79

79

79

79

12

12

79

12

12

79

79

79

79

79

79

79

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

11

11

11

8

8

8

12

79

8 79

79

12

12

79

79

79

12

5

5

57

12

21

21

21

12

79

79

79

79

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

34

5

34

34

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

79

5

6

6

34

34

6

6

6

14

10

10

48

11

11

7

11

7

7

11

11

11

11

11

5

21

79

5

5

12

6

6

6

6

6

6

6

6

6

6

6

21

21

21

21

21

21

21

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

7

7

7

7

7

7

5

11

7 12

12

5

5

11

12

12

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VSS_82

VSS_83

VSS_84VSS_85

VSS_87

VSS_86

VSS_88

VSS_89VSS_90

VSS_92

VSS_91

VSS_93

VSS_94

VSS_95

VSS_97

VSS_96

VSS_100

VSS_98VSS_99

VSS_102

VSS_101

VSS_105

VSS_103VSS_104

VSS_106VSS_107

VSS_110VSS_109

VSS_108

VSS_111VSS_112

VSS_115VSS_114

VSS_113

VSS_116

VSS_117VSS_118

VSS_120

VSS_119

VSS_123

VSS_121

VSS_122

VSS_124

VSS_125

VSS_128

VSS_126

VSS_127

VSS_129

VSS_130

VSS_133

VSS_131VSS_132

VSS_134

VSS_135

VSS_138

VSS_136VSS_137

VSS_139VSS_140

VSS_141

VSS_143VSS_142

VSS_146

VSS_144VSS_145

VSS_147VSS_148

VSS_151VSS_150

VSS_149

VSS_152

VSS_153

VSS_156VSS_155

VSS_154

VSS_157

VSS_158VSS_159

VSS_161

VSS_160

VSS_162

VSS_1

VSS_2

VSS_3

VSS_5

VSS_4

VSS_6VSS_7

VSS_8

VSS_10

VSS_9

VSS_11VSS_12

VSS_15

VSS_13

VSS_14

VSS_16

VSS_17VSS_18

VSS_19VSS_20

VSS_23VSS_22

VSS_21

VSS_24

VSS_25

VSS_28

VSS_27

VSS_26

VSS_29

VSS_30

VSS_33

VSS_32

VSS_31

VSS_34

VSS_35

VSS_38

VSS_37VSS_36

VSS_39VSS_40

VSS_41VSS_42

VSS_43

VSS_46

VSS_44VSS_45

VSS_47VSS_48

VSS_51

VSS_49

VSS_50

VSS_52VSS_53

VSS_56

VSS_54

VSS_55

VSS_57

VSS_58VSS_59

VSS_60

VSS_61

VSS_63

VSS_62

VSS_64

VSS_65

VSS_66

VSS_69

VSS_68

VSS_67

VSS_70

VSS_71

VSS_74

VSS_73VSS_72

VSS_75

VSS_76

VSS_79

VSS_78VSS_77

VSS_80VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66VCC_65

VCC_63VCC_62

VCC_61

VCC_59VCC_60

VCC_58

VCC_57VCC_56

VCC_54VCC_55

VCC_53

VCC_51VCC_52

VCC_49

VCC_50

VCC_48

VCC_47

VCC_46

VCC_44

VCC_45

VCC_43

VCC_41

VCC_42

VCC_40

VCC_39

VCC_38

VCC_36

VCC_37

VCC_33

VCC_35VCC_34

VCC_31

VCC_32

VCC_29VCC_30

VCC_28

VCC_26VCC_27

VCC_23

VCC_25

VCC_24

VCC_22VCC_21

VCC_20

VCC_18VCC_19

VCC_17

VCC_16VCC_15

VCC_13

VCC_14

VCC_12

VCC_10VCC_11

VCC_8

VCC_9

VCC_7

VCC_6

VCC_5

VCC_3

VCC_4

VCC_2VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82VCC_83

VCC_86VCC_85

VCC_87

VCC_89VCC_88

VCC_90VCC_91

VCC_92

VCC_94VCC_93

VCC_95

VCC_96VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1

VCCP_2

VCCP_3VCCP_4

VCCP_5

VCCP_6VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12

VCCP_13

VCCP_14

VCCP_16

VCCP_15

VCCA

VID0

VID1VID2

VID3

VID4VID5

VID6

VSSSENSE

VCCSENSE

VCC_73(3 OF 4)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USEZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB)TO CONNECT A DIFFERENCTIAL PROBEBETWEEN VCCSENSE AND VSSSENSE AT THELOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTHVCCSENSE AND VSSSENSE LINESLAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHMTRANSMISSION LINE

VID FOR CPU POWER SUPPLYIF NO USE, NEED PULL-UP ORPULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

79 9

79 9

79 9

79 9

79 9

79 9

1/16W1%

402MF-LF

100

2

1R0803

79 9

79 57

79 57

100MF-LF402

1%1/16W2

1R0802

OMIT

BGA

YONAHCPU

V22V5V2U24U21U6U3T26T23T4B6T1R25R22R5R2P24P21P6

P3N26

A26

N23N4N1

M25M22M5M2

L24L21L6

A23

L3K26K23K4K1

J25J22J5J2

H24

A19

H21H6H3

G26G23G1G4

F25F22F2

A16

F19F16F13F11F8F5

E24E21E19E16

A14

E14E11E8E6E3

D26D23D19D16D13

A11

D11D8D4D1

C25C22C2

C19C16C14

A8

C11C8C5

AF24AF21AF19

B24

AF16AF13AF11AF8AF6AF3AE26AE23AE19AE16

B21

AE14AE11AE8AE4AE1AD25AD22AD19AD16AD13

B19

AD11AD8AD5AD2AC24AC21AC19AC16AC14AC11

B16

AC8AC6AC3AB26AB23AB19AB16AB13AB11AB8

B13

AB4AB1AA25AA22AA19AA16AA14AA11AA8AA5

B11

AA2Y24Y21Y6Y3W26W23W4W1V25

B8

A4 U0700

OMIT

BGA

YONAHCPU

AE7

AE2AF2AE3AF4AE5AF5AD6

AF7

N21M21K21J21M6K6J6G21

W21V21T6T21R6R21N6

V6

B26

AF18AF17AF15AF14AF12AF10AF9AE20AE18AE17

A20

AE15AE13AE12AE10AE9AD18AD17AD15AD14AD12

A18

AD10AD9AD7AC18AC17AC15AC13AC12AC9AC7

A17

AB7AB20

AB18AB17AB15AB14AB12AB10AC10AB9

A15

AA20AA18AA17AA15AA13AA12AA10AA9AA7F20

A13

F18F17F15F14F12F10F9F7

E20E18

A12

E17E15E13E12E10E9E7

D18D17D15

A10

D14D12D10D9

C18C17C15C13C12C10

A9

C9B20B18B17B15B14B12B10B9

AF20

B7

A7 U0700

CPU 2 OF 2-PWR/GNDSYNC_MASTER=M42

051-6941 A

8 104

SYNC_DATE=11/16/2005

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<0>CPU_VID<1>CPU_VID<2>CPU_VID<3>CPU_VID<4>CPU_VID<5>CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

63

63

63

51

11

51

9

9

9

8

7

8

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NOTE: This cap is shared

CPU VCORE HF AND BULK DECOUPLING

VCCP (CPU I/O) Decoupling

Will probably be removed before productionResistors to allow for override of CPU VID

CPU VCORE VID Connections4x 470uF. 20x 22uF 0805

1x 10uF, 1x 0.01uF

between CPU and NB

1x 470uF, 6x 0.1uF 0402

VCCA (CPU AVdd) Decoupling

6.3V20%X5R805

22uF2

1 C09066.3V20%X5R

22uF

8052

1 C0904

6.3V20%X5R

22uF

8052

1 C09166.3V20%X5R

22uF

8052

1 C0914

6.3V20%X5R

22uF

8052

1 C09086.3V20%X5R

22uF

8052

1 C09036.3V20%X5R

22uF

8052

1 C09076.3V20%X5R

22uF

8052

1 C09026.3V20%X5R805

22uF2

1 C0901

6.3V20%X5R805

22uF2

1 C09136.3V20%X5R

22uF

8052

1 C09126.3V20%X5R

22uF

8052

1 C09116.3V20%X5R

22uF

8052

1 C0919

6.3V20%X5R

22uF

8052

1 C0900

6.3V20%X5R

22uF

8052

1 C0910

0.1UF

CERM402

20%10V2

1 C093620%

2.5VTANTD2T

470uF-7MOHM

CRITICAL

32

1C0935

6.3V20%X5R

22uF

8052

1 C09056.3V20%X5R

22uF

8052

1 C0909

20%X5R

22uF6.3V805

2

1 C09156.3V20%X5R

22uF

8052

1 C0917

0.1UF

CERM402

20%10V2

1 C09370.1UF

CERM402

20%10V2

1 C09380.1UF

CERM402

20%10V2

1 C09390.1UF

CERM402

20%10V2

1 C09400.1UF

CERM402

20%10V2

1 C0941

22uF

X5R20%6.3V805

2

1 C0918

20%

D2T2.5VTANT

470uF-7MOHM

CRITICAL

3 2

1 C095020%2.5VD2TTANT

470uF-7MOHM

CRITICAL

3 2

1 C0952470uF-7MOHM20%2.5VTANTD2T

CRITICAL

3 2

1 C0953470uF-7MOHM20%2.5VTANTD2T

CRITICAL

3 2

1 C0954

16V0.01UF

CERM402

20%2

1 C0981

X5R

10uF20%

6.3V603

2

1C0980

0

5%1/16WMF-LF402

21

R0996

0

5%1/16WMF-LF402

21

R0995

402MF-LF1/16W5%

021

R0993

402

1/16W5%

0

MF-LF

21

R0994

402MF-LF1/16W5%

021

R0991

402MF-LF1/16W5%

021

R0992

402MF-LF1/16W5%

021

R0990

CPU Decoupling & VID

051-6941

SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

A

9 104

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

=PP1V05_S0_CPU

IMVP6_VID<1>

CPU_VID<6>

IMVP6_VID<4>CPU_VID<4>





CPU_VID<1>

IMVP6_VID<6>

63

63

11

51

63

8

79

79

79

79

79

79

79

8

8

7

57

8

57 8

57 8

57 8

57 8

57 8

8

57

www.vinafix.vn

D+D-

ALERT*/

THM*

SCLKSDATA

VDD

GND

THM2*

IO

IO

IN

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PLACE U1001 NEAR THE U1200

ADD GND GUARD TRACECPU_THERMD_N ON SAMEFOR CPU_THERMD_P AND

10 MIL SPACING

LAYER.10 MIL TRACE

ROUTE CPU_THERMD_P AND

CPU ZONE THERMAL SENSOR

LAYOUT NOTE:

CPU_THERMD_N

(TO CPU INTERNAL THERMAL DIODE)

LAYOUT NOTE:

PLACEHOLDER ADT7461A

CRITICAL

MSOPADT7461

1

4

78

5

32

6

U1001

MF-LF

499

1/16W402

1%

21

R1001

CERM50V0.001uF10%

4022

1 C1001

X5R

0.1UF16V10%

4022

1 C1002

499

1%MF-LF402

1/16W

21

R1002

1/16W5%

402

10K

MF-LF2

1R100510K1/16W402MF-LF5%

2

1R1006

051-6941 A

10 104

SYNC_MASTER=M42 SYNC_DATE=10/07/2005

CPU MISC1-TEMP SENSOR

SMB_THRM_DATASMB_THRM_CLK

THRM_ALERT

THRM_ALERT_L

=PP3V3_S0_THRM_SNR

CPU_THERMD_N

CPU_THERMD_PTHRM_CPU_DX_NTHRM_CPU_DX_P

27

27

63

7

7

50

50

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IO

IO

IO

IO

IO

IO

OUT

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTOR’S FBO PIN.

518S0320

(TCK)

(FBO)

CPU ITP700FLEX DEBUG SUPPORT

(DEBUG PORT ACTIVE)(DBR#)

(DBA#)

NC

NC

NCTO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(AND WITH RESET BUTTON) (DEBUG PORT RESET)

(FROM CK410M HOST 133/167MHZ)

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEXROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

MF-LF

22.61%

1/16W402

ITP

21R1100

ITP

402

1%

22.6

1/16WMF-LF

21R1102

54.91/16W1%

402MF-LF

ITP

2

1R1103

402X5R16V10%0.1UF2

1C1100

1/16W240

402MF-LF5%

2

1R1104

F-RT-SM52435-2872

CRITICALITPCONN

987654

30

3

29

282726252423222120

2

19181716151413121110

1

J1101

1/16W402

54.91%MF-LF2

1R1101

680

402

5%1/16WMF-LF2

1R1106

CPU ITP700FLEX DEBUGSYNC_DATE=10/12/2005

051-6941 A

11 104

SYNC_MASTER=M42

ITPRESET_L

XDP_DBRESET_L

ITP_TDOCPU_XDP_CLK_PXDP_TCKXDP_BPM_L<5>XDP_BPM_L<4>XDP_BPM_L<3>XDP_BPM_L<2>XDP_BPM_L<1>

XDP_TRST_L

CPU_XDP_CLK_N

XDP_TMS

=PP1V05_S0_CPU

=PP3V3_S5_SB_PM

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<0>

FSB_CPURST_L

=PP1V05_S0_CPU

63

63

11

11

9

63

79

9

26

79

8

26

12

8

79

7

34

7

7

7

23

7

7

7

7

www.vinafix.vn

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IN

IO

IN

IO

IO

HD4*

HD6*

HD16*

HTRDY*HSLPCPU*

HRS1*HRS0*

HHITM*HLOCK*

HHIT*

HDSTBP2*HDTSBP3*

HDSTBP1*HDSTBP0*

HDSTBN3*

HDSTBN1*HDSTBN2*

HDSTBN0*

HDINV2*HDINV3*

HDINV1*HDINV0*

HDVREFHDRDY*HDPWR*

HDEFER*HDBSY*

HCPURST*HBREQ0*HBPRI*HBNR*HAVREF

HCLKIN*HCLKIN

HYSWING

HYRCOMPHYSCOMP

HXSWINGHXSCOMPHXRCOMP

HA13*

HADS*HADSTB0*

HD3*HD2*HD1*HD0*

HD63*HD62*HD61*HD60*HD59*HD58*HD57*HD56*HD55*HD54*HD53*HD52*HD51*HD50*HD49*HD48*HD47*HD46*HD45*HD44*HD43*HD42*HD41*HD40*HD39*HD38*HD37*HD36*HD35*HD34*HD33*HD32*HD31*

HD29*HD28*HD27*HD26*HD25*HD24*HD23*HD22*HD21*HD20*HD19*HD18*HD17*

HD15*

HD10*HD11*HD12*HD13*HD14*

HD5*

HD7*HD8*HD9*

HA30*HA29*HA28*HA27*HA26*HA25*HA24*HA23*

HA31*

HA20*HA19*HA18*

HA16*HA15*HA14*

HA21*HA22*

HA17*

HA9*HA8*HA7*HA6*HA5*HA4*HA3*

HA10*HA11*HA12*

HADSTB1*

HREQ0*HREQ1*HREQ2*HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

402X5R16V10%

0.1uF2

1C1211 2001%1/16WMF-LF4022

1R1211

1001%1/16WMF-LF4022

1R1210

54.91%

1/16WMF-LF

4022

1R1220

402MF-LF1/16W

1%24.9

2

1R1221

2211%1/16WMF-LF4022

1R1225

1%1/16WMF-LF402

100

2

1R12260.1uF

402X5R16V10%

2

1 C1226

402X5R16V10%0.1uF

2

1 C1236

2211%1/16WMF-LF4022

1R123554.9

1%1/16WMF-LF

4022

1R1230

1%1/16WMF-LF402

100

2

1R1236

402MF-LF1/16W

1%24.9

2

1R1231

BGANB

945GM

OMIT

W1U1Y1

E4E2E1

E7E3

D6E6B4

A8F8B8G8D8

B3D4D3

K13

AC5AA5T6K3

AC4Y5T7K4

H8J9

AB10U3W8J7

C3A7

K1K9G2

AC8AD4

AD10AB5

G1

AC6AD7AC1AD9AD1AC2AB3

AC11AB11AC9

K2

AB4AA1Y8

AA10AA6AA2AA7AA4W2AB8

H3

Y10W5Y7Y3W3W4AA9AB7T5W6

J6

T9U5W7T4T8T1W9T11U11U9

H1

U7T3W11T10G4K11J3H4J8K7

J1F1

B7

AG1AG2

C7F6C6J13C13B9E8

F9G12F11G11E11C9

D14C14

H9

A14C12B14B12F12G13E13A13A12C11A11D12F14J15H13J14D9G14J12H11

U1200

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

NB CPU Interface

A

12 104

051-6941

NB_FSB_XRCOMP

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

FSB_RS_L<2>

FSB_REQ_L<4>

FSB_D_L<30>

FSB_REQ_L<3>FSB_REQ_L<2>FSB_REQ_L<1>FSB_REQ_L<0>

FSB_ADSTB_L<1>


FSB_A_L<3>FSB_A_L<4>FSB_A_L<5>FSB_A_L<6>FSB_A_L<7>FSB_A_L<8>FSB_A_L<9>

FSB_A_L<17>




FSB_A_L<31>

FSB_A_L<23>FSB_A_L<24>FSB_A_L<25>FSB_A_L<26>FSB_A_L<27>FSB_A_L<28>FSB_A_L<29>FSB_A_L<30>

FSB_D_L<14>FSB_D_L<13>FSB_D_L<12>FSB_D_L<11>

FSB_D_L<15>

FSB_D_L<18>FSB_D_L<19>FSB_D_L<20>FSB_D_L<21>FSB_D_L<22>FSB_D_L<23>FSB_D_L<24>FSB_D_L<25>FSB_D_L<26>FSB_D_L<27>FSB_D_L<28>FSB_D_L<29>

FSB_D_L<31>FSB_D_L<32>FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>FSB_D_L<45>FSB_D_L<46>FSB_D_L<47>FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>FSB_D_L<52>FSB_D_L<53>FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>

FSB_ADSTB_L<0>FSB_ADS_L

FSB_A_L<13>

NB_FSB_XSCOMPNB_FSB_XSWING

NB_FSB_YSCOMPNB_FSB_YRCOMP

NB_FSB_YSWING

FSB_CLK_NB_PFSB_CLK_NB_N

FSB_BNR_LFSB_BPRI_LFSB_BREQ0_LFSB_CPURST_LFSB_DBSY_LFSB_DEFER_LFSB_DPWR_LFSB_DRDY_L

FSB_DINV_L<3>

FSB_DSTBN_L<1>

FSB_DSTBP_L<0>

FSB_HIT_L

FSB_LOCK_LFSB_HITM_L

FSB_RS_L<0>FSB_RS_L<1>

FSB_SLPCPU_LFSB_TRDY_L

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<3>

FSB_D_L<7>FSB_D_L<8>FSB_D_L<9>FSB_D_L<10>



NB_FSB_VREF

FSB_DINV_L<2>FSB_DINV_L<1>

FSB_DSTBN_L<0>

FSB_DINV_L<0>

FSB_DSTBP_L<3>FSB_DSTBP_L<2>FSB_DSTBP_L<1>

FSB_DSTBN_L<3>FSB_DSTBN_L<2>

FSB_D_L<17>

63

63

63

34

34

34

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

19

19

19

79

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

79

79

79

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

12

12

12

7

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

34

34

5

5

5

5

5

5

7

7

7

7

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

www.vinafix.vn

CRT_BLUE*CRT_BLUE

CRT_GREEN*CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNCCRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF

TV_IRTNA

TV_DACB_OUT

TV_DACC_OUT

TV_DACA_OUT

LB_DATA2LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLKLB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFLL_VREFH

L_VBG

L_IBG

L_DDC_CLKL_DDC_DATA

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN0EXP_A_RXN1

EXP_A_RXN2



EXP_A_RXN7


EXP_A_RXN10


EXP_A_RXN13


EXP_A_RXP0

EXP_A_RXP1EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11

EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2


EXP_A_TXN4

EXP_A_TXN7


EXP_A_TXN10


EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9

EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13

EXP_A_TXP14

EXP_A_TXP15

L_CLKCTLB

L_BKLTENL_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is usedCan leave all signals NC if LVDS is not implemented

CRT Disable

TV-Out Disable

Composite: DACA only

TV-Out Signal Usage:

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

Unused DAC outputs must remain powered, but can omit

S-Video: DACB & DACC only

connect to GND through 75-ohm resistors.

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

Component: DACA, DACB & DACC

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

filtering components. Unused DAC outputs should

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

VCCD_LVDS must remain powered with proper decoupling.

LVDS Disable

Otherwise, tie VCCD_LVDS to GND also.

SDVOC_CLKPSDVOC_BLUESDVOC_GREENSDVOC_RED

SDVOB_BLUESDVOB_CLKP

SDVOB_RED#SDVOB_GREEN#SDVOB_BLUE#SDVOB_CLKNSDVOC_RED#SDVOC_GREEN#SDVOC_BLUE#SDVOC_CLKN

SDVOB_REDSDVOB_GREEN

SDVO_FLDSTALLSDVO_INTSDVO_TVCLKIN

SDVO_INT#SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

BGANB

945GM

OMIT

B19B18

B16J20

A19

C18

A16

F29

F28

D30

D29

G30

F30

E27

E26

A37

A36

B35

B34

C37

B37

A33

A32

C32

C33F32

C35

B38G25

G26H29

H30

J30D32

G23

R40P36

N40M36

L40

J36H40

G36

AB40AA36

Y40

W36V40

T36

F40D36

T40

R36P40

N36

M40L36

J40

H36

AC40

AB36

AA40Y36

W40V36

G40

F36

R38P34

N38M34

L38

J34H38

G34

AB38AA34

Y38

W34V38

T34

F38D34

T38

R34P38

N34

M38L34

J38

H34

AC38

AB34

AA38Y34

W38V34

G38

F34

D38D40

H23

B21A21

J22

B22

C22

C25

C26

D23

E23

U1200 402MF-LF1/16W1%24.9

2

1R1310

051-6941 A

10413


NB PEG / Video Interfaces

CRT_HSYNC_R

CRT_VSYNC_R

LVDS_CLKCTLB

=PP1V5_S0_NB_PCIE

LVDS_BKLTCTL

LVDS_CLKCTLALVDS_BKLTEN

PEG_R2D_C_P<15>PEG_R2D_C_P<14>PEG_R2D_C_P<13>

PEG_R2D_C_P<11>PEG_R2D_C_P<12>





PEG_R2D_C_P<0>

PEG_R2D_C_N<15>

PEG_R2D_C_N<13>PEG_R2D_C_N<14>

PEG_R2D_C_N<12>PEG_R2D_C_N<11>PEG_R2D_C_N<10>PEG_R2D_C_N<9>PEG_R2D_C_N<8>PEG_R2D_C_N<7>

PEG_R2D_C_N<4>PEG_R2D_C_N<5>PEG_R2D_C_N<6>



PEG_D2R_P<15>

PEG_D2R_P<13>PEG_D2R_P<14>


PEG_D2R_P<8>PEG_D2R_P<9>PEG_D2R_P<10>




PEG_D2R_N<14>PEG_D2R_N<13>PEG_D2R_N<12>PEG_D2R_N<11>PEG_D2R_N<10>

PEG_D2R_N<8>

PEG_D2R_N<6>PEG_D2R_N<5>PEG_D2R_N<4>PEG_D2R_N<3>PEG_D2R_N<2>PEG_D2R_N<1>PEG_D2R_N<0>

PEG_COMP

LVDS_DDC_DATALVDS_DDC_CLK

LVDS_IBGTP_LVDS_VBG

LVDS_VREFHLVDS_VREFL

LVDS_VDDEN

LVDS_A_CLK_NLVDS_A_CLK_PLVDS_B_CLK_NLVDS_B_CLK_P

LVDS_A_DATA_N<0>LVDS_A_DATA_N<1>LVDS_A_DATA_N<2>

LVDS_A_DATA_P<0>LVDS_A_DATA_P<1>LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>LVDS_B_DATA_N<1>LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0>LVDS_B_DATA_P<1>LVDS_B_DATA_P<2>

CRT_IREF

CRT_DDC_DATA

CRT_RED_L

CRT_DDC_CLK

CRT_RED

CRT_GREENCRT_GREEN_L

CRT_BLUECRT_BLUE_L

PEG_D2R_N<15>

PEG_D2R_N<9>

PEG_D2R_N<7>

TV_IRTNCTV_IRTNBTV_IRTNATV_IREF

TV_DACC_OUTTV_DACB_OUTTV_DACA_OUT

63

19

19

19

19

19

19

19

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

65

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

65

65

65

19

19

19

19

19

19

19

www.vinafix.vn

SM_CS0*RSVD15

RSVD14

SM_CKE2

RSVD2RSVD3

RSVD6

RSVD4

RSVD5

RSVD8RSVD7

RSVD9

RSVD1

RSVD10RSVD11

RSVD12

RSVD13

CFG1CFG0

CFG2

CFG3CFG4

CFG6

CFG5

CFG7

CFG8

CFG9CFG10

CFG11CFG12

CFG13

CFG14

CFG17

CFG16

CFG15

CFG18

CFG19

CFG20

PM_BM_BUSY*PM_EXTTS0*

PM_EXTTS1*PW_THRMTRIP*

PWROK

RSTIN*

SDVO_CTRLCLKSDVO_CTRLDATA

ICH_SYNC*

CLK_REQ*

NC2NC3

NC4

NC5NC6

NC7

NC8NC9

NC0NC1

NC13

NC12NC11

NC10

NC18

NC17NC16

NC15

NC14

SM_CK0

SM_CK1SM_CK2

SM_CK0*

SM_CK3

SM_CK1*

SM_CK2*

SM_CK3*

SM_CKE0SM_CKE1

SM_CKE3

SM_CS1*

SM_CS2*SM_CS3*

SMOCDCOMP0

SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0

SMVREF1

G_CLKIN*

G_CLKIND_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*D_REFSSCLKIN

DMI_RXN0

DMI_RXN1DMI_RXN2

DMI_RXN3

DMI_RXP0

DMI_RXP1DMI_RXP2

DMI_RXP3

DMI_TXN0

DMI_TXN1DMI_TXN2

DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC

PM

CLK

DMI

MISC

(2 OF 10)

RSVD

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

NC

IPU

IPU

NCNCIPU

IPUIPUIPU

IPUIPUIPU

IPU

IPUIPU

IPU

IPU

IPD

IPU

NCNCNCNCNC

NC

NCNCNCNCNCNCNCNCNC

NCNC

NC

NCNCNC(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)(H_PLLMON1#)(H_PLLMON1)

(TV_DCONSEL1)(TV_DCONSEL0)

(TESTIN#)(H_PROCHOT#)

(D_PLLMON1)(H_EDRDY#)

(LB_DATAP3)(LB_DATAN3)(LA_DATAP3)(LA_DATAN3)

IPD

IPD

NCNC

BGANB

945GM

OMIT

AK41

AK1

AV9

AT9

AF10

AL20

AU21AY20

BA12BA13

AW21

AY21AW12

AW13

AY29BA29

AT20

AU20

AY40

AW40

AY7

AW7

AT1

AR1

AW35

AY35

H27

H28

K30

J19

H7AF11

AG11

F7F3

R32

D27D28

A34A35

A41

J29

T32

AH34AH33

G6

H26F25

G28

B41

BA1BA2

BA3

BA39BA40

BA41

C1

A3

A39

A4A40

AW1

AW41AY1

AY41

B2

C41

D1

K28

AF33AG33

AG41AF37

AE41

AC37

AH41AG37

AF41

AE37

AG39

AF35

AE39AC35

AH39

AG35

AF39AE35

C40

D41

A27

A26

H32

G16

D16D19

E18F15

E15

F18

J26

J18

K27J25

H15G18

H16

C15K15

G15

D15E16

K18

K16

U1200

402MF-LF1/16W5%

10021

R1430

10K

402

5%

MF-LF1/16W

2

1R144110K

402

5%1/16WMF-LF

2

1R1440

0.1uF

402CERM10V20%

2

1 C14160.1uF

402CERM10V20%

2

1C1415

1/16W1%

402MF-LF

80.6

2

1R1410

1/16W1%

402MF-LF

80.6

2

1R1411

1/16W5%

402MF-LF

10K

2

1R1420

NB Misc InterfacesSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10414

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

NB_CLK_DREFCLKIN_NNB_CLK_DREFCLKIN_PNB_CLK_DREFSSCLKIN_NNB_CLK_DREFSSCLKIN_P

=PP3V3_S0_NB

NB_TV_DCONSEL1NB_TV_DCONSEL0

TP_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

NB_RST_IN_L

DMI_N2S_P<3>

DMI_N2S_P<1>DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>DMI_N2S_N<2>DMI_N2S_N<1>DMI_N2S_N<0>

DMI_S2N_P<3>DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>

DMI_S2N_N<3>DMI_S2N_N<2>DMI_S2N_N<1>DMI_S2N_N<0>

NB_CLK100M_GCLKIN_PNB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>MEM_CKE<0>

MEM_CLK_N<3>MEM_CLK_N<2>MEM_CLK_N<1>

MEM_CLK_P<3>

MEM_CLK_N<0>

MEM_CLK_P<2>MEM_CLK_P<1>MEM_CLK_P<0>

NB_SB_SYNC_LSDVO_CTRLDATASDVO_CTRLCLK

VR_PWRGOOD_DELAYPM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>NB_CFG<19>

NB_CFG<15>NB_CFG<16>NB_CFG<17>

NB_CFG<14>

NB_CFG<10>NB_CFG<9>

NB_CFG<7>

NB_CFG<5>NB_CFG<6>

NB_CFG<4>NB_CFG<3>NB_BSEL<2>

NB_BSEL<0>NB_BSEL<1>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>MEM_ODT<1>

MEM_CS_L<3>MEM_CS_L<2>MEM_CS_L<1>

MEM_CKE<2>

=PP1V8_S3_MEM_NB

MEM_RCOMP_LMEM_RCOMP

MEM_VREF_NB_0MEM_VREF_NB_1

TP_NB_XOR_LVDS_A34TP_NB_XOR_LVDS_D28TP_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

63

63

20

79

20

63

48

19

57

19

22

22

22

22

30

30

30

30

30

57

30

30

30

30

30

30

30

19

47

33

19

19

19

19

14

19

23

14

20

6

6

6

26

22

5

22

5

22

22

5

5

22

22

22

22

22

22

22

22

34

34

29

28

29

28

28

29

29

28

29

28

29

28

28

22

19

19

26

23

20

20

6

20

6

6

6

20

20

20

6

6

6

34

34

34

28

6

29

28

29

29

28

29

16

32

32

19

19

19

www.vinafix.vn

SA_DQ1

SA_DQ0

SA_DQ2

SA_DQ3SA_DQ4

SA_DQ5

SA_DQ6SA_DQ7

SA_DQ8

SA_DQ9SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13

SA_DQ14SA_DQ15

SA_DQ16

SA_DQ17SA_DQ18

SA_DQ19

SA_DQ20SA_DQ21

SA_DQ22

SA_DQ23SA_DQ24

SA_DQ25SA_DQ26

SA_DQ27

SA_DQ29SA_DQ28

SA_DQ30

SA_DQ31SA_DQ32

SA_DQ33

SA_DQ35SA_DQ34

SA_DQ36SA_DQ37

SA_DQ38

SA_DQ39SA_DQ40

SA_DQ41

SA_DQ42SA_DQ43

SA_DQ44

SA_DQ46SA_DQ45

SA_DQ47SA_DQ48

SA_DQ49

SA_DQ50SA_DQ51

SA_DQ52

SA_DQ53SA_DQ54

SA_DQ55

SA_DQ56SA_DQ57

SA_DQ58SA_DQ59

SA_DQ60

SA_DQ61SA_DQ62

SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0SA_DM1

SA_DM2

SA_DM3

SA_DM5

SA_DM4

SA_DM7SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6

SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4*

SA_DQS5*SA_DQS6*

SA_DQS7*

SA_MA1

SA_MA0

SA_MA2SA_MA3

SA_MA5

SA_MA4

SA_MA6

SA_MA7

SA_MA9

SA_MA8

SA_MA10SA_MA11

SA_MA12

SA_MA13

SA_RAS*

SA_RCVENIN*SA_RCVENOUT*

SA_WE*

SA_DQS1*SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

SB_DQ1

SB_DQ0

SB_DQ2

SB_DQ3SB_DQ4

SB_DQ5

SB_DQ6SB_DQ7

SB_DQ8

SB_DQ9SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13

SB_DQ14SB_DQ15

SB_DQ16

SB_DQ17SB_DQ18

SB_DQ19

SB_DQ20SB_DQ21

SB_DQ22

SB_DQ23SB_DQ24

SB_DQ25SB_DQ26

SB_DQ27

SB_DQ29SB_DQ28

SB_DQ30

SB_DQ31SB_DQ32

SB_DQ33

SB_DQ35SB_DQ34

SB_DQ36SB_DQ37

SB_DQ38

SB_DQ39SB_DQ40

SB_DQ41

SB_DQ42SB_DQ43

SB_DQ44

SB_DQ46SB_DQ45

SB_DQ47SB_DQ48

SB_DQ49

SB_DQ50SB_DQ51

SB_DQ52

SB_DQ53SB_DQ54

SB_DQ55

SB_DQ56SB_DQ57

SB_DQ58SB_DQ59

SB_DQ60

SB_DQ61SB_DQ62

SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0SB_DM1

SB_DM2

SB_DM3

SB_DM5

SB_DM4

SB_DM7SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6

SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4*

SB_DQS5*SB_DQS6*

SB_DQS7*

SB_MA1

SB_MA0

SB_MA2SB_MA3

SB_MA5

SB_MA4

SB_MA6

SB_MA7

SB_MA9

SB_MA8

SB_MA10SB_MA11

SB_MA12

SB_MA13

SB_RAS*

SB_RCVENIN*SB_RCVENOUT*

SB_WE*

SB_DQS1*SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NCNC

NCNC

BGA

945GMNB

OMIT

AY14AK24

AK23

AW14

AT16

AW17

AU17AV17

AU16

BA17BA16

AW16

AV12AV20

AT17

AU13

AU14

AY16

AH5

AG5

AN3

AP3

AL8

AN8

AM12

AN12

AM21

AM22

AN27

AN28

AU33

AT33

AK32

AK33

AP33AN35

AH31

AF8

AF4

AH6AG9

AJ32

AF6

AG4AF9

AG7

AL2AN1

AT3AV2

AN2

AP1

AK35

AW2

AY2

AL5AT5

AN9

AP9AK7

AK8AN7

AK9

AJ36

AL12AL14

AT12

AT13AP12

AP13

AR14AR12

AT21AP20

AM33

AP24

AL23AN20

AP21

AL22AP23

AP26

AM24AL28

AK28

AM31

AN24

AM26

AL27AK26

AN33

AM34AM36

AN38

AP31AR31

AJ34

AJ35

AH4

AR3AL9

AM14

AN22AL26

AM35

AJ33AY13

BA20

AV14

AU12

U1200

BGA

945GMNB

OMIT

AR27AK18

AK16

AU23

AW27

AV27

AV28AU27

AT28

AT27AR28

AY24

AR23AY27

BA27

AV24

AW24

AY23

AP5

AN5

AT7

AR7

AT10

AR10

AP16

AR16

AP29

AR29

AT35

AU35

AU39

AT39

AM40

AM39

AV41AT40

AP41

AJ3

AJ5

AK5AT4

AN41

AK3

AK4AR5

AV4

AY5AW5

AY9AY10

AW4

BA4

AK38

AW10

BA10

AJ8AK10

AH11

AK13AN10

AJ9AH10

AJ11

AJ38

AL15AP15

AM16

AN17AN14

AP14

AL19AM19

AW29AV29

AR41

AW31

AU31AU29

AT31

BA33AY33

AP34

AP35AU36

BA36

AP39

AP36

AR36

AV36BA38

AY38

AW38AR40

AP38

AV38AU38

AJ37

AK39

AN4

BA5AH8

AL17

BA31AT36

AR38

AK36AR24

AY28

AV23

AT24

U1200


NB DDR2 Interfaces

051-6941 A

10415

MEM_B_DQ<1>MEM_B_DQ<0>

MEM_B_DQ<2>MEM_B_DQ<3>MEM_B_DQ<4>MEM_B_DQ<5>MEM_B_DQ<6>MEM_B_DQ<7>MEM_B_DQ<8>MEM_B_DQ<9>MEM_B_DQ<10>


MEM_B_DQ<13>MEM_B_DQ<14>MEM_B_DQ<15>MEM_B_DQ<16>MEM_B_DQ<17>MEM_B_DQ<18>MEM_B_DQ<19>MEM_B_DQ<20>MEM_B_DQ<21>MEM_B_DQ<22>MEM_B_DQ<23>MEM_B_DQ<24>MEM_B_DQ<25>MEM_B_DQ<26>MEM_B_DQ<27>


MEM_B_DQ<30>MEM_B_DQ<31>MEM_B_DQ<32>MEM_B_DQ<33>


MEM_B_DQ<36>MEM_B_DQ<37>MEM_B_DQ<38>MEM_B_DQ<39>MEM_B_DQ<40>MEM_B_DQ<41>MEM_B_DQ<42>MEM_B_DQ<43>MEM_B_DQ<44>


MEM_B_DQ<47>MEM_B_DQ<48>MEM_B_DQ<49>MEM_B_DQ<50>MEM_B_DQ<51>MEM_B_DQ<52>MEM_B_DQ<53>MEM_B_DQ<54>MEM_B_DQ<55>MEM_B_DQ<56>MEM_B_DQ<57>MEM_B_DQ<58>MEM_B_DQ<59>MEM_B_DQ<60>MEM_B_DQ<61>MEM_B_DQ<62>MEM_B_DQ<63>

MEM_B_BS<1>MEM_B_BS<0>

MEM_B_BS<2>

MEM_B_CAS_LMEM_B_DM<0>MEM_B_DM<1>MEM_B_DM<2>MEM_B_DM<3>

MEM_B_DM<5>MEM_B_DM<4>

MEM_B_DM<7>MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>MEM_B_DQS_P<1>

MEM_B_DQS_P<3>



MEM_B_DQS_N<3>MEM_B_DQS_N<2>

MEM_B_DQS_N<4>MEM_B_DQS_N<5>MEM_B_DQS_N<6>MEM_B_DQS_N<7>

MEM_B_A<1>MEM_B_A<0>





MEM_B_A<10>MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>MEM_B_DQS_N<0>

MEM_A_DQ<1>MEM_A_DQ<0>

MEM_A_DQ<2>MEM_A_DQ<3>MEM_A_DQ<4>

MEM_A_DQ<6>MEM_A_DQ<7>MEM_A_DQ<8>MEM_A_DQ<9>MEM_A_DQ<10>


MEM_A_DQ<13>MEM_A_DQ<14>MEM_A_DQ<15>MEM_A_DQ<16>MEM_A_DQ<17>MEM_A_DQ<18>MEM_A_DQ<19>MEM_A_DQ<20>MEM_A_DQ<21>MEM_A_DQ<22>MEM_A_DQ<23>MEM_A_DQ<24>MEM_A_DQ<25>MEM_A_DQ<26>MEM_A_DQ<27>


MEM_A_DQ<30>MEM_A_DQ<31>MEM_A_DQ<32>MEM_A_DQ<33>


MEM_A_DQ<36>MEM_A_DQ<37>MEM_A_DQ<38>MEM_A_DQ<39>MEM_A_DQ<40>MEM_A_DQ<41>MEM_A_DQ<42>MEM_A_DQ<43>MEM_A_DQ<44>


MEM_A_DQ<47>MEM_A_DQ<48>MEM_A_DQ<49>MEM_A_DQ<50>MEM_A_DQ<51>MEM_A_DQ<52>MEM_A_DQ<53>MEM_A_DQ<54>MEM_A_DQ<55>MEM_A_DQ<56>MEM_A_DQ<57>MEM_A_DQ<58>MEM_A_DQ<59>MEM_A_DQ<60>MEM_A_DQ<61>MEM_A_DQ<62>MEM_A_DQ<63>

MEM_A_BS<1>MEM_A_BS<0>

MEM_A_BS<2>

MEM_A_CAS_LMEM_A_DM<0>MEM_A_DM<1>MEM_A_DM<2>MEM_A_DM<3>

MEM_A_DM<5>MEM_A_DM<4>

MEM_A_DM<7>MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>MEM_A_DQS_P<1>

MEM_A_DQS_P<3>



MEM_A_DQS_N<3>MEM_A_DQS_N<2>

MEM_A_DQS_N<4>MEM_A_DQS_N<5>MEM_A_DQS_N<6>MEM_A_DQS_N<7>

MEM_A_A<1>MEM_A_A<0>





MEM_A_A<10>MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>MEM_A_DQS_N<0>

MEM_A_DQ<5>

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

www.vinafix.vn

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57VCCAUX_NCTF56

VCCAUX_NCTF55



VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47

VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39


VCCAUX_NCTF36


VCCAUX_NCTF32

VCCAUX_NCTF33

VCCAUX_NCTF31


VCCAUX_NCTF27

VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24

VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23


VCCAUX_NCTF41

VCCAUX_NCTF19

VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14

VCCAUX_NCTF15


VCCAUX_NCTF11



VCCAUX_NCTF6


VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7

VSS_NCTF8

VSS_NCTF5VSS_NCTF6

VSS_NCTF4

VSS_NCTF2VSS_NCTF3

VSS_NCTF0VSS_NCTF1

VCC_NCTF72VCC_NCTF71

VCC_NCTF70



VCC_NCTF65

VCC_NCTF64

VCC_NCTF61

VCC_NCTF62

VCC_NCTF63

VCC_NCTF60


VCC_NCTF59


VCC_NCTF53

VCC_NCTF54

VCC_NCTF52

VCC_NCTF50

VCC_NCTF51

VCC_NCTF49

VCC_NCTF48



VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42


VCC_NCTF36

VCC_NCTF37

VCC_NCTF34

VCC_NCTF35

VCC_NCTF33

VCC_NCTF31

VCC_NCTF32

VCC_NCTF30

VCC_NCTF29


VCC_NCTF26



VCC_NCTF21

VCC_NCTF20

VCC_NCTF18

VCC_NCTF19


VCC_NCTF15



VCC_NCTF10

VCC_NCTF8VCC_NCTF9

VCC_NCTF7

VCC_NCTF6VCC_NCTF5

VCC_NCTF4

VCC_NCTF3VCC_NCTF2

VCC_NCTF0VCC_NCTF1

(7 OF 10)

NCTF

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NCTF balls are Not Critical To FunctionThese connections can break without

impacting part performance.

Layout Note:Place near pin BA23

Place near pin BA15Layout Note:

Layout Note:Place in cavity

1.05V or 1.5V

1.05V, External Graphics: 1500mA Max1.5V, Internal Graphics: 5500mA Max

1.05V, Internal Graphics: 3500mA Max

667MTs 1700mA 3200mA533MTs 1500mA 2800mA400MTs 1300mA 2400mASpeed 1 Channel 2 Channel

1.8V Max Current

BGA

NB

945GM

OMIT

AT6

AV6

AW6

AY6

BA6

AP8

AR8

AT8

AV8

AW8

AT34

AY8

BA8

AK11

AG12

AH12

AJ12

AK12

AH13

AJ13

AJ14

AU34

AJ15

AR15

AT15

AU15

AV15

AW15

AY15

BA15

AH16

AJ16

AV34

AH17

AJ17

AJ18

AJ19

AK19

AP19

AR19

AT19

AU19

AV19

AW34

AW19

AY19

BA19

AK20

AK21

AJ22

AK22

AP22

AR22

AT22

AY34

AU22

AV22

AW22

AY22

BA22

AJ23

BA23

AH24

AJ24

AH25

BA34

AJ25

AH26

AJ26

AR26

AT26

AU26

AV26

AW26

AY26

BA26

AU40

AH27

AJ27

AH28

AJ28

AH29

AJ29

AK29

AL29

AM29

AM30

AM41

AN30

AP30

AR30

AT30

AU30

AV30

AW30

AY30

BA30

AJ1

AV1

AJ6

AK6

AL6

AN6

AP6

AR6

AR34

AT41

AU41

N19

Y19

AA19

AB19

L20

M20

N20

P20

W20

Y20

V32

AB20

AC20

L21

M21

N21

W21

AA21

AC21

L22

M22

W32

N22

P22

W22

Y22

AB22

AC22

L23

M23

N23

P23

Y32

Y23

AA23

AB23

M24

N24

P24

L25

M25

N25

L26

AA32

N26

P26

L27

M27

N27

P27

L28

M28

N28

P28

J33

R28

T28

U28

V28

Y28

AA28

AB28

L29

M29

P29

L33

R29

U29

V29

W29

Y29

AA29

L30

M30

N30

P30

N33

R30

T30

U30

V30

W30

Y30

AA30

M31

N31

P31

P33

R31

T31

V31

W31

AA31

J32

L32

M32

L16

N32

M16

N16

M17

N17

P17

L18

M18

N18

L19

M19

P32

W33

AA33

U1200

402

6.3VCERM-X5R

0.47uF20%

2

1 C1610

603

20%

X5R6.3V

10uF2

1 C162110uF6.3VX5R

20%

6032

1C1620

945GMNBBGA

OMIT

AE18

AE19

AE20AE21

AE22

AE23AE24

AE25

U17Y17

AC17

AE26AE27

AF23

AG23AF24

AG24

R15

T15

U15V15

W15

Y15AA15

AB15

AF25

AC15

AD15

AE15AF15

AG15

R16T16

U16

V16W16

AG25

Y16AA16

AB16

AC16AD16

AE16

AF16AG16

R17

T17

AF26

V17

W17AA17

AB17

AD17AE17

AF17

AG17R18

AF18

AG26

AG18R19

AF19AG19

AF20

AG20AF21

AG21

AF22AG22

AF27

AG27

R27

T27

T18

U18

V18

U27

W18

Y18

AA18AB18

AC18AD18

T19

U19V19

AD19

V27

R20T20

U20

V20AD20

R21T21

U21

V21AD21

W27

R22

T22U22

V22

AD22R23

T23U23

V23

AD23

Y27

R24

T24

U24V24

W24

Y24AA24

AB24AC24

AD24

AA27

R25T25

U25

V25W25

Y25

AA25AB25

AC25AD25

AB27

R26

T26U26

V26

W26Y26

AA26

AB26AC26

AD26

AC27AD27

U1200

402

6.3VCERM-X5R

0.47uF20%

2

1 C1611

402

6.3VCERM-X5R

0.47uF20%

2

1C1612

402

6.3VCERM-X5R

20%0.47uF

2

1 C1613

402

6.3VCERM-X5R

20%0.47uF

2

1C1614 402

6.3VCERM-X5R

20%0.47uF

2

1 C1615

NB Power 1SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10416

=PP1V8_S3_MEM_NBNB_VCCSM_LF1NB_VCCSM_LF2

NB_VCCSM_LF5NB_VCCSM_LF4

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB_VCCAUX

63

63

63

63

19

19

19

19

14

16

16

17

www.vinafix.vn

VTT0

VTT1VTT2

VTT3VTT4

VTT5

VTT6VTT7

VTT8

VTT9VTT10

VTT11

VTT12VTT13

VTT15VTT14

VTT16

VTT18VTT17

VTT19

VTT20VTT21

VTT22

VTT23VTT24

VTT25

VTT27

VTT26

VTT28VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35

VTT36VTT37

VTT39

VTT38

VTT40

VTT41

VTT42VTT43

VTT44

VTT45

VTT48

VTT46

VTT47

VTT49

VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57VTT56

VTT58VTT59

VTT60

VTT61VTT62

VTT64

VTT63

VTT65

VTT66

VTT67

VTT69

VTT68

VTT70

VTT71

VTT73VTT72

VTT74

VTT76VTT75

VCCSYNC

VCC_TXLVDS0

VCC_TXLVDS1VCC_TXLVDS2

VCC3G0

VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLLVCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0VCCA_CRTDAC1

VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBGVSSA_TVBG

VCCA_TVDACC0

VCCA_TVDACC1

VCCA_TVDACB0VCCA_TVDACB1

VCCA_TVDACA0

VCCA_TVDACA1

VCCD_HMPLL0VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0

VCCD_LVDS1

VCCD_TVDAC

VCC_HV1

VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17VCCAUX16

VCCAUX14

VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11VCCAUX10

VCCAUX0

VCCAUX1

VCCAUX2VCCAUX3

VCCAUX4

VCCAUX6VCCAUX5

VCCAUX9VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23

VCCAUX24

VCCAUX22

VCCAUX25

VCCAUX26

VCCAUX29

VCCAUX28VCCAUX27

VCCAUX30VCCAUX31

VCCAUX33VCCAUX32

VCCAUX34

VCCAUX35VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39

VCCAUX40

POWER

(8 OF 10)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1900mA Max

40mA Max

See VCCSYNC

150mA Max

120mA Max

45mA Max

45mA Max50mA Max50mA Max

10mA Max

24mA Max

20mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

60mA Max

2mA Max

800mA Max

1500mA Max VCC3G/3GPLL

OMIT

BGANB

945GM

L14

M14

M1

N1

P1R1

AB1

D2M2

N14

P2

R2M3

N3P3

R3

M4N4

P4

M5

P14

N5

P5

R5A6

M6P6

R6

M7N7

P7

R14

M8N8

P8

R8M9

N9P9

M10

N10P10

T14

R10

M11N11

P11

R11L12

M12N12

P12

R12

V14

T12

U12

V12W12

Y12

AA12AB12

L13M13

N13

W14

R13T13

U13

V13W13

Y13

AA13AB13

AC13AD13

AB14

AC14

G20

B39

G21

H41

H22

D21

H19

C28

B28A28

AH2

AH1

AF30AG30

AH30AJ30

AK30

AD12

AL30

AE12

AF12

AE13AF13

Y14

AE14AF14

AG14

AH14P15

AC31

AH15P16

P19

AH19AH20

AJ20

AH21AJ21

AH22

AE28

AE31

AF28

AG28AC29

AD29

AE29AF29

AG29

AC30AD30

AE30

AF31AK31

F20E20

D20

C20

F19

E19

H20

AF2

A38

AF1

C39

B26

E21

F21

AC33

G41

A30

B30

C30

B25

B23A23

L41N41

R41

V41Y41

AB41AJ41

U1200

402CERM-X5R

6.3V

0.47uF20%

2

1C171120%0.22uF6.3V

402X5R2

1 C1712

402

6.3VCERM-X5R

20%0.47uF

2

1C1713


NB Power 2

051-6941 A

10417

PP2V5_S0_NB_VCCA_CRTDAC

=PP1V5_S0_NB_VCCAUX

PP1V5_S0_NB_VCCD_QTVDAC

=PP3V3_S0_NB_VCC_HV

=PP1V5_S0_NB_VCCD_HMPLL

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

GND_NB_VSSA_TVBGPP3V3_S0_NB_VCCA_TVBG

PP1V5_S0_NB_VCCA_MPLL

=PP2V5_S0_NB_VCCA_LVDSGND_NB_VSSA_LVDS

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_DPLLAPP1V5_S0_NB_VCCA_DPLLB

GND_NB_VSSA_CRTDAC

GND_NB_VSSA_3GBG=PP2V5_S0_NB_VCCA_3GBGPP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0_NB_VCC3G

=PP2V5_S0_NB_VCC_TXLVDS

=PP2V5_S0_NB_VCCSYNC

NB_VTTLF_CAP1NB_VTTLF_CAP2

NB_VTTLF_CAP3

=PP1V05_S0_NB_VTT

PP1V5_S0_NB_VCCD_TVDAC

=PP1V5_S0_NB_VCCD_LVDS

63 19

63

63

63

63

19

16

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

www.vinafix.vn

VSS_1

VSS_0

VSS_2

VSS_3

VSS_4VSS_5

VSS_6VSS_7

VSS_9

VSS_8

VSS_10

VSS_11

VSS_12VSS_13

VSS_14

VSS_15VSS_16

VSS_17

VSS_19

VSS_18

VSS_20VSS_21

VSS_22

VSS_23VSS_24

VSS_25

VSS_26

VSS_28

VSS_27

VSS_29

VSS_30

VSS_31VSS_32

VSS_33

VSS_34VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40

VSS_41

VSS_42VSS_43

VSS_44

VSS_45VSS_46

VSS_47

VSS_49VSS_48

VSS_50VSS_51

VSS_52

VSS_53VSS_54

VSS_55

VSS_57VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65

VSS_66

VSS_67VSS_68

VSS_69

VSS_70VSS_71

VSS_73VSS_72

VSS_74

VSS_75VSS_76

VSS_77

VSS_78VSS_79

VSS_82

VSS_80

VSS_81

VSS_84VSS_83

VSS_85

VSS_87VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92VSS_93

VSS_94

VSS_96

VSS_95

VSS_97

VSS_98VSS_99

VSS_100

VSS_101VSS_102

VSS_103VSS_104

VSS_105

VSS_106VSS_107

VSS_108

VSS_109VSS_110

VSS_111

VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118

VSS_119

VSS_120VSS_121

VSS_122

VSS_123VSS_124

VSS_125

VSS_127

VSS_126

VSS_128VSS_129

VSS_130

VSS_131VSS_132

VSS_133

VSS_134VSS_135

VSS_137VSS_136

VSS_138

VSS_139VSS_140

VSS_141

VSS_143VSS_142

VSS_144

VSS_145VSS_146

VSS_147VSS_148

VSS_149

VSS_150VSS_151

VSS_152

VSS_153VSS_154

VSS_155

VSS_156

VSS_158

VSS_157

VSS_159

VSS_160

VSS_161VSS_162

VSS_164

VSS_163

VSS_165

VSS_166

VSS_167VSS_168

VSS_169VSS_170

VSS_172

VSS_171

VSS_173

VSS_174

VSS_175VSS_176

VSS_177

VSS_178VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269

VSS_270

VSS_268

VSS_266

VSS_267

VSS_265VSS_264

VSS_263

VSS_261

VSS_262

VSS_260VSS_259

VSS_258

VSS_256VSS_257

VSS_255

VSS_254VSS_253

VSS_251VSS_252

VSS_250

VSS_248VSS_249

VSS_247

VSS_246VSS_245

VSS_243

VSS_244

VSS_242

VSS_241VSS_240

VSS_238

VSS_239

VSS_237

VSS_236

VSS_235

VSS_233

VSS_234

VSS_232VSS_231

VSS_230

VSS_228

VSS_229

VSS_227

VSS_225

VSS_226

VSS_224VSS_223

VSS_222

VSS_220VSS_221

VSS_219VSS_218

VSS_217

VSS_215VSS_216

VSS_214

VSS_213VSS_212

VSS_210

VSS_211

VSS_209

VSS_207VSS_208

VSS_205

VSS_206

VSS_204

VSS_202

VSS_203

VSS_201

VSS_200

VSS_199

VSS_197

VSS_198

VSS_196

VSS_195

VSS_194

VSS_192

VSS_193

VSS_191VSS_190

VSS_189

VSS_187VSS_188

VSS_186

VSS_184

VSS_185

VSS_183VSS_182

VSS_180

VSS_181

VSS_273

VSS_274

VSS_276VSS_275

VSS_277

VSS_279VSS_278

VSS_281VSS_280

VSS_282

VSS_283VSS_284

VSS_286

VSS_285

VSS_287

VSS_288

VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301

VSS_302

VSS_300

VSS_304

VSS_303

VSS_305VSS_306

VSS_307

VSS_309VSS_308

VSS_311

VSS_310

VSS_312

VSS_313VSS_314

VSS_315

VSS_317VSS_316

VSS_318

VSS_319VSS_320

VSS_322

VSS_321

VSS_323

VSS_324VSS_325

VSS_327

VSS_326

VSS_328

VSS_329

VSS_330

VSS_332

VSS_331

VSS_334VSS_333

VSS_335

VSS_337

VSS_336

VSS_338VSS_339

VSS_340

VSS_342

VSS_343

VSS_341

VSS_345VSS_344

VSS_346VSS_347

VSS_348

VSS_350VSS_349

VSS_352

VSS_351

VSS_353

VSS_354

VSS_355VSS_356

VSS_357VSS_358

VSS_359

VSS_360

VSS

(10 OF 10)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NB945GM

BGA

OMIT

AF34

AG34

AK34

AN34D35

F35

G35H35

J35L35

AP40

M35

N35P35

R35

T35V35

W35

Y35AA35

AB35

AV40

AH35

AR35

AV35BA35

B36

C36AC36

AE36

AF36AG36

F41

AH36AN36

AW36

AY36D37

F37

G37H37

J37

L37

J41

M37

N37P37

R37

T37V37

W37

Y37AA37

AB37

M41

AH37AK37

C38AE38

AF38

AG38AH38

AM38

AT38D39

P41

F39

G39H39

J39L39

M39

N39P39

R39

T39

T41

V39

W39

Y39AA39

AB39AC39

AJ39

AN39AR39

AV39

W41

AW39AY39

AW23AL24

AU24BA24

A25

D25E25

H25

K25P25

B40

AK25

D26F26

K26M26

AN26

B27C27

F27

G27

AE40

J27

AK27

AM27AP27

E28J28

W28

AC28AD28

AM28

AF40

AP28AU28

AW28

BA28A29

B29C29

E29

G29K29

AG40

N29

T29AB29

AN29

AT29E30

AB30Y31

AB31

AG31

AH40

AJ31

AN31

AV31AY31

B32

G32AB32

AC32AE32

AF32

AJ40

AG32AH32

B33

D33F33

G33

H33M33

R33T33

AK40

V33

Y33AB33

AE33

AR33AV33

AW33

C34AC34

AE34

AN40

AA41

AC41

U1200NB

945GM

BGA

OMIT

AL1

C2F2

H2

J2N2

T2U2

Y2

AB2AD2

AJ2

AK2AP2

AR2

AT2G3

AA3AC3

AD3

AF3AG3

AH3

AL3AV3

AW3

AY3C4

F4J4

R4

U4Y4

AJ4

AL4AP4

AR4

AY4AD5

AF5AV5

B6

H6K6

N6

U6Y6

AB6

AD6AG6

D7G7

R7

AC7AF7

AH7

AJ7AL7

AP7

AV7BA7

C8K8

U8

AA8AD8

AG8

A9E9

G9

R9Y9

AB9AH9

AR9

AW9BA9

U10

W10AC10

AG10

AJ10AL10

AP10AV10

B11

D11J11

Y11AA11

AD11

E12H12

K12

AC12AY12

B13

D13F13

P13AG13

AL13

AM13AN13

AR13

AV13E14

H14

K14U14

AA14AD14

AK14

AT14BA14

A15

B15L15

M15

N15AK15

AM15AN15

C16

F16J16

AL16

AN16AV16

AK17

AM17AP17

AR17AY17

A18

D18H18

P18

AH18C19

G19

K19W19

AC19AN19

A20

B20K20

AA20

AM20AR20

AW20

C21H21

J21K21

P21

Y21AB21

AL21

AN21AR21

AV21

BA21A22

D22E22

F22

G22K22

AA22

C23F23

J23

K23W23

AC23AH23

AM23

AN23AT23 U1200


NB Grounds

051-6941 A

10418

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

800mA Max

Place in cavityLayout Note:

(MCH FSB 1.05V PWR)MCH VTT BYPASS

(SHARE C0940 470UF)

Layout Note:Place on the edge

40mA Max

(MCH HV BUFFER 3.3V PWR)MCH VCC_HV BYPASS

2mA Max

MCH VCCA_3GBG BYPASS(MCH PCIE/DMI BAND GAP 2.5V PWR)

1900mA Max

GMCH VCCAUX FILTER

100mA Max

45mA Max

GMCH VCCA_MPLL FILTER(MCH MEMORY PLL 1.5V PWR)

(HOST PLL 1.5V PWR)

45mA Max

GMCH VCCA_HPLL FILTER

1500mA Max

Layout Note:

close to MCHPlace L and C

Layout Note:3GPLL 10uF cap shouldbe placed in cavity

Layout Note:

GMCH VCC3G FILTER

(3GIO PLL 1.5V PWR)

Layout Note: Route to caps, then GND

10uF caps should

(PCI-E/DMI ANALOG 1.5V PWR)

GMCH VCCA_3GPLL FILTER

on opposite side.be close to MCH

1500mA Max

(MCH DISPLAY B PLL 1.5V PWR)

(MCH DISPLAY A PLL 1.5V PWR)

(MCH H/V SYNC 2.5V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH LVDS ANALOG 2.5V PWR)

(MCH LVDS DIGITAL 1.5V PWR)

(MCH LVDS DATA/CLK TX 2.5V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TVDAC DEDICATED PWR 1.5V)

Rail Totals:

3200mA Max

132mA Max

These are the power signals that leave the NB "block"Power Interface

2310mA Max?

150mA Max1900mA Max

2mA Max

1500mA Max

40mA Max? 40mA Max ?mA Max

3674mA Max

800mA Max ?mA Max

100mA Max 24mA Max

3200mA Max

70mA Max 60mA Max

?mA Max

?mA Max

10mA Max?1500mA Max

1500mA MaxGMCH CORE PWR 1.05V BYPASS

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

0.22uF

X5R6.3V20%

4022

1 C1907

X5R603

20%6.3V10uF

2

1 C1972

POLYSMB22.5V20%220UF

2

1C1970

6.3V20%

402X5R

0.22uF2

1 C19676.3V603

2.2uF20%CERM12

1 C19666.3V20%

603CERM

4.7uF2

1 C1965

470uF-7MOHM20%2.5VTANTD2T

CRITICAL

3 2

1 C1900

91nH

1210

21

L1970

0.1uF

402

20%10V

CERM 2

1C1916

6.3V20%

402X5R

0.22uF2

1 C1906

10V20%

402CERM

0.1uF2

1 C19156.3V20%

603X5R

10uF2

1C1914

6.3V402

20%X5R

0.22uF2

1 C1905

20%10V402CERM

0.1uF2

1 C1935

FERR-120-OHM-0.2A

0603

21

L1934

0.1uF

CERM20%10V402

2

1 C1937

4026.3V1uF

CERM10%

2

1 C1904

FERR-120-OHM-0.2A

0603

21

L1936

22uF

X5R805

20%6.3V 2

1C1934

22uF

X5R805

20%6.3V 2

1C1936

6.3VX5R20%

603

10uF2

1 C19036.3V20%

603X5R

10uF2

1 C1902

0.1uF10V20%

402CERM 2

1C1918

10V20%

402CERM

0.1uF2

1 C1976

1.0UH-220MA-0.12-OHM

0805

21

L1975

6.3V20%

603X5R

10uF2

1C1975MF-LF402

0.51

1/16W1%

21

R1975

10uF

X5R603

20%6.3V2

1 C1971

NB (GM) DecouplingSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10419

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3GMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_NB_VCCSYNC

TP_NB_XOR_LVDS_D27

LVDS_B_DATA_N<2..0>

=PP2V5_S0_NB_VCCSYNC=PP2V5_S0_NB_VCC_TXLVDS

CRT_HSYNC_RCRT_VSYNC_R

=PP1V5_S0_NB_TVDAC

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_B_DATAN<2..0>

TP_NB_XOR_LVDS_A34

MAKE_BASE=TRUETP_SDVO_CTRLCLK SDVO_CTRLCLK

MAKE_BASE=TRUETP_SDVO_CTRLDATA SDVO_CTRLDATA

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_A34

TP_NB_XOR_LVDS_A35

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D28

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_D27

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_A35

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_B_CLKP LVDS_B_CLK_P

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_B_DATAP<2..0> LVDS_B_DATA_P<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_B_CLKN LVDS_B_CLK_N

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_A_DATAN<2..0> LVDS_A_DATA_N<2..0>

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_A_DATAP<2..0> LVDS_A_DATA_P<2..0>

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_A_CLKN LVDS_A_CLK_N

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_A_CLKP LVDS_A_CLK_P

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_VREFH LVDS_VREFHMAKE_BASE=TRUETP_LVDS_VDDEN LVDS_VDDEN

MAKE_BASE=TRUETP_LVDS_VREFL LVDS_VREFL

MAKE_BASE=TRUETP_LVDS_DDC_DATA LVDS_DDC_DATA

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_IBG LVDS_IBG

MAKE_BASE=TRUETP_LVDS_DDC_CLK LVDS_DDC_CLKMAKE_BASE=TRUETP_LVDS_CLKCTLB LVDS_CLKCTLBMAKE_BASE=TRUETP_LVDS_CLKCTLA LVDS_CLKCTLA

MAKE_BASE=TRUETP_LVDS_BKLTCTL LVDS_BKLTCTL

MAKE_BASE=TRUETP_LVDS_BKLTEN LVDS_BKLTEN

TV_IRTNBTV_IRTNC

TV_IREFTV_IRTNA

TV_DACA_OUT

TV_DACC_OUTTV_DACB_OUT

=PP1V05_S0_NB_CRTCRT_REDCRT_GREENCRT_BLUECRT_RED_LCRT_GREEN_LCRT_BLUE_LCRT_IREF

CRT_DDC_CLK

MAKE_BASE=TRUETP_CRT_DDC_DATA CRT_DDC_DATAMAKE_BASE=TRUETP_CRT_DDC_CLK

=PPVCORE_S0_NB

=PP1V05_S0_NB_CRT

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_VCCAUX=PP1V5_S0_NB_VCCD_HMPLL

=PP1V8_S3_MEM_NB

=PP2V5_S0_NB_VCCA_3GBG

=PP3V3_S0_NB_VCC_HV=PP3V3_S0_NB

=PP1V05_S0_FSB_NB

=PP1V5_S0_NB_PCIE

=PP1V5_S0_NB_3G

=PP1V05_S0_NB_VTT

=PP1V5_S0_NB

=PPVCORE_S0_NB

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

=PP2V5_S0_NB_VCC_TXLVDS

=PP1V5_S0_NB_VCCD_LVDS

=PP2V5_S0_NB_VCCA_LVDS

GND_NB_VSSA_LVDSNO_TEST=TRUE

NC_GND_NB_VSSA_LVDSMAKE_BASE=TRUE

GND_NB_VSSA_CRTDAC

PP2V5_S0_NB_VCCA_CRTDAC

PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QTVDAC

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVBG

GND_NB_VSSA_TVBG

PP1V5_S0_NB_VCCA_DPLLAMAKE_BASE=TRUETP_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_DPLLBTP_NB_VCCA_DPLLBMAKE_BASE=TRUE

NB_CLK_DREFCLKIN_N

NB_CLK_DREFCLKIN_P

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFSSCLKIN_P

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_3GPLL PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

GND_NB_VSSA_3GBG

PP1V5_S0_NB_3GPLL_F


PP1V5_S0_NB_VCCA_HPLL


PP1V5_S0_NB_VCCA_MPLL


=PP1V5_S0_NB_PLL

=PP1V5_S0_NB_VCCAUX=PP2V5_S0_NB_VCCA_3GBG=PP3V3_S0_NB_VCC_HV=PP1V05_S0_NB_VTT

63

63

63

19

63

63

63

63

63

63

63

63

19 63

63 63

19

19

19

63

63

19

63

63

63

63

17

63

16

19

19

20

34

63

63

19

19

19

63

19

63

63

63

17 19

19 19

17

17

14

13

17

17

13

13

19

14

14

14

14

14

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

19

13

13

13

13

13

13

13

13

13

16

19

19

19

19

16

17

14

17

17

14

12

13

19

17

63

16

16

19

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

14

14

14

14

19

19 17

17

17

17

19

16 17

17 17

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PCIe BackwardInterop. Mode

VCC Select

ReversalDMI Lane

High = Reversed

Low = Normal

High = 1.5V

Low = 1.05V

Internal pull-down

Internal pull-down

Internal pull-down

945 External Design Spec says reserved

High = Both active

Low = Only SDVO or PCIe x1

ODTFSB Dynamic

RESERVED

Low = Disabled

High = Enabled

RESERVED

Internal pull-up

RESERVED

00 = Partial Clock Gating Disable01 = XOR Mode Enabled10 = All-Z Mode Enabled11 = Normal Operation

Internal pull-up

Low = Reversed

RESERVED

CPU Strap

RESERVED

PCIE GraphicsHigh = Normal

Low = RESERVED

High = DMIx4

Low = DMIx2

NB_CFG<20>

NB_CFG<19>NB_CFG<9>

NB_CFG<8>NB_CFG<18>

NB_CFG<17>

NB_CFG<6>NB_CFG<16>

NB_CFG<15>NB_CFG<5>

NB_CFG<14>

NB_CFG<13:12>

RESERVED

NB_CFG<3>

NB_CFG<4>

Lane Reversal

PROBABLY NOT NEEDED

PROBABLY NOT NEEDEDDMI x2 Select

Internal pull-up

RESERVED

NB_CFG<7> High = Mobile CPU

NB_CFG<10>

NB_CFG<11>

RESERVED

RESERVED

Internal pull-up

Internal pull-ups

402

5%2.2K1/16WMF-LF

NBCFG_DMI_X2

2

1R2075

5%2.2K1/16WMF-LF402

NBCFG_DYN_ODT_DISABLE

2

1R2085

402

1/16W5%2.2K

NBCFG_VCC_1V5

MF-LF2

1R2058

402MF-LF1/16W5%2.2K

NBCFG_DMI_REVERSE

2

1R2059

NBCFG_SDVO_AND_PCIE

402MF-LF1/16W5%2.2K

2

1R2060

NO STUFF

2.2K5%1/16WMF-LF4022

1R2077

402MF-LF1/16W5%2.2K

NBCFG_PEG_REVERSE

2

1R2079

20 104

A051-6941

NB Config StrapsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

NB_CFG<7>

NB_CFG<9>

NB_CFG<5>

NB_CFG<16>

NB_CFG<20>

NB_CFG<19>

NB_CFG<18>

=PP3V3_S0_NB

=PP3V3_S0_NB

=PP3V3_S0_NB

63

63

63

20

20

20

19

19

19

14

14

14

14

14

14

14

14

14

14

www.vinafix.vn

IO

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IO

IO

IO

IO

IN

IO

DDACK*

SATARBIASNSATARBIASP

SATA_CLKNSATA_CLKP

SATA_2TXPSATA_2TXN

SATA_2RXNSATA_2RXP

SATA_0TXPSATA_0TXNSATA_0RXPSATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNCACZ_BIT_CLK

LAN_TXD2

LAN_TXD0LAN_TXD1

LAN_RXD1LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLKEE_CS

INTVRMENINTRUDER*

RTCRST*

RTCX2RTCX1

THRMTRIP*

STPCLK*

NMISMI*

RCIN*

INTRINIT*

INIT3_3V*IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23LDRQ0*

LAD3LAD2

LAD0LAD1

EE_DOUTEE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDYDDREQ

DD0DD1

DD3DD2

DD5DD4

DD6DD7DD8

DD11

DD9DD10

DD12DD13DD14DD15

DA0DA1DA2

DCS3*DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

IN OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(WEAK INT PU)

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

INTEL HIGH DEFINITION AUDIO

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK

ACZ_RST#

ACZ_SDIN[0-2]

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

AC ’07

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN - LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NONE

INTERNAL 20K PD

INTERNAL 20K PD ONLY ENABLED IN S3COLD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

NOTE: DD<7> HAS INTERNAL 11.5K PD

(HSTROBE)(STOP)

20K PD

20K PD

20K PD

(DSTROBE)

< 2 IN OF R2107 W/O STUBLAYOUT NOTE: R2108 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2107 TO BE< 2 IN OF SB

BOM CONSOLIDATIONNOTE: RISING-EDGE TRIGGERED AT CPU

NOTE: KEYBOARD CONTROLLER RESET CPU

POR IS SMC WILL PUT LAN INT’FNOTE:

INTO RESET STATE TO SAVE PWR.

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTEL CONFIRMS OK TO LEAVE PINS AS NC

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

NOTE: PULLED UP PER INTEL NOTE: R2110=56 IN CV. CHANGED TO 54.9 FORBOM CONSOLIDATION

NOTE: R2108=56 IN CV.

(WEAK INT PD)

(INT PU)

(INT PU)

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

NOSTUFF

1/16WMF-LF

0

5%402

21R2100

NOSTUFF

402

2.2K5%

1/16WMF-LF

21R2101

MF-LF5%

394021/16W

21R21953921R21983921R2197

3921R2196

402

10K5%1/16WMF-LF2

1R2199

BGASB

ICH7-M

OMIT

AH25AF24

AF26

AH22

AF23

AG10AH10

AF18

AE1AF1

AH6AG6AE7AF7

AH2AG2AE3AF3

AB2AB1

AA3

AG23

AH24

AB3

AA5AC3

V7V6U7

T5V4U5

U3

V3

Y6AC4AB5AA6

AG16

W4Y5

AF25

AG21AF22

AG22

AH16

AG24

AG26

Y1Y2W3

W1

AH15AF15

AE15

AF16

AF12AE12AC12AD12AC13AD14AF13AG13

AC15AH14AH13AF14AC14AB13

AE14AB15

AD16AE16

AF17AE17AH17

AG27

R6

T4

T1T3T2R5

U1

AH28AE22

U2100 402

10K5%1/16WMF-LF2

1R2194332K402

1%1/16WMF-LF

2

1

R2105

24.9MF-LF1/16W1%

40221

R2107402MF-LF

1/16W1%54.9

2

1

R2108

MF-LF1/16W

40254.9

1%

21

R2110

A

21 104

051-6941


SB: 1 OF 4

TP_SB_XOR_V7TP_SB_XOR_V6TP_SB_XOR_U7

TP_SB_XOR_Y2TP_SB_XOR_Y1TP_SB_XOR_W1

SB_INTVRMEN

=PP1V05_S0_SB_CPU_IO

CPU_FERR_L

SB_A20GATE

CPU_RCIN_L

SATA_C_D2R_P

IDE_PDDACK_L

SATA_RBIAS_NSATA_RBIAS_P

SB_CLK100M_SATA_NSB_CLK100M_SATA_P

SATA_C_R2D_C_PSATA_C_R2D_C_N

SATA_C_D2R_N

SATA_A_R2D_C_PSATA_A_R2D_C_NSATA_A_D2R_PSATA_A_D2R_N

TP_SB_SATALED_L

SB_ACZ_SDATAOUT

TP_SB_ACZ_SDIN1TP_SB_ACZ_SDIN2

ACZ_SDATAIN<0>

SB_ACZ_SYNCSB_ACZ_BITCLK

SB_SM_INTRUDER_L

SB_RTC_X1

CPU_THERMTRIP_R

CPU_STPCLK_L

CPU_NMICPU_SMI_L

CPU_INTRCPU_INIT_LFWH_INIT_LCPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_LCPU_DPSLP_L

CPU_A20M_L

TP_CPU_CPUSLP_L

SB_ACZ_RST_L

IDE_PDIOR_L

IDE_IRQ14

IDE_PDIOW_L

IDE_PDIORDYIDE_PDDREQ

IDE_PDD<0>IDE_PDD<1>



IDE_PDD<11>


IDE_PDD<12>IDE_PDD<13>IDE_PDD<14>IDE_PDD<15>

IDE_PDA<0>IDE_PDA<1>IDE_PDA<2>

IDE_PDCS3_LIDE_PDCS1_L

ACZ_SYNC SMC_RCIN_L


PM_THRMTRIP_LACZ_SDATAOUT

IDE_PDD<6>

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_GPIO

LPC_AD<0>LPC_AD<1>LPC_AD<2>LPC_AD<3>

TP_SB_DRQ0_LTP_SB_GPIO23

LPC_FRAME_L

SB_RTC_X2

SB_RTC_RST_L

ACZ_BITCLK

ACZ_RST_L

PP3V3_S5_SB_RTC

TP_SB_XOR_U3

TP_SB_XOR_U5TP_SB_XOR_V4TP_SB_XOR_T5

TP_SB_XOR_W3

TP_SB_XOR_V3


63

63

56

56

56

56

56

25

79

49

79

25

48 79

63

63

49

49

49

49

49

79

79

26

24

34

34

45

79

79

79

79

79

48

79

79

57

79

79

45

24

14 45

23

23

47

47

47

47

47

45

45

25

21

7

76

36

36

36

5

5

76

76

76

36

36

36

36

79

5

79

79

26

26

7

7

7

7

7

5

7

7

7

7

7

79

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

36

5 47

21

7 5

36

21

21

5

5

5

5

5

26

26

5

5

24

6

6

6

6

36

36

www.vinafix.vn

IN

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*USBRBIAS

DMI0RXNDMI0RXPDMI0TXNDMI0TXP

DMI2TXNDMI2TXP

DMI3RXN

DMI3TXPDMI3TXNDMI3RXP

USBP0NUSBP0PUSBP1NUSBP1PUSBP2NUSBP2PUSBP3NUSBP3P

USBP4PUSBP5NUSBP5PUSBP6NUSBP6PUSBP7NUSBP7P

USBP4N

OC0*OC1*OC2*OC3*OC4*

OC6*/GPIO30OC5*/GPIO29

SPI_CLKSPI_CS*

SPI_MOSISPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXPDMI2RXN

DMI1TXPDMI1TXN

DMI1RXNDMI1RXP

PERN1PERP1PETN1PETP1






OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*RSVD8RSVD7RSVD6RSVD5

RSVD4

GPIO5/PIRQH*GPIO4/PIRQG*GPIO3/PIRQF*GPIO2/PIRQE*

GPIO17/GNT5*GPIO1/REQ5*GNT4*/GPIO48

C/BE0*C/BE1*

DEVSEL*PERR*

STOP*

PCIRST*PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLKPAR

PLOCK*SERR*

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C/BE2*C/BE3*

GNT0*REQ1*GNT1*REQ2*GNT2*REQ3*GNT3*

PIRQA*PIRQB*PIRQC*PIRQD*

RSVD0RSVD1RSVD2RSVD3

MISC

INT I/F

PCI

(2 OF 6)

IO

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IO

IO

IO

IO

OUT

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

AND PWROK=H

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

BOM NOTE FOR PD ON PCI_GNT3_L:

IR

BT

CF/SD

CAMERA

AIRPORT (MINI-PCIE)

EXTERNAL 2

EXTERNAL 1

EXTERNAL 0

NOTE:

STUFF - A16 SWAP OVERRIDE(STRAPPED TO TOP-BLOCK SWAP MODEIE SB INVERTS A16 FOR ALL CYCLESTARGETING FWH BIOS SPACE)

SB BOOT BIOS SELECTGNT4#GNT5#

TO RSVD[1-9]NOTE: CHANGE SYMBOL

R2210STRAP

11

10

01 STUFF

UNSTUFF

UNSTUFFUNSTUFF

STUFF

UNSTUFFSPI

PCI

LPC (DEFAULT)

NOTE:

LAYOUT NOTE:PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:PLACE R2204 < 1/2 IN FROM SB

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

(INT PD)

(INT PD)

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NOTE: FWH_WP_L NOT USED

R2211

ENABLED ONLY WHEN PCIRST#=0

SB: 2 OF 4

(AKA TP3, INTERNAL 20K PU)

(INT 20K PU)

GNT[0-3]# HAVE INT 20K PU

NO STUFF - DEFAULT

1/16W 402

24.9MF-LF1%

21R2203

10K1/16WMF-LF5%

402

USB_G_OC_PU

2

1R2222

402

22.61%

1/16WMF-LF

21R2204

1/16W5%10KMF-LF4022

1R222310K5%1/16WMF-LF4022

1R2225402MF-LF1/16W10K5%

2

1R2226

10K5%1/16WMF-LF4022

1R2299

OMIT

BGASB

ICH7-M

D2D1

N3N4M2M1L5L4K2K1J3J4H2H1G3G4F2F1

P5P2

P6R2

P1

R27

N27

L27

J27

G27

E27

R28

N28

L28

J28

G28

E28

T24

P25

M25

K25

H25

F25

T25

P26

M26

K26

H26

F26

B3A2C3E5D4D5C4D3

C25D25

AE27AE28

AC27AC28AD24AD25

AA27AA28AB25AB26

W27W28Y25Y26

U27U28V25V26

U2100

SBBGA

ICH7-M

OMIT

F14F15B10

F21AH8AG8AE9

AD9AH4AG4AD5AE5

A13

E13

C17

C16

D7

B19

C26

E11

B5C5B4A3

C9

B18

A9E10

AH20

A7

G7F8F7G8

D8C8A14

F13

D17

D16

E7

F16

A12

C15D12C12B15

C14A15A17E17A18E16

D6E6

F18

B6C7A6A8B9D9E9

F10F11A10

A16

A11D11C11E12G13G15C13B12D14E14

C18E18 U2100

MF-LF1/16W5%10K

4022

1R2200

402MF-LF1/16W5%10K

USB_C_OC_PU

2

1R225010K5%1/16WMF-LF402

USB_E_OC_PU

2

1R2251USB_D_OC_PU

MF-LF1/16W5%10K

4022

1R2255

MF-LF4021/16W5%10K

2

1R2298

MF-LF402 5%

10K1/16W

2

1

R2205

402

10KMF-LF

5%1/16W

NOSTUFF2

1

R2206MF-LF1/16W10K

402 5%

2

1

R2207

VOLTAGE=0V

1/16WMF-LF5%1K

4022

1 R2211

051-6941

10422

A

PCI_PME_FW_L

=PP3V3_S0_SB

SPI_SI

SPI_CE_L

SB_GPIO30

PCI_REQ2_L

BOOT_LPC_SPI_L

PCI_C_BE_L<2>

SPI_SCLK

PCI_STOP_L

PCI_REQ3_L

PCI_REQ1_L

PCI_REQ0_LPCI_AD<1>

PCI_AD<6>

USB_E_OC_L

SB_GPIO29

TP_SB_XOR_AE9TP_SB_XOR_AG8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AH8

TP_SB_XOR_AE5

TP_SB_XOR_AD9TP_SB_XOR_AH4TP_SB_XOR_AG4TP_SB_XOR_AD5

INT_PIRQD_L

USB_H_P

SPI_SO

SPI_ARB

USB_C_OC_LUSB_D_OC_L

USB_B_OC_LUSB_A_OC_L

USB_C_OC_L

=PP3V3_S5_SB_IO PP1V5_S0_SB_VCC1_5_B

SB_GPIO31

PCIE_F_R2D_C_PPCIE_F_R2D_C_NPCIE_F_D2R_PPCIE_F_D2R_N

PCIE_E_R2D_C_PPCIE_E_R2D_C_NPCIE_E_D2R_PPCIE_E_D2R_N

PCIE_D_R2D_C_PPCIE_D_R2D_C_NPCIE_D_D2R_PPCIE_D_D2R_N

PCIE_C_R2D_C_PPCIE_C_R2D_C_NPCIE_C_D2R_PPCIE_C_D2R_N

PCIE_B_R2D_C_PPCIE_B_R2D_C_NPCIE_B_D2R_PPCIE_B_D2R_N

PCIE_A_R2D_C_PPCIE_A_R2D_C_NPCIE_A_D2R_PPCIE_A_D2R_N

DMI_N2S_P<1>DMI_N2S_N<1>

DMI_S2N_N<1>DMI_S2N_P<1>

DMI_N2S_N<2>DMI_N2S_P<2>

SB_CLK100M_DMI_N

SB_GPIO29SB_GPIO30

USB_E_N

USB_H_NUSB_G_PUSB_G_NUSB_F_PUSB_F_NUSB_E_P

USB_D_PUSB_D_NUSB_C_PUSB_C_NUSB_B_PUSB_B_NUSB_A_PUSB_A_N

DMI_N2S_P<3>DMI_S2N_N<3>DMI_S2N_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>DMI_S2N_N<2>

DMI_S2N_P<0>DMI_S2N_N<0>DMI_N2S_P<0>DMI_N2S_N<0>

USB_RBIAS_PN

SB_CLK100M_DMI_P

DMI_IRCOMP_R

INT_PIRQC_LINT_PIRQB_LINT_PIRQA_L

PCI_C_BE_L<3>

PCI_AD<31>PCI_AD<30>PCI_AD<29>PCI_AD<28>PCI_AD<27>PCI_AD<26>PCI_AD<25>PCI_AD<24>PCI_AD<23>PCI_AD<22>PCI_AD<21>PCI_AD<20>PCI_AD<19>PCI_AD<18>PCI_AD<17>PCI_AD<16>PCI_AD<15>PCI_AD<14>PCI_AD<13>PCI_AD<12>PCI_AD<11>PCI_AD<10>PCI_AD<9>PCI_AD<8>PCI_AD<7>

PCI_AD<5>PCI_AD<4>PCI_AD<3>PCI_AD<2>

PCI_AD<0>

PCI_SERR_LPCI_LOCK_L

PCI_PARPCI_CLK_SB

PCI_IRDY_L

PCI_FRAME_L

PCI_TRDY_L

PLT_RST_L

TP_PCI_PME_LPCI_RST_L

PCI_PERR_LPCI_DEVSEL_L

PCI_C_BE_L<1>PCI_C_BE_L<0>

SB_GPIO2SB_GPIO3SB_GPIO4ODD_PWR_EN_L

TP_SB_RSVD9NB_SB_SYNC_L

SB_GPIO31

USB_A_OC_L

USB_E_OC_L

USB_B_OC_L

USB_D_OC_L

=PP3V3_S5_SB_USB

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_GNT2_L

PCI_GNT3_L

TP_PCI_GNT4_L

49

63

52

52

22

47

52

40

40

22

40

52

22

22

22

22

22

25

14

14

22

14

14

40

40

40

40

40

40

22

22

22

22

40

25

47

47

6

26

5

40

47

26

26

26

26

40

40

6

22

26

6

47

47

6

6

6

6

6

63 24

22

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

37

37

37

37

5

5

14

14

14

14

34

22

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

14

14

14

14

14

14

14

14

5

5

34

26

26

26

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

26

26

40

34

26

26

26

26

40

26

26

40

40

26

26

26

36

14

22

6

6

6

6

63

40

www.vinafix.vn

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IO

IO

OUT

OUT

OUT

IN

IN

IO

IN

IN

IO

IN

IN

IN

IN

OUT

IO

IO

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GPGPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3*SLP_S4*SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10GPIO9

GPIO12

GPIO14GPIO13

GPIO24GPIO15

GPIO25GPIO35GPIO38GPIO39

SMBCLKSMBDATALINKALERT*

SMLINK1SMLINK0

RI*

SYS_RST*

SPKRSUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQTHRM*

GPIO7GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

HI = PRESENTLO = NOT PRESENT

SV_SET_UP IS LINDACARD DETECTNOTE:

NOTE:SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’FIN RESET STATE TO SAVE PWR

DEF=GPI

DEF=GPI

DEF=GPI

OD

(INT 20K PU)

NOTE FOR GPIO25:

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLELAYOUT NOTE:

(INT WEAK PD)

NOTE: RESERVED FOR FUTURE

NOT USED

NOTE FOR R2323 (DEF=NOSTUFF)SB WILL DISABLE TCO TIMERSTRAPPING @ PWROK RISING:SYSTEM REBOOT FEATURE

RESERVED FOR MOBILEAZALIA DOCKING INT’F

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

100 21 R2302100 21 R2303100 21 R2305

NOSTUFF

4025%MF-LF1/16W10K2

1

R2306

10K4025%MF-LF1/16W2

1

R2307

4021/16WMF-LF5%

10K2

1

R2308

5%MF-LF1/16W0402

NOSTUFF

2

1

R2309

4025%MF-LF1/16W10K2

1

R2310

1/16WMF-LF5%

NOSTUFF

40210K2

1

R2311

10K1/16WMF-LF5%4022

1

R2313

402

NOSTUFF

01/16WMF-LF5%2

1

R2314

40210K1/16WMF-LF5%2

1

R231640210K1/16WMF-LF5%2

1

R2317

10K4021/16WMF-LF5%2

1

R2318

10K1/16WMF-LF5%4022

1

R2319

4025%MF-LF1/16W10K2

1

R2320

1/16W5%10KSM-LF

5678

4321

RP2300

5%402MF-LF

1/16W

100K21R2399

1/16WMF-LF5%4021K2

1

R2398

5%MF-LF1/16W8.2K4022

1

R2397

MF-LF5%

1/16W10K4022

1

R23968.2K1/16WMF-LF4025%2

1

R2395 OMIT

BGASB

ICH7-M

F20

AD22

C21

AF20

A22

C20A27A19

A25B25

B22C22

F22D23B24

AH21

Y4

A28

AA4

C23

A26

C19

E20

E21AC18AC21

AE20AD20

AE19AH19

AD21

U2AC19

AG18

E23B21

A21

D20R3

AF19

AF21

AH18

AC20AC22

E22R4E19F19

B23

A20

AB18

B2AC1

U2100

402

10K5%1/16WMF-LF2

1R2390

4021/16WMF-LF5%10K

2

1R2388

MF-LF4025%

1K1/16W

NO_REBOOT_MODE

2

1

R2323NOSTUFF

10K1/16WMF-LF4025%2

1

R2326NOSTUFF

5%MF-LF1/16W40210K2

1

R2327

5%

402

8.2K1/16WMF-LF2

1

R2343

SB: 3 OF 4SYNC_DATE=11/16/2005SYNC_MASTER=M38

051-6941

10423

A

SMC_RUNTIME_SCI_LSMC_EXTSMI_L

PM_THRM_L

SB_GPIO26

SMB_ALERT_L

PM_CLKRUN_L

PCIE_WAKE_LINT_SERIRQ

=PP3V3_S5_SB

SMB_DATA

SB_SPKR

PM_BMBUSY_L

PM_STPCPU_L

FWH_MFG_MODE

TP_AZ_DOCK_RST_L

PM_STPPCI_L

PATA_PWR_EN_L

=PP3V3_S5_SB

SATA_C_PWR_EN_L

=PP3V3_S0_SB_GPIO

CRB_SV_DET

SMC_WAKE_SCI_L

SMS_INT_L

PATA_PWR_EN_LSMC_SB_NMI

=PP3V3_S0_SB_GPIO

BIOS_RECFWH_MFG_MODE

=PP3V3_S5_SB

CRB_SV_DET

TP_SB_GPIO38TP_SB_GPIO6

IDE_RESET_L

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB

VR_PWRGD_CK410

TP_AZ_DOCK_EN_L

BIOS_REC

PM_SUS_STAT_LPM_SYSRST_L

PM_RI_L

SMLINK<0>SMLINK<1>

SMB_LINK_ALERT_L

SATA_C_PWR_EN_L

SB_CLK100M_SATA_OE_LTP_SB_GPIO25_DO_NOT_USE

SV_SET_UP

PM_LAN_ENABLE

PM_PWRBTN_L

PM_DPRSLPVR

PM_BATLOW_L

PM_SB_PWROK

PM_SLP_S5_LPM_SLP_S4_LPM_SLP_S3_L

SUS_CLK_SB

SB_CLK14P3M_TIMER

SB_GPIO37

SB_CLK48M_USBCTLR

SB_GPIO21SB_GPIO19

SATA_C_DET_L

SMB_CLK

PM_RSMRST_L

SV_SET_UP

56

56

49

56

49

47

45

49

63

63

63

63

63

63

63

63

48

47

49

79

62

62

49

40

37

47

25

25

23

48

23

25

25

26

25

47

26

23

57

48

47

47

23

47

47

47

5

5

5

23

27

14

33

23

33

23

23

23

21

23

47

47

23

47

21

23

23

23

23

36

23

11

23

26

23

5

5

23

33

5

47

47

14

47

26

47

39

41

6

34

34

36

27

47

5

www.vinafix.vn

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB COREVCC1_5_A

ARXUSB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCCSUS3_3

VCC1_5_A

VCC1_5_A

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDAVCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3VDEPENDING ON VIO OF AZALIA INTERFACEVCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3VNOTE:

VOLTAGE GENERATED INTERNALLYSO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLYSO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOTS3 IF INTERNAL LAN IS USEDNOTE FOR VCCLAN_3_3:

0 0

OMIT

BGAICH7-M

SB

AE21AE18AE13AE11AE8AE4AE2AD23AD19AD15

AD11

AD8AD7AD4AD3

AD1AC11AC9AC5AC2

AB28

AB27

AB24AB21AB19AB16AB14AB11AB6AB4

AA26AA25

AA24

AA1Y28Y27Y24Y3

W26W25W24W6

V28

V27

V24V15V13V2

U26U25U24U17U16U15

U14

U13U12U4

T17T16T15T14T13T12T6

R18

R17R16R15R14R13R12R11R1

P28P27

P24

P17P16P15P14P13P12P4P3

N26N25

N24

AH27AH23AH12AH7

N18

AH3AH1AG25AG20AG17AG14AG11

AG7AG3AG1

N17

AF28AF27AF11AF8AF4AF2

AE25AE24

N16N15

N14

N13N12N11N6N5N2N1M28M27M24

M17

M16M15M14M13M12M5M4M3L26L25

L24

L15L13K28K27K24J26J25J24J5J2

J1

H28H27H24H5H4H3G26G25G24G21

G18

G14G9G6G5G2G1F28F27F12F5

F4

F3E15E8E4E2E1D24D21D18D13

D10

C27C6C2B28B26B20B17B14B11B8

B1

A23A4

U2100

OMIT

BGASB

ICH7-M

C1

K6K5K4K3

G19D22D19C24

E3

N7M7M6L7L6L3L2L1

A24

P7

R7

G20C28

K7

AD2

W5

W7W2V1V5

Y7AA2

AG28

AG15AG12AD18AD13AC16AB20AB12

G16

AA7

G12G11F9D15C10B7B16B13A5

AG19

AH11

B27

U6

AD27AD26AC26AC25

Y23Y22W23

AC24

W22V23V22U23U22T28T27T26T23T22

AC23

R26R25R24R23R22P23P22N23N22M23

AB23

M22L23L22K23K22J23J22H23H22G23

AB22

G22F24F23E26E25E24D28D27D26

AD28

AA23AA22

AB10

AH5AG5AF6AF5AE6AD6

J7J6H7H6A1

AC8AB8

G17F17T7

AC7

AC17AB17

AH9AG9AF9

AF10AE10AD10AC10AB9

AC6AB7

P11M18M11L18L17L16L14

V18

L12

V17V16V14V12V11U18U11T18T11P18

L11

AH26AE26AE23

F6

AD17G10

U2100

SB: 4 OF 4SYNC_DATE=11/16/2005SYNC_MASTER=M38

A

24 104

051-6941

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE


=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3


=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

63

26

63

63

63

63

63

63

63

25

25

63

63

25

63

25

63

63

25

25

63

63

25

25

25

25

24

21

25

25

24

25

24

25

25

25

24

21

25

25

25

25

22

www.vinafix.vn

NC

NC

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCDMIPLL BYPASS

PLACE C2520 NEAR PIN E3 OF SB

PLACEMENT NOTE:PLACE C2503 < 2.54MM OF PIN AD17 OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARYPLACE C2504 < 2.54MM OF PIN F6 OF SBPLACEMENT NOTE:

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)ICH V5REF_SUS BYPASS

(ICH SUSPEND 3.3V PWR)ICH VCCSUS3_3 BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)ICH VCC1_5_A/ARX BYPASS

ICH VCC3_3 BYPASS

PLACE C2509 NEAR PIN B27 OF SBPLACEMENT NOTE:

ICH VCC3_3 BYPASS

(ICH RTC 3.3V PWR)ICH VCCRTC BYPASS

V5, W2, OR W7

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

3.56MM ON PRIMARY NEAR PIN AD2

ICH VCC_PAUX/VCCLAN3_3 BYPASS(ICH LAN I/F BUFFER 3.3V PWR)

PLACEMENT NOTE:PLACE CAPS NEAR PINSAB8 AND AC8 OF SB

ICH USB/VCCSUS3_3 BYPASS(ICH SUSPEND USB 3.3V PWR)

PLACE CAPS NEAR PINSK3 ... N7 OF SB

PLACE C2520 NEAR PIN C1 OF SB

NEAR PINS D28, T28, AD28

PLACEMENT NOTE:

ICH VCC1_5_A/ATX BYPASS

(ICH IO BUFFER 3.3V PWR)

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

ICH VCCSATAPLL BYPASS(ICH SATA PLL 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V_CPU_IO BYPASS(ICH CPU I/O 1.05V PWR)

ICH IDE/VCC3_3 BYPASS


(ICH PCI I/O 3.3V PWR)

A24 ... G19 AND P7 OF SB

DISTRIBUTE IN PCI SECTION OF SBNEAR PINS A5 ... G16

(ICH IO BUFFER 3.3V PWR)

3.56MM ON PRIMARY NEAR PIN AG9

3.56MM ON PRIMARY NEAR PIN AG5

PLACEMENT NOTE:

PLACEHOLDERFOR 270UF PLACE CAPS NEAR PINS

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE:

PLACEMENT NOTE:

SB: 4 OF 4


ICH V5REF BYPASS

PLACEMENT NOTE:

ICH CORE/VCC1_05 BYPASS(ICH CORE 1.05V PWR)

PLACEMENT NOTE:PLACE CAP UNDER SB NEAR PINS V1,

3.56MM ON PRIMARY NEAR PIN U6

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

(ICH SUSPEND 3.3V PWR)ICH VCCSUS3_3 BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH VCC1_5A BYPASS(ICH LOGIC&IO 1.5V PWR)

(ICH USB CORE 1.5V PWR)

3.56MM ON PRIMARY NEAR PINS A1 ... J7 PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AH11 PLACE < 2.54MM OF SB ON SECONDARY ORPLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY ORPLACEMENT NOTE:

(ICH IDE I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH DMI PLL 1.5V PWR)

(ICH USB PLL 1.5V PWR)ICH VCCUSBPLL BYPASS

ON SECONDARY SIDE OR 3.56MM ON PRIMARYPLACE C2500 & C2505-07 < 2.54MM OF SB

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

(ICH INTEL HDA CORE 3.3V PWR)ICH VCC3_3/VCCHDA BYPASS

PLACE CAPS AT EDGE OF SBPLACEMENT NOTE:


PLACE < 2.54MM OF SB ON

ICH VCCA3GP(VCC1_5_B BYPASS(ICH IO,LOGIC 1.5V PWR)

20%220UFPOLY2.5VSMB2

2

1C2500

X5R16V10%0.1UF

4022

1 C2510

0

402

0.1UF10%16VX5R2

1 C2512

0

15%1/10W

MF-LF603

21R2500

4.7UF20%6.3VCERM603

2

1C25240.1UF10%16VX5R402

2

1 C2522

BAT54DWSOT-363

5

6

1D2502

BAT54DWSOT-363

2

3

4D2502

1206

0.28-OHM21

L2507

0.1UF

402

10%16VX5R2

1 C2503

0

X5R16V10%0.1UF

4022

1 C2504

0

5%MF-LF1/16W402

10

21

R2501

100-OHM-EMISM-3

21

L2500

0

0.1UF10%16VX5R402

2

1 C2505X5R16V10%0.1UF

4022

1 C25060.1UF16V10%X5R402

2

1 C2507

0.01UF10%16VCERM402

2

1C2501

603

10UF20%6.3VX5R2

1C2508

0

10%16VX5R402

0.1UF2

1C2509

0

X5R40216V10%0.1UF

2

1C2511

0

0.1UF

402X5R16V10%

2

1 C2517

0

0.1UF10%16VX5R402

2

1 C2513

0

0

4026.3VCERM10%1UF

2

1C2514

0

0.1UF10%16VX5R402

2

1C2520

402X5R16V10%0.1UF

2

1C2515

0

0

CASE-C2POLY20%2.5V330UF

2

1C25165%

1/16W402MF-LF100

2

1

R2502

1UF10%6.3VCERM402

2

1 C2502

402

0.1UF10%16VX5R2

1C2518

0

X5R16V10%0.1UF

4022

1C2519

0

0.1UF10%16V402X5R2

1C2521

0

X5R16V10%0.1UF

4022

1C2523

0

0.1UFX5R16V10%

4022

1C2525

0

X5R16V10%0.1UF

4022

1C2526X5R16V10%0.1UF

4022

1 C2527X5R16V10%0.1UF

4022

1C2528

402

0.1UF10%16VX5R2

1 C2529

0

402

0.1UF10%16VX5R2

1C2530

402

0.1UF10%16VX5R2

1C2534

0

402

0.1UF10%16VX5R2

1 C2531

402

0.1UF10%16VX5R2

1 C2532

0

402

0.1UF10%16VX5R2

1C2533

051-6941

10425

A

VOLTAGE=1.5VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ATX

=PPVCORE_S0_SB

=PP3V3_S0_SB_3V3_1V5_VCCHDA



MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5VPP1V5_S0_SB_VCCDMIPLLPP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

=PP3V3_S0_SB_VCC3_3_IDE

=PP1V5_S0_SB_VCC1_5_A_USB_CORE


=PP1V5_S0_SB


=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S5_SB_VCCSUS3_3_USB


=PP3V3_S0_SB_VCCLAN3_3

PP3V3_S5_SB_RTC

=PP5V_S5_SB

=PP3V3_S0_SB

=PP3V3_S5_SB

=PP5V_S0_SB

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MMVOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REFVOLTAGE=5V

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM

63

63

63

63

63

26

24

63

63

63

63

24

63

63

63

25

63

25

25

63

63

25

63

63

63

63

24

63

63

22

25

24

24

24

21

24

24

24

24

24

25

24

24

24

24

24

24

24

24

24

21

63

22

23

63

24

24

www.vinafix.vn

IO

IO

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

OUT

OUT IN

IN

OUT

IN OUT

IN

SYM_1

NCNC

IN

OUT

OUT

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Platform Reset Connections

but may change after characterization.Initial resistor values are based on CRB,

NC NC

This part is never stuffed,

LIO represents X loads (2?)

Buffered

Linda Card represents 3 loads

100-ohm on NB page

1G00 used as small & cheap inverter

to solder a reset button.on the board to short orit provides a set of pads

SB RTC Crystal Circuit

RTC Battery Connector

NC

NC

518S0226

Unbuffered

Silk: "SYS RST"

NCNC

NOTE: R2607 and D2600 form the double-fault protection for RTC battery.

MF-LF

5%

402

1/16W

20K21

R2600

0.1UF

402CERM10V20%

2

1C2611

402CERM6.3V10%1UF

2

1 C2605

100K

MF-LF402

5%1/16W

OMIT

2

1R2698

1M

402MF-LF1/16W5%

2

1R2606

10K

MF-LF402

5%1/16W

2

1R2697

402

5%

MF-LF1/16W

1K12

R2607

12pF

CERM402

5%50V

21

C2608

12pF

50V5%

402CERM

21

C2609SM-2

CRITICAL

32.768K

31

42

Y2600

0

402MF-LF1/16W5%

21

R2610

10M

402MF-LF1/16W

5%

2

1R2609

CERM

0.1UF20%10V

4022

1 C2680 100K5%1/16WMF-LF4022

1R2680 402

0

MF-LF1/16W5%

21

R2681

100

402MF-LF1/16W5%

21

R2683

0

1/16W5%

MF-LF402

21

R2684

0

402MF-LF1/16W5%

21

R2685

0

5%1/16WMF-LF402

21

R2687

0

402MF-LF1/16W5%

21

R2682

CRITICAL

F-RT-SM88460-0201

2

1

4

3

J2600

402

ITP

5%1/16WMF-LF

1K21

R2696

MC74VHC1G00SC70-5

5

4

1

2

3

U2603

MC74VHC1G08SC70

5

4

1

2

3

U2680

SC70MC74VHC1G08 5

4

1

2

3

U2601

BAT54DWSOT-363

25

3

6

4

1

D2600

402MF-LF1/16W5%1.8K

2

1R26110.1UF

402CERM10V20%

2

1C2607

402MF-LF1/16W

5%10K

2

1R261210K5%1/16WMF-LF4022

1R2622

8.2K21R26238.2K21R26248.2K21R26258.2K21R26268.2K21R26278.2K21R2628

8.2K21R26298.2K21R2630

8.2K21R26318.2K21R2632

8.2K21R26338.2K21R2634

8.2K21R26368.2K21R2637

8.2K21R26388.2K21R26398.2K21R2640

8.2K21R26418.2K21R2642

4026.3V10%CERM

1UF2

1 C2610


26

051-6941 A

104

SB Misc

SB_RTC_X2

SB_RTC_X1_R

PPVBATT_G3C_RTCVOLTAGE=3.3V

SB_RTC_RST_L

CK410_PD_VTT_PWRGD_L

VR_PWRGD_CK410

=PP3V3_S5_SB_PM

NB_RST_IN_L

PEG_RESET_L

SMC_LRESET_L

DEBUG_RST_L

SB_RTC_X1 LIO_PLT_RESET_L

SB_SM_INTRUDER_L

XDP_DBRESET_LMAKE_BASE=TRUEPM_SYSRST_L

=PP3V3_S0_SB_PM

VR_PWRGD_CK410_LMAKE_BASE=TRUE

=PP3V3_S0_RSTBUF

PM_SB_PWROKALL_SYS_PWRGD

VR_PWRGOOD_DELAY

=PP3V3_S0_SB_PM

PPVBATT_G3C_RTC_RVOLTAGE=3.3V

=PP3V42_G3H_SB_RTC

PP3V3_S5_SB_RTC=PP3V3_S0_SB_PCI

PCI_FRAME_LPCI_IRDY_LPCI_TRDY_LPCI_STOP_LPCI_SERR_LPCI_DEVSEL_LPCI_PERR_LPCI_LOCK_L

PCI_REQ0_LPCI_REQ1_LPCI_REQ2_L

INT_PIRQA_L

PCI_REQ3_L

INT_PIRQC_LINT_PIRQB_L

INT_PIRQD_L

SB_GPIO3SB_GPIO2

SB_GPIO4

MAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

MAKE_BASE=TRUEPLT_RST_L

ENET_RST_L

TPM_LRESET_L

PLT_RST_BUF_L

63

47

25

33

23

49

45

23

63

62

57

63

24

40

40

40

40

40

40

40

40

40

21

21

23

11

14

65

47

5

21 5

21

5

26

57

63

23

47

14

26

63

21

63

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

37

56

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SO-DIMM "B"

(Write: 0xA0 Read: 0xA1)

SMC

SO-DIMM "A"

SMC

U2 - Keyboard Controller

U1 - Trackpad Controller

Trackpad I2C Connections:

M35 - TMP105

(Write: 0x70 Read: 0x71)


Left I/O SMBus Connections:


(Address determined by ARP)ExpressCard Slot

Left I/O Board

(See Table)

SMC "0" SMBus Connections

(MASTER)

SMC "A" SMBus Connections (MASTER)U5800

SMC "Battery A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

SMC "Battery B" SMBus Connections

J8250

U5800(MASTER)

Ambient Thermal

Right-Side TempADT7461: U6150

GPU Temp

TMP105: J4930

U5800

J2800

Clock Chip(Write: 0xD2 Read: 0xD3)

CY28445-5: U3301U2100(MASTER)

MAX6695: U6100



J4900


Left ALS - TSL2561(Write: 0x92 Read: 0x93)

SMC

(Write: 0x90 Read: 0x91)LIO - TMP105

(MASTER)

SMCU5800

SMC "B" SMBus Connections

(See Table)J5400

ADT7461: U1001CPU Temp


(See Table)Left Temp - TMP105


ICH7-M

Left I/O BoardLeft I/O SMBus Connections:

J5500(See Table)

(Write: 0xA4 Read: 0xA5)J2900

TrackpadJ4900

(MASTER)U5800

Battery


Right Temp - TMP105

Top-Case SMBus Connections: Top-Case

ICH7-M SMBus Connections


MF-LF402

1/16W5%

4.7K

2

1R2700

MF-LF402

5%1/16W

4.7K

2

1R2701

1/16W5%

402MF-LF

4.7K

2

1R27801/16W5%

402MF-LF

4.7K

2

1R2781

100K5%1/16W402MF-LF

2

1R2791100K1/16W

5%

402MF-LF

2

1R2790

402MF-LF1/16W5%4.7K

2

1R27615%

1/16W402

MF-LF

4.7K

2

1R2760

1/16WMF-LF402

5%4.7K

2

1R27711/16W

402MF-LF

5%4.7K

2

1R2770

402MF-LF1/16W5%4.7K

2

1R2751

MF-LF402

5%1/16W

4.7K

2

1R2750

M1 SMBus ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

10427

A051-6941

=SMBUS_BATT_SDA

=I2C_TRACKPAD_SDA

=I2C_TRACKPAD_SCL

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=SMBUS_LIO_SB_SCL

=SMBUS_LIO_SB_SDA

SMB_THRM_DATA

=SMBUS_LIO_SMC_SCL

=SMBUS_TOPCASE_SCL

SMB_THRM_CLK

=SMBUS_LIO_SMC_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMBUS_TOPCASE_SDA

SMB_BSB_DATA

=SMBUS_GPUTHMSNS_SDA

SMB_CLK

SMB_DATA

=I2C_SODIMMA_SCL

SMB_CK410_DATA

SMB_CK410_CLK

=SMBUS_ATS_SDA

SMB_0_S0_DATA

SMB_0_S0_CLK

=SMBUS_GPUTHMSNS_SCL

=SMBUS_RSTHMSNS_SDA

=SMBUS_RSTHMSNS_SCL

SMB_BSB_CLK

SMB_BSA_DATA

SMB_BSA_CLK =SMBUS_BATT_SCL

SMBUS_SMC_BSB_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_BSB_SCL

=PP3V3_S0_SMBUS_SMC_BSB

=I2C_SODIMMA_SDA

=SMBUS_ATS_SCL

SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_B_S0

MAKE_BASE=TRUESMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDAMAKE_BASE=TRUE

=PP3V42_G3H_SMBUS_SMC_BSA

MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUESMBUS_SB_SDA

MAKE_BASE=TRUESMBUS_SB_SCL

=PP3V3_S0_SMBUS_SB

64

45

45

45

45

43

64

43

5

43

43

29

29

5

5

10

5

43

10

5

47

47

47

47

43

47

50

23

23

28

33

33

5

47

47

50

50

50

47

47

5

63

28

5

63

63

63

63

63

www.vinafix.vn

VSS2

DQS0*

DQ5

VSS0DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0VSS58

DQ63

DQ62VSS56

DQS7DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*CK1

VSS46

DQ53DQ52

VSS44

VSS42

DQS5DQS5*

VSS39DQ45

DQ44

VSS37DQ39

DQ38

VSS35DM4

VSS34

DQ37DQ36

VSS32NC3

VDD11

NC/A13ODT0

VDD9

S0*

BA1

VDD7A0

A2A4

VDD5

A6A7

A11

VDD3NC/A14

NC/A15

NC/CKE1

VSS30DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0VSS19

DQ21

DQ20VSS17

VSS15

DQ15DQ14

VSS13

CK0*CK0

VSS11

DQ13

DQ12

DQ47DQ46

DQ61

DQ55

DM6

VDDSPD

SCLSDA

VSS57

DQ59DQ58

VSS55DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47NC_TEST

VSS45

DQ49DQ48

VSS43

VSS41

DM5VSS40

DQ41

VSS38

DQ35

VSS36

DQS4DQS4*

VSS33

DQ33DQ32

VSS31

VDD10

NC/S1*CAS*

VDD8

WE*BA0

A10/AP

VDD6A1

A3A5

VDD4

A8A9

A12

VDD2BA2

NC2

VDD0CKE0

DQ27

DQ26

VSS27NC1

DM3

DQ25

DQ24

VSS23DQ19

DQ18VSS21

DQS2

DQS2*VSS18

DQ17

DQ16VSS16

VSS14

DQ11DQ10

VSS12

DQS1DQS1*

DQ9DQ8

VSS8

DQ3DQ2

VSS6DQS0

VREF

DQ34

DQ40

DQ42DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

"Lower" (surface-mount) slot

by another page.The reference voltage must be providedNOTE: This page does not supply VREF.

Page Notes

- =I2C_SODIMMA_SDA- =I2C_SODIMMA_SCL

NC

Power aliases required by this page:

(NONE)BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S3_MEM- =PPSPD_S0_MEM (2.5V - 3.3V)

516S0382

NC

NC

NC

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)DDR2 Bypass Caps

NC0.1uF

CERM402

20%10V2

1 C28130.1uF

CERM402

20%10V2

1 C2812

10UF

X5R603

20%6.3V2

1 C2809

0.1uF

CERM402

20%10V2

1 C2811

10UF

X5R603

20%6.3V2

1 C2808

0.1uF

CERM402

20%10V2

1 C2810

0.1uF

CERM402

20%10V2

1 C28190.1uF

CERM402

20%10V2

1 C2818

0.1uF

CERM402

20%10V2

1 C28170.1uF

CERM402

20%10V2

1 C2816

0.1uF

CERM402

20%10V2

1 C28210.1uF

CERM402

20%10V2

1 C2820

0.1uF

CERM402

20%10V2

1 C28150.1uF

CERM402

20%10V2

1 C2814

0.1uF

CERM402

20%10V2

1 C2800

DDR2-SODIMM-DUAL

F-RT-SM

CRITICAL

109A

24A21A

18A15A

12A

196A193A

190A187A

184A183A

178A177A

172A

9A

171A

168A165A

162A161A

156A155A

150A149A

145A144A

139A138A

133A132A

128A127A

122A121A

78A

8A

77A

72A71A

66A65A

60A59A

54A53A

3A

48A47A

42A41A

40A39A

34A33A

28A27A

2A1A

199A

112A111A

104A103A

96A95A

88A87A

82A

118A117A

81A

195A197A

200A198A

110A108A

114A

163A

120A

83A

69A

50A

115A

119A

80A

84A86A

116A

204

203

202

201

186A188A

167A169A

146A148A

129A131A

68A70A

49A51A

29A31A

11A13A

25A23A

16A14A

194A192A

182A180A

6A

191A189A

181A179A

176A174A

160A158A

175A173A

4A

159A157A

154A152A

142A140A

153A151A

143A141A

19A

136A134A

126A124A

137A135A

125A123A

76A74A

17A

64A62A

75A73A

63A61A

58A56A

46A44A

7A

57A55A

45A43A

38A36A

22A20A

37A35A

5A

185A

170A

147A

130A

67A

52A

26A

10A

79A

166A164A

32A30A

113A

85A

106A107A

91A93A

92A94A

97A 98A99A 100A

101A

89A 90A

105A

102A

J28002.2uF

20%

603CERM16.3V 2

1C2801


DDR2 SO-DIMM Connector A

051-6941 A

10428

MEM_VREF

MEM_A_DM<0>

MEM_CLK_P<1>

=PP1V8_S3_MEM

=PPSPD_S0_MEM

=PP1V8_S3_MEM

=PP1V8_S3_MEM

MEM_A_DQ<2>


MEM_A_DQS_N<3>

MEM_A_DQ<23>

MEM_A_CAS_LMEM_CS_L<1>

MEM_ODT<0>

MEM_A_RAS_L

MEM_A_A<0>

MEM_A_A<11>

MEM_A_DQ<31>


MEM_A_DQ<17>

MEM_A_DM<2>

MEM_A_DQ<22>

MEM_A_DQ<1>

MEM_A_BS<1>

MEM_CKE<1>

MEM_A_DQ<14>

MEM_A_DQ<11>


MEM_A_DQS_N<0>MEM_A_DQS_P<0>

MEM_A_DQ<6>




MEM_A_DQ<25>

MEM_A_DM<3>


MEM_CKE<0>

MEM_A_BS<2>

MEM_A_A<12>MEM_A_A<9>MEM_A_A<8>

MEM_A_A<5>MEM_A_A<3>MEM_A_A<1>

MEM_A_A<10>MEM_A_BS<0>MEM_A_WE_L

MEM_A_DQ<7>

MEM_ODT<1>




MEM_A_DM<7>

MEM_A_DQ<58>




MEM_A_DM<6>


=I2C_SODIMMA_SDA=I2C_SODIMMA_SCL

MEM_A_DQ<8>

MEM_CLK_P<0>MEM_CLK_N<0>

MEM_A_DQ<0>

MEM_A_DQ<21>




MEM_CS_L<0>

MEM_A_A<13>


MEM_A_DM<4>



MEM_CLK_N<1>

MEM_A_DM<5>

MEM_A_DQ<47>

MEM_A_DQ<54>



DIMM_OVERTEMP_L

MEM_A_DQ<44>

MEM_A_DQS_P<3>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<3>


MEM_A_DM<1>

MEM_A_DQ<10>

MEM_A_DQS_P<1>MEM_A_DQS_N<1>

MEM_A_DQ<59>

MEM_A_DQ<61>


MEM_A_DQ<55>


MEM_A_DQ<62>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQS_N<7>

MEM_A_DQ<56>

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15

15

15

15

27

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15

6

6

15

15

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15

14

15

15

15

15

15

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15

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15

15

15

15

15

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www.vinafix.vn

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0*

DQS0VSS6

DQ2DQ3

DQ8DQ9

VSS10

DQS1*DQS1

DQ10DQ11

VSS14

VSS16DQ16

DQ17

VSS18DQS2*

DQS2

VSS21DQ18

DQ19VSS23

DQ24

DQ25VSS25

DM3

NC1VSS27

DQ26

DQ27VSS29

CKE0VDD0

NC2

BA2VDD2

A12

A9A8

VDD4

A5A3

A1VDD6

A10/AP

BA0WE*

VDD8

CAS*NC/S1*

VDD10

NC/ODT1VSS31

DQ32DQ33

VSS33

DQS4*DQS4

VSS36

DQ35

VSS38

DQ41

VSS40DM5

VSS41

VSS43

DQ48DQ49

VSS45

NC_TESTVSS47

DQS6*

VSS49

DQ50

VSS51

DQ56

VSS53

DM7VSS55

DQ58DQ59

VSS57

SDASCL

VDDSPD

DM6

DQ55

DQ61

DQ46DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0CK0*

VSS13

DQ14DQ15

VSS15

VSS17DQ20

DQ21

VSS19NC0

DM2

VSS22DQ22

DQ23VSS24

DQ28

DQ29VSS26

DQS3*

DQS3VSS28

DQ30

DQ31VSS30

NC/CKE1VDD1

NC/A15

NC/A14VDD3

A11

A7A6

VDD5

A4A2

A0VDD7

BA1

RAS*S0*

VDD9

ODT0NC/A13

VDD11

NC3VSS32

DQ36DQ37

VSS34

DM4VSS35

DQ38

DQ39VSS37

DQ44

DQ45VSS39

DQS5*DQS5

VSS42

VSS44

DQ52DQ53

VSS46

CK1CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54

DQS7*DQS7

VSS56DQ62

DQ63

VSS58SA0

SA1

DQ5

VSS2

VREF

VSS4

VSS8

VSS0DQ4

VSS5

DQ6

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

"Upper" (thru-hole) slot

516-0140

NOTE: This page does not supply VREF.The reference voltage must be providedby another page.

- =I2C_SODIMMB_SDA- =I2C_SODIMMB_SCL

Page Notes

NC


(NONE)

Power aliases required by this page:- =PP1V8_S3_MEM- =PPSPD_S0_MEM (2.5V - 3.3V)

BOM options provided by this page:

NC

NC

NC

NC

NC

DDR2 Bypass Caps(For return current)

Resistor prevents pwr-gnd short

ADDR=0xA4(WR)/0xA5(RD)

10V0.1uF

CERM402

20%2

1 C291310V0.1uF

CERM402

20%2

1 C2912

6.3V20%

603X5R

10UF2

1 C2909

10V0.1uF

CERM402

20%2

1 C2911

6.3V20%

603X5R

10UF2

1 C2908

10V0.1uF

CERM402

20%2

1 C2910

10V0.1uF

CERM402

20%2

1 C291910V0.1uF

CERM402

20%2

1 C2918

0.1uF

CERM402

20%10V2

1 C291710V0.1uF

CERM402

20%2

1 C2916

10V0.1uF

CERM402

20%2

1 C29210.1uF10VCERM402

20%2

1 C2920

10V0.1uF

CERM402

20%2

1 C291510V0.1uF

CERM402

20%2

1 C2914

402MF-LF1/16W5%10K

2

1R2900

CRITICAL

DDR2-SODIMM-DUAL

F-RT-TH1

109B

24B

21B

18B

15B

12B

196B

193B

190B

187B

184B183B

178B177B

172B

9B

171B

168B

165B

162B161B

156B155B

150B149B

145B

144B

139B

138B

133B

132B

128B127B

122B121B

78B

8B

77B

72B71B

66B65B

60B59B

54B53B

3B

48B47B

42B41B

40B39B

34B33B

28B27B

2B1B

199B

112B111B

104B103B

96B95B

88B87B

82B

118B117B

81B

195B

197B

200B

198B

110B

108B

114B

163B

120B

83B

69B

50B

115B

119B

80B

84B

86B

116B

202

201

186B

188B

167B

169B

146B

148B

129B

131B

68B

70B

49B

51B

29B

31B

11B

13B

25B

23B

16B

14B

194B

192B

182B

180B

6B

191B

189B

181B

179B

176B

174B

160B

158B

175B

173B

4B

159B

157B

154B

152B

142B

140B

153B

151B

143B

141B

19B

136B

134B

126B

124B

137B

135B

125B

123B

76B

74B

17B

64B

62B

75B

73B

63B

61B

58B

56B

46B

44B

7B

57B

55B

45B

43B

38B

36B

22B

20B

37B

35B

5B

185B

170B

147B

130B

67B

52B

26B

10B

79B

166B

164B

32B

30B

113B

85B

106B

107B

91B

93B

92B

94B

97B 98B

99B 100B

101B

89B 90B

105B

102B

J29000.1uF

CERM402

20%10V2

1 C29002.2uF

20%

603CERM16.3V 2

1C2901

10429

051-6941 A


DDR2 SO-DIMM Connector B

MEM_VREF

=PPSPD_S0_MEM

SODIMM_A_SA1

MEM_B_DQ<50>


=I2C_SODIMMB_SDA=I2C_SODIMMB_SCL

=PPSPD_S0_MEM

MEM_B_DQ<15>

MEM_B_DM<1>MEM_B_DQ<14>

MEM_B_DQS_N<0>

MEM_B_DQ<21>

MEM_B_DQS_N<2>MEM_B_DQS_P<2>

MEM_B_DQ<23>


MEM_B_DQ<25>

MEM_CKE<2>

MEM_B_BS<2>

MEM_B_A<12>MEM_B_A<9>MEM_B_A<8>


MEM_B_A<10>MEM_B_BS<0>MEM_B_WE_L

MEM_B_CAS_LMEM_CS_L<3>

MEM_ODT<3>





MEM_B_DM<5>

MEM_B_DQ<43>


MEM_B_DM<6>


MEM_B_DQ<42>

MEM_B_RAS_LMEM_CS_L<2>

MEM_ODT<2>MEM_B_A<13>

MEM_B_DQ<37>

MEM_B_DM<4>




MEM_B_DQ<46>

MEM_CLK_N<2>

MEM_B_DQ<55>

MEM_B_DQ<32>

MEM_B_DQ<12>

MEM_B_DM<2>


MEM_B_DQ<28>




MEM_B_BS<1>


MEM_B_DQ<19>

MEM_B_DM<3>

MEM_B_A<14>

MEM_CKE<3>

MEM_B_A<5>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQ<61> MEM_B_DQ<57>MEM_B_DQ<60> MEM_B_DQ<56>

MEM_B_DM<7>

MEM_CLK_P<2>

MEM_B_DQ<62>MEM_B_DQ<63>MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<8>

MEM_B_DQS_P<0>

DIMM_OVERTEMP_L




MEM_B_DM<0>

MEM_CLK_P<3>

MEM_B_DQ<4>


MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<26>


MEM_B_A<15>

MEM_B_DQ<27>

=PP1V8_S3_MEM

MEM_B_DQ<20>

=PP1V8_S3_MEM

=PP1V8_S3_MEM

MEM_B_DQ<0>

MEM_CLK_N<3>

MEM_B_DQ<1>

63

63

63 63

63

32

29

29

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

48

29 29

29

28

28

15

15

15

27

27

28

15

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

14

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

14

14

15

15

15

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

6

14

15

15

15

15

15

15

15 15

15 15

15

14

15

15

15

15

15

15

28

15

15

15

15

15

15

15

14

15

15

15

15

15

15

15

15

15

6

15

28

15

28

28

15

14

15

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

One cap for each side of every RPAK, one cap for every two discrete resistorsEnsure CS_L and ODT resistors are close to SO-DIMM connector

402

10V20%

CERM

0.1uF2

1 C3051

0.1uF

402CERM10V20%

2

1 C30530.1uF

CERM10V20%

4022

1 C3052

CERM

0.1uF20%10V

4022

1 C3050

20%10VCERM402

0.1uF2

1 C3055

0.1uF

402CERM10V20%

2

1 C3057

20%10VCERM402

0.1uF2

1 C30590.1uF20%

CERM402

10V2

1 C3058

402CERM10V20%0.1uF

2

1 C3056

0.1uF

402CERM10V20%

2

1 C3054

0

1

2

3

5

4

6

7

8

9

10

11

12

13

0

2

1

29 15

29 15

29 15

29 15

29 15

SM-LF1/16W5%56 63RP305856

SM-LF1/16W5%54RP3058

56SM-LF1/16W5%

72RP3032 5% SM-LF1/16W56 81RP3032

1/16W SM-LF5%56 72RP3052

565% 1/16W SM-LF

81RP305056

5% 1/16W SM-LF81RP3054

1/16W5% SM-LF56 81RP3056 5% 1/16W SM-LF56 81RP3005 SM-LF1/16W5%56 54RP3056

SM-LF1/16W5%56 72RP3058 SM-LF1/16W5%56 81RP3058 SM-LF1/16W5%56 54RP3054 SM-LF1/16W5%56 63RP3054 SM-LF1/16W5%56 81RP3052 SM-LF1/16W5%56 72RP3054 SM-LF1/16W5%56 63RP3052 SM-LF1/16W5%56 54RP3050 SM-LF1/16W5%56 63RP3050 SM-LF1/16W5%56 72RP3005

SM-LF1/16W5%56 72RP3050

SM-LF1/16W5%56 63RP3056

1/16W5% SM-LF56 72RP3056

SM-LF1/16W5%56 54RP3052

1/16W5% MF-LF 40256 21R3000

402MF-LF5% 1/16W56 21R3002 5% MF-LF 4021/16W56 21R3001

5% MF-LF 4021/16W56 21R3003

565% 1/16W SM-LF

54RP3005

56SM-LF1/16W5%

54RP3030

565% 1/16W SM-LF

63RP3030

56SM-LF1/16W5%

81RP3010

56SM-LF1/16W5%

72RP3010

5% 1/16W SM-LF56 72RP3034

5% 1/16W SM-LF56 81RP3030 5% 1/16W SM-LF56 63RP3032 5% 1/16W56

SM-LF72RP3030

5% 1/16W56

SM-LF63RP3005

5% 1/16W56

SM-LF81RP3034 5% 1/16W SM-LF

56 54RP3034

5% 1/16W56

SM-LF54RP3032

SM-LF5% 1/16W56 81RP3036

5% 1/16W56

SM-LF63RP3034

5% 1/16W56

SM-LF63RP3036

56SM-LF1/16W5%

54RP3036

56SM-LF1/16W5%

72RP3036

56SM-LF1/16W5%

54RP301056

5% 1/16W SM-LF63RP3010

402MF-LF5% 1/16W56 21R301056

1/16W5% MF-LF 40221R3011

402MF-LF5% 1/16W56 21R3012

402MF-LF1/16W56

5%21R3013

0

1

0

1

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

29 28 14

29 28 14

28 15

28 15

28 15

28 15

28 15

2

3

2

3

20%10VCERM402

0.1uF2

1 C30390.1uF20%

CERM402

10V2

1 C3038

20%10VCERM402

0.1uF2

1 C3033

402

20%10VCERM

0.1uF2

1 C3032

402CERM10V20%0.1uF

2

1 C3031

CERM

0.1uF20%10V

4022

1 C3030

0.1uF10V20%

402CERM2

1 C30110.1uF

402

20%10VCERM2

1 C3010

20%

CERM402

0.1uF10V2

1 C30070.1uF

402CERM10V20%

2

1 C3005

20%10VCERM402

0.1uF2

1 C3002

402CERM10V20%0.1uF

2

1 C3000

0.1uF

402CERM10V20%

2

1 C3037

402CERM10V20%0.1uF

2

1 C3036

20%10VCERM402

0.1uF2

1 C30350.1uF

402CERM10V20%

2

1 C3034

0

1

2

3

29 28 14

30 104

A051-6941

Memory Active TerminationSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MEM_CKE<3..0>

MEM_A_BS<2..0>

MEM_B_A<13..0>

MEM_ODT<3..0>

MEM_CS_L<3..0>

MEM_A_A<13..0>

MEM_B_BS<2..0>

=PP0V9_S0_MEM_TERM

MEM_B_RAS_LMEM_B_CAS_L

MEM_A_RAS_LMEM_A_CAS_LMEM_A_WE_L

MEM_B_WE_L

63

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VREF

VTT

GND

VTT_IN

ENVTTS

VDDQ VCC

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

disable MEMVTT in sleep.MEMVTT_EN can be used toIf power inputs are not S0,

DDR2 Vtt Regulator

leave 1.8V powered in S3.Okay to turn off 5V and

Page Notes

- =PP0V9_S0_MEMVTT_LDO- =PP1V8_S0_MEMVTT- =PP5V_S0_MEMVTT




(NONE)

(NONE)

6.3V20%

X5R603

10uF2

1C3101

CRITICAL

MSOP-8BD3533FVM

3

7

8

4

5 6

1

2

U3100

MEMVTT_EN_PU

1K

402MF-LF1/16W5%

2

1R3100

6.3V

SMC-LFPOLY

20%150UFC3105

603X5R

20%10uF6.3V2

1 C3102

CERM1

20%6.3V

2.2uF

6032

1C3104

220

5%1/16WMF-LF402

2 1

R3104

10%16VX5R

0.1uF

4022

1 C3103

6.3V10%1uF

CERM402

2

1 C3100


Memory Vtt Supply

051-6941 A

10431

=PP0V9_S0_MEMVTT_LDO

VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP1V8_S0_MEMVTT_VDDQ

=PP5V_S0_MEMVTT

MEMVTT_VREF

MEMVTT_EN

=PP1V8_S0_MEMVTT

63

63

63

www.vinafix.vn

V+

V-

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CRITICAL

MAX4236EUTTSOT23-6-LF

2

6

5

1

4

3

U3200

20%0.1UF

40210V

CERM 2

1C3200

CERM402

220pF25V5%

2

1C320510K1/16W

1%

402MF-LF

2

1R3206

10K

MF-LF402

1%1/16W

2

1R3205

100K

MEMVREF_S3

MF-LF402

5%1/16W

2

1R3202

5%1/16WMF-LF402

0

MEMVREF_S0

2 1

R3203

32 104

A051-6941

DDR2 VRefSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.15 mmVOLTAGE=0.9VMIN_LINE_WIDTH=0.2 mm

MAKE_BASE=TRUE

MEMVREF_OUT

=PP1V8_S3_MEMVREF

MEMVREF_UNBUFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9V

MEM_VREF_NB_1MEM_VREF_NB_0MEM_VREF

=MEMVREF_EN

=PP3V3_S3_MEMVREF

MEMVREF_SHDN_L

29

63

14

14

28

62

63

www.vinafix.vn

VTT_PWRGD*/PD

DOT96T/27MHZ_NON-SPREAD

SRCT_0/LCD100MT

CPUC2_ITP/SRCC_10

VDD48

XIN

VDD_PCI1

VDD_SRC0

VDD_REF

VDD_SRC1

VDD_SRC2

VDD_SRC3

REF1/FCTSEL0REF0/FSC

FSA/48M

DOT96C/27MHZ_SPREAD

CLKREQ_8*

SRCT_8

SRCC_8

SRCT_7SRCC_7

CLKREQ_6*

CPUT2_ITP/SRCT_10

IREF

SDATASCLK

VSS_REF

VSS_PCI1

VSS_PCI0

VSS_CPU

VSS48

VSS_SRC

PCIF1

PCI1

SRCT_5

THRML_PAD

PCI4

PCI2

FSB

CLKREQ_4*

SRCC_5

SRCC_4

SRCT_4

SRCT_3CLKREQ_3*

SRCC_3

SRCC_2SRCT_2

SRCC_1

CLKREQ_1*

SRCT_1

SRCC_0/LCD100MC

CPUC1CPUT1

CPUC0

CPUT0

PCI_STP*CPU_STP*

SRCC_6

CLKREQ_5*

SRCT_6

PCIF0/ITP_SEL

PCI5/FCTSEL1

PCI3

XOUT

VDDAVSSA

VDD_PCI0

VDD_CPU

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO

OUT

IN

IO

IO

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(NO USED)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)(ICH SM BUS)

(ICH7M PCI 33MHZ)(PORT80 LPC 33MHZ)

0

(INT PU)

(ICH7M,SIO,LPC REF. 14.318MHZ)

(INT PD)

(GMCH G_CLKIN 100 MHZ )

(FROM ICH7 GPIO18 STPPCI* )(FROM ICH7 GPIO20 STPCPU* )

(GMCH HOST 133/167MHZ)

(ITP HOST 133/167MHZ)

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

PROTO TO REMOVE 100M FROM SIGNAL NAME)(SIGNAL NAME WILL BE CHANGED POST(INT PU)

(CPU HOST 133/167MHZ)

(NOT USED )

(INT PD)

(INT PU)

(INT PD)

(INT PU)

(INT PU)

PIN 6

* FOR EXT. GRAPHIC SYSTEM

* FOR INT. GRAPHIC SYSTEM

SRCT0SRCT0

DOT96CDOT96TDOT96T

PIN 7 PIN 10 PIN 11100MC_SST

FCTSEL100

0 111 1 OFF LOW

27M NONSPREAD 27MSPREAD

TBD

DOT96C 100MT_SSTSRCT0

SRCC0SRCC0SRCC0

FCTSEL0

(INT PU)

(ICH SATA 100 MHZ)

(TPM LPC 33MHZ)(SMC LPC 33MHZ)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)(EACH POWER PIN PLACED ONE 0.1UF)

(INT PU)(INT PU)

(GPU PCI-E 100 MHZ )

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?(ICH7M DMI 100 MHZ )

(FROM ICH7 GPIO35)

(FROM GMCH CLK_REQ*)

(WIRELESS PCI-E 100 MHZ )

(GIGA LAN PCI-E 100 MHZ )

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

(FROM CPU VCORE PWR GOOD)(ICH7M USB 48MHZ)

NEED TO CHECK CAP VALUE

(FOR PCI-E CARD)

(FW PCI 33MHZ)

603

NOSTUFF

X5R

10UF20%6.3V2

1C3309

FERR-120-OHM-1.5A

040221

L3302

0.1UF10%X5R16V402

2

1C330516VX5R402

10%0.1UF2

1C3306

16VX5R

0.1UF10%

4022

1C3307

0.1UF10%

40216VX5R2

1C3308

CY284455

CRITICAL

QFNOMIT

5051

2

39

31

52

6662

46

5

38

35

28

17

12

49

67

61

43

3

69

33

29

26

23

21

18

15

13

10

32

30

27

24

22

19

16

14

11

4847

5354

168

56

6564635857

40

8

4

67

37

42

45

36

41

44

55

34

25

60

20

59

9

U330150V402CERM5%18pF

2

1C339050V5%CERM402

18pF2

1C3389

MF-LF1%475

4021/16W2

1R3300

20%10UF6.3VX5R603

2

1C331216V0.1UF

402X5R10%

2

1C3311

402

10%16VX5R

0.1UF2

1C3304X5R16V402

0.1UF10%2

1C33030.1UF10%16VX5R4022

1C3302

402X5R16V0.1UF10%

2

1C3301

1UF6.3VCERM10%

4022

1C3310

10UF

6036.3V20%X5R2

1C331610%X5R16V402

0.1UF2

1C3315

FERR-120-OHM-1.5A

040221

L3301

1UF10%CERM6.3V402

2

1C3314

402MF-LF1/16W5%

2.221R3302

4021/16W5%

MF-LF

1 21R3303

6036.3V20%10UFX5R2

1C3317

MF-LF402

2.25%

1/16W

21R3304

10K5%MF-LF4021/16W2

1R3301

CRITICAL

5X3.2-SM

14.3181821

Y3301

A051-6941

33 104

SYNC_DATE=10/12/2005CLOCKS

SYNC_MASTER=M42

CK410_XTAL_OUTCK410_XTAL_IN

CK410_SRC1_P

PP3V3_S0_CK410_VDDAMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

CK410_PCI4_CLK

CK410_SRC8_PCK410_SRC_CLKREQ8_L

CK410_DOT96_27M_NCK410_DOT96_27M_PCK410_PD_VTT_PWRGD_LCK410_USB48_FSA

CK410_CPU2_ITP_SRC10_P

CK410_CPU0_NPM_STPCPU_LPM_STPPCI_L

CK410_CPU1_P

MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mmVOLTAGE=3.3VPP3V3_S0_CK410_VDD_PCI

PP3V3_S0_CK410_VDD_REFVOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK410_VDD_CPU_SRCVOLTAGE=3.3V


CK410_PCI5_FCTSEL1

CK410_PCIF1_CLK

CK410_IREFSMB_CK410_DATA

CK410_SRC5_PCLK_NB_OE_L

CK410_SRC_CLKREQ6_L

CK410_CPU0_P

=PP3V3_S0_CK410

CK410_CLK14P3M_TIMERCK410_REF1_FCTSEL0

CK410_PCI2_CLK

CK410_SRC_CLKREQ1_LCK410_SRC2_N

CK410_SRC3_P

CK410_CPU1_N

CK410_LVDS_PCK410_LVDS_N

CK410_CPU2_ITP_SRC10_N

SMB_CK410_CLK

CK410_SRC_CLKREQ3_L

SB_CLK100M_SATA_OE_LCK410_SRC5_N

CK410_SRC4_PCK410_SRC4_N

=PP3V3_S0_CK410

CK410_SRC8_NCK410_SRC7_PCK410_SRC7_N

CK410_SRC6_NCK410_SRC6_P

CK410_PCI3_CLK

CK410_SRC3_N

CK410_SRC2_P

=PP3V3_S0_CK410


PP3V3_S0_CK410_VDD48VOLTAGE=3.3V

CK410_SRC1_N

CK410_FSB_TEST_MODE

CK410_PCI1_CLK

CK410_PCIF0_CLK

63

63

63

34

34

34

34 34

34

34

34

34

26

34

34

34

23

23

34

34

27

34

14

34

34

33

34

34

34

34

34

34

34

34

34

34

23

34

34

34

33

34

34

34

34

34

34

34

33

34

34

34

www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUTIN

IN

OUTIN

OUT

OUT

OUTOUT

OUT

IO

IO

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUTIN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(ExpressCard Slot)

(TO FIREWIRE PCI 33MHZ)

(TO TPM PCI 33MHZ)

(TO SMC PCI 33MHZ)(ITP HOST 133/167MHZ)

GPU CLK OE*

(WIRELESS PCI-E MINI 100MHZ)

(TO MCH FS_A)

NEED TO CHECK THE BSEL PULLS

(TO ICH7M USB 48MHZ)

(TO ICH7M PCI 33MHZ)

(PORT80 LPC 33MHZ)

(ICH7M SATA 100MHZ)

(FROM CPU FS_A)

RESERVED

(TO MCH FS_C)

(ICH7M 14.318MHZ)

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

(ICH7M DMI 100MHZ)

(GMCH G_CLKIN 100MHZ)

(GMCH HOST 133/167MHZ)

(CPU HOST 133/167MHZ)

FS_A266M

200M

133M

400M

## 1

0

0

333M100M

11111

111

111

00

000

000

0FS_C CPU

166M

FS_B0

(FROM CPU FS_C)

(FROM CPU FS_B)

(TO MCH FS_B)

(GPU PCI-E Graphics 100MHz)

(GPU 27MHz Spread / Non-Spread)

(Yukon PCI-E 100MHZ)

Yukon CLK OE*

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED

49.9

MF-LF402

1%1/16W

ITP

21

R3441

4021/16W1%

MF-LF

71.521

R3402MF-LF

1%

402

1/16W

12121

R3418

1%

402MF-LF1/16W

12121

R3419

402MF-LF1/16W5%

3321

R3422

33

5%1/16WMF-LF402

21

R3423

33

MF-LF402

5%1/16W

21

R3465

MF-LF402

1/16W

33

5%

21

R342637 34

37 34

34 22 33

MF-LF5%

1/16W402

21

R34285%1/16W

33

MF-LF402

21

R3427

1/16W5%

402

33

MF-LF

21

R3429

33

MF-LF402

5%1/16W

21

R3430

1/16W5%

402MF-LF

3321

R3433

MF-LF5%

4021/16W

3321

R3432

40

56

47

22

5%

MF-LF402

1/16W

3321

R34355%

402MF-LF1/16W

3321

R3434

49.9

MF-LF402

1%1/16W

21

R3408

49.9

MF-LF402

1%1/16W

21

R3436

49.9

MF-LF402

1%1/16W

21

R3437

49 5

1/16W5%

MF-LF

33

402

21

R3463

34 22

10K

MF-LF402

5%1/16W

2

1R3467

10K

MF-LF402

5%1/16W

2

1R3466

49.9

MF-LF402

1%1/16W

21

R3431

1/16W5%

402MF-LF

1K

2

1R3469

1/16W5%

402MF-LF

1K 21

R3468

1/16W5%

402MF-LF

1K21

R34721/16W5%

402MF-LF

1K

2

1R3470

1/16W5%

402MF-LF

1K21

R3471

1/16W5%

402MF-LF

1K

2

1R3473

1/16W5%

402MF-LF

1K 21

R3475

1/16W5%

402MF-LF

1K 21

R3474

23

49.9

MF-LF402

1%1/16W

21

R3406

34 21 5

34 21 5 33

MF-LF402

5%1/16W

21

R3478MF-LF402

5%1/16W

33 21

R3477

1/16W1%

402MF-LF

49.921

R3439

1/16W5%

402MF-LF

1K

NOSTUFF

2

1R3480

1/16W1%

402MF-LF

49.921

R3481

1/16W1%

402MF-LF

49.921

R3482

1/16W5%

402MF-LF

33 21

R3476

1/16W5%

402MF-LF

0 21

R3450

1/16W5%

402MF-LF

021

R3453

1/16W5%

402MF-LF

1K

NOSTUFF

2

1R3454

49.9

MF-LF402

1%1/16W

21

R3407

1/16W5%

402MF-LF

021

R3451

1/16W5%

402

1K

NOSTUFF

MF-LF2

1R3452

45 34 5

45 34 5

1/16WMF-LF5%

402

33 21

R34995%

4021/16W

33

MF-LF

21

R3498

34 12

49.9

MF-LF402

1%1/16W

21

R3495

49.9

MF-LF402

1%1/16W

21

R3496

MF-LF402

1/16W

33

5%

21

R3493

5%

33

4021/16WMF-LF

21

R349449.9

MF-LF1%

1/16W402

21

R3490

34 12

49.9

MF-LF402

1%1/16W

21

R3491

34 7

5%

1K

1/16W402

MF-LF

21

R34865%

1K

MF-LF1/16W402

21

R3485

34 7

79 34 11

79 34 11

402

33

MF-LF1/16W5%

21

R3411

49.9

MF-LF402

1%1/16W

ITP

21

R3440

33

MF-LF402

5%1/16W

21

R3413

402MF-LF1/16W5%

33

ITP

21

R3415

1/16W1%

402MF-LF

49.921

R3438

49.9

MF-LF402

1%1/16W

21

R3404

49.9

MF-LF402

1%1/16W

21

R3442

33

402

5%1/16WMF-LF

21

R3412

1/16W5%

402MF-LF

33 21

R3414

49.9

MF-LF402

1%1/16W

21

R3403

1/16W1%

402MF-LF

71.521

R3405

1/16W1%

402MF-LF

49.921

R3400

1/16W

402MF-LF

5%

33

ITP

21

R3416

1/16W5%

402MF-LF

33 21

R3417

1/16W5%

402MF-LF

2.2K21

R3401

Clock TerminationSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

34 104

A051-6941

GPU_CLK27MSS_IN

GPU_CLK27M GPU_CLK27M

GPU_CLK27MSS_IN

SB_CLK100M_SATA_P

CPU_XDP_CLK_P

CK410_CPU1_N

CK410_SRC2_N

CK410_SRC4_N

CK410_PCIF1_CLK

PCI_CLK_SMC

CK410_SRC5_N

CK410_SRC_CLKREQ6_L

EXCARD_CLKREQ_LMAKE_BASE=TRUEMINI_CLKREQ_L

MAKE_BASE=TRUE

CK410_SRC7_N

CK410_SRC_CLKREQ1_L

CK410_SRC_CLKREQ8_L

CK410_LVDS_N

PEG_CLK100M_GPU_P

PEG_CLK100M_GPU_N

SB_CLK48M_USBCTLR

CK410_PCI3_CLK

PCI_CLK_TPMCK410_PCI2_CLK

PCI_CLK_FWCK410_PCI1_CLK

CK410_PCIF0_CLK

PCI_CLK_SB

CK410_PCI4_CLKMAKE_BASE=TRUETP_CK410_PCI4_CLK

MAKE_BASE=TRUETP_CK410_SRC7P

CK410_LVDS_PMAKE_BASE=TRUETP_CK410_LVDSP

CK410_SRC1_N PEG_CLK100M_GPU_N

PCIE_CLK100M_EXCARD_N

SB_CLK100M_SATA_N

SB_CLK100M_SATA_P

NB_CLK100M_GCLKIN_N

NB_CLK100M_GCLKIN_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_P

ENET_CLK100M_PCIE_N

ENET_CLK100M_PCIE_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_CLK_NB_N

FSB_CLK_NB_P

CPU_XDP_CLK_P

CPU_XDP_CLK_N

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

NB_CLK100M_GCLKIN_N

PCIE_CLK100M_MINI_N

CPU_XDP_CLK_N

CK410_CPU2_ITP_SRC10_P

FSB_CLK_NB_N

FSB_CLK_NB_PCK410_CPU1_P

CK410_CPU0_N FSB_CLK_CPU_N

CK410_CPU0_P FSB_CLK_CPU_P

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_BSEL<0>

CK410_FSB_TEST_MODE

CK410_USB48_FSA

NB_BSEL<2>

CPU_BSEL_R<0> CPU_BSEL<0>

CK410_CLK14P3M_TIMER

CPU_BSEL_R<1>

NB_BSEL<1>

CPU_BSEL<1>

CK410_SRC3_N

ENET_CLK100M_PCIE_N

CPU_BSEL<2>

SB_CLK100M_SATA_N

SB_CLK100M_DMI_P

CK410_SRC8_N

CK410_SRC8_P

CK410_SRC4_P

PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

CK410_SRC1_P

MAKE_BASE=TRUETP_CK410_LVDSNCPU_BSEL_R<2>

CK410_REF1_FCTSEL0

SB_CLK14P3M_TIMER

CK410_PCI5_FCTSEL1

=PP1V05_S0_FSB_NB

=PP3V3_S0_CK410

CK410_SRC7_P

PEG_CLK100M_GPU_P

ENET_CLK100M_PCIE_P

NB_CLK100M_GCLKIN_P

CK410_SRC6_N

CK410_SRC5_P

PCIE_CLK100M_MINI_P

SB_CLK100M_DMI_N

CK410_SRC2_P

CK410_SRC_CLKREQ3_L

CK410_CPU2_ITP_SRC10_N

CK410_SRC6_P

PCI_CLK_PORT80_LPC

MAKE_BASE=TRUETP_CK410_SRC7N

CK410_SRC3_P

CK410_27M_NONSPREADMAKE_BASE=TRUE

CK410_27M_SPREADMAKE_BASE=TRUE

CK410_DOT96_27M_N

CK410_DOT96_27M_P

63

63

63 34

34

45

45

79

79

45

34

34

45

45

34

45

69

69 69

69

45

45

33

33

65

65

33

33

65

21

21

34

34

34

34

37

37

34

34

34

34

34

34

34

34

34

34

19

19

34

34

19

63

33

65

34

34

34

34 34

34

33

33

33

33

33

33

5

5

33

33

34

34

23

33

33

33

33

33 34

5

5

14

14

5

5

34

34

7

7

12

12

11

11

22

22

14

5

33

33

33

33

12

12

14

33

33

14

7

33

14

7

33

7

33

33

33

5

5

33

33

33

12

33

34

14

33

33

5

33

33

33

33

33

33

33

www.vinafix.vn

NC7

NC6NC5

NC4

NC2

NC3

OUT

VDD

NC0

NC1

VIO

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NCNC

TPM Crystal Circuit

SMC G3Hot Oscillator

NCNC

NC

NC

NCNC

NC

NC

SM-2

CRITICAL

32.768K

31

42

Y3720

5%

402

0

1/16WMF-LF

21

R3721

1/16W5%

402MF-LF

NO STUFF

10M

2

1R3720

SG-3040LC-SM

CRITICAL

32.768KHZ-9-3.6V

1

12

7

11

10

98

5

4

32

6

U375010V

CERM402

20%0.1uF

2

1C3751SM

FERR-EMI-100-OHM21

L3750

4.7uF20%

CERM603

6.3V2

1 C3750

5%1/16WMF-LF

22

402

21

R3750

15pF

50VCERM402

5%

21

C3720

15pF

CERM402

5%50V

21

C3721

Mobile ClockingSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10437

SMC_SUS_CLKSMC_CLK32K_SUSCLKMAKE_BASE=TRUE

VOLTAGE=3.425V

PP3V42_G3H_SMC_CLK_FMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TPM_XTALO

=PP3V42_G3H_SMC_CLK

SMC_CLK32K_SUSCLK_R

TPM_XTALO_R

TPM_XTALI

47

56

63

56

www.vinafix.vn

IN

IO

IO

IO

IO

IO

IN

IO

IO

IO

IN

IN

IN

IN

OUT

GDS

IN

IO

IO

IO

IO

IO

IO

IO

IO

IN

OUT

OUT

INOUT

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Indicates disk presence

516S0335

IDE (ODD) Connector

(UATA_STOP)

Placement notePlace within 12.7mmfrom ball of SB

(UATA_CS1*)

NC

(UATA_DSTROBE)(UATA_HSTROBE)

(UATA_CS0*)

Counters 10K pull-up to 5V inODD to keep SB GPIO <= 3.3V

1/16W

100

402MF-LF

5%

2

1R3850

M-ST-SM1-LF

CRITICAL

9876

50

5

49484746454443424140

4

39383736353433323130

3

2928272625

2423222120

2

19181716151413121110

1

J3800

1%24.91/16WMF-LF4022

1R3860

1/16W402

MF-LF

NO STUFF

4.7K5%

2

1R3801

402

4.7K

MF-LF5%

1/16W

2

1R3802

6.2K

MF-LF402

5%1/16W

2

1R3803

33K

MF-LF402

5%1/16W

2

1R3810

BGA

CRITICAL

FDZ293PB3

B2

B1

A3

A2

A1

C3

C2

C1

Q3820

1/16W5%

402MF-LF

10K

2

1R3820

0.22uF

402X5R6.3V20%

21

C3821

10K

MF-LF402

5%1/16W

2

1R3821

1/16WMF-LF

402

5%15K

2

1R3811

SYNC_MASTER=(MASTER)

10438

A051-6941

PATA ConnectorSYNC_DATE=(MASTER)

IDE_RESET_L

IDE_PDD<12>

SATA_RBIAS_NSATA_RBIAS_P

IDE_PDA<2>IDE_PDCS1_L

IDE_PDA<0>

IDE_PDD<7>IDE_PDD<6>IDE_PDD<5>


IDE_PDD<8>IDE_PDD<9>IDE_PDD<10>IDE_PDD<11>


IDE_PDDACK_L

IDE_PDA<1>

IDE_PDCS3_L

IDE_PDD<4>

SATA_A_R2D_C_N

SATA_C_DET_L

SATA_A_R2D_C_P TP_SATA_A_R2DPMAKE_BASE=TRUE

SATA_A_D2R_P TP_SATA_A_D2RPMAKE_BASE=TRUE

SATA_A_D2R_N TP_SATA_A_D2RNMAKE_BASE=TRUE

TP_SATA_A_R2DNMAKE_BASE=TRUE

SATA_RBIASMAKE_BASE=TRUE

ODD_PWR_EN_L

IDE_PDD<13>

=PP5V_S0_IDE

IDE_PDD<0>

ODD_PWR_EN_L_RC

IDE_IRQ14

IDE_PDD<3>

IDE_PDIORDYIDE_PDIOR_LIDE_PDDREQ

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=5V

PP5V_S0_IDE_ODD

SMC_ODD_DETECT

IDE_PDIOW_L

=PP3V3_S0_IDE

23

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

23

21

21

21

22

21

63

21

21

21

21

21

21

47

21

63

www.vinafix.vn

OUT

OUT

AVDDL0

AVDDL4

AVDD

THRML_PAD

VDDO_TTL0

AVDDL6

VDDO_TTL1

RX_N

TESTMODE

TSTPT

LINK*

LED_LINK10/100*

LED_LINK1000*

LED_ACT*

RSET

CTRL25

CTRL12

HSDACNHSDACP

SWITCH_VAUX

SWITCH_VCCVMAIN_AVLBL

VAUX_AVLBL

LOM_DISABLE*

XTALO

XTALI

SPI_DOSPI_CLK

SPI_CS

SPI_DI

VPD_CLK

VPD_DATA

MDIP3

MDIN3

MDIN2MDIP2

MDIN1

MDIP1

MDIN0MDIP0

WAKE*

REFCLKN

TX_N

VDDO_TTL3

VDDO_TTL2

VDDO_TTL4

VDD0

VDD1

VDD3

VDD2

VDD6

VDD5

VDD4

VDD7

AVDDL1

AVDDL2

AVDDL5

VDD25

PERST*

REFCLKP

RX_P

AVDDL3

TX_P

PU_VDDO_TTL0PU_VDDO_TTL1

TEST

TESTTWSI

SPI

MAIN CLK

PCI EXPRESSANALOG

MEDIALED

E2

WC*

NC0NC1

VCC

VSS

SCL

SDA

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

12 MIL OF U2100 E27 AND E28

NC

INTERNAL PULL-UP

NCNC

OPTIONAL EXTERNAL LDO

PLACE RESISTORS CLOSE TO U4101

ASF IS UNAVAILABLE ON 8053

1. KEEP ENET_XTALI AND ENET_XTALO

NC

NCNCNC

NCNC

NC

2. DO NOT ROUTE UNDER CRYSTAL

NCNC

SCHEME MATCHES DOC MVL100258-01PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

SCHEME MATCHES DOC MVL100258-01

PLACE C4140 NEAR U4102 VCC

PLACE C4107 NEAR U4101 AVDD

12 MIL OF U4101 PIN 49 AND 50PLACE C4110 AND C4111 WITHIN

SCHEME MATCHES DOC MVL100258-01PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

PLACE C4113 AND C4112 WITHIN

NO PULL-UP NEEDED

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

TRACE LENGTH <12MIL

27pF50VCERM5%

4022

1 C4151

5%

4.7K

1/16W

MF-LF

402

21R4122

4.7K

MF-LF

5%

402

1/16W

21R4123

40216VX5R10%0.1UF

2

1 C4101

CRITICALOMIT

QFN88E8053

1415

6

4138

47

61

4540 8 1

5848

44

3933

64

13 7 2

124950

29

65

46

119

3435

36

37

54

53

16

5556

43

42

5

30

26

20

17

31

27

21

18

10

63

6260

59

24

25

4

3

5752

51

3228

2219

23

U4101

16V10%0.1UF

402X5R2

1 C4140

SO8

CRITICAL

M24C08

OMIT

7

4

8

5

6

2

1

3

U4102

1/16W

1%

4.87K

MF-LF

402

21R4102

0.1UF

X5R402

10%16V2

1 C4107

402

10%16VX5R0.1UF

21

C4110

16V10%

0.1UF402

X5R

21

C411110%0.1UF

40216V

X5R

21

C4112

402X5R16V10%

0.1UF

21

C4113

402MF-LF

1%49.91/16W

2

1R4106

402

1%1/16WMF-LF

49.9

2

1R4117

402MF-LF1/16W

49.91%

2

1R41181%49.91/16WMF-LF4022

1R4119

402

1/16W1%

MF-LF

49.9

2

1R4120

MF-LF

49.9

402

1%1/16W

2

1R4103

402MF-LF1/16W1%49.9

2

1R4104

402MF-LF1/16W1%49.9

2

1R4105

50V10%

402CERM

0.001UF2

1 C4116

402

10%0.001UF50VCERM2

1 C41180.001UF

CERM

10%

402

50V2

1 C4117

402

50V10%

CERM

0.001UF2

1 C4115

402CERM6.3V10%1UF

2

1 C4100

FERR-120-OHM-1.5A

0402

21

L4100

4.7K5%1/16WMF-LF4022

1R4131

402MF-LF1/16W5%4.7K

2

1R4130

4.7K

1/16W

402

5%

MF-LF

21R4101

0.001UF

CERM10%50V402

2

1 C4105

X5R10%0.1UF

40216V2

1 C4104

402

0.1UF

X5R10%16V2

1 C410310%0.1UF

X5R40216V2

1 C41020.001UF

402CERM50V10%

2

1 C4106

40216V0.1UF

X5R10%

2

1 C41280.001UF10%

40250VCERM2

1 C413350V402CERM

0.001UF10%

2

1 C4134

402CERM

0.001UF10%50V2

1 C413110%0.001UF

CERM40250V2

1 C413216V10%X5R402

0.1UF2

1 C412710%X5R40216V0.1UF

2

1 C412616V402X5R

0.1UF10%

2

1 C412916V10%

402X5R

0.1UF2

1 C4130

402CERM10%50V0.001UF

2

1 C41390.001UF50VCERM402

10%2

1 C413816V0.1UF

X5R402

10%2

1 C4137

402

10%X5R

0.1UF16V2

1 C4136

402X5R

0.1UF10%16V2

1 C4135

25.0000MSM-3.2X2.5MM

CRITICAL

3 1

4 2

Y4101

27pF

402CERM50V5%

2

1 C4150

A051-6941

104


ETHERNET CONTROLLER

41

ENET_MDI2

ENET_MDI_N<1>

=PP1V2_S3_ENET

ENET_CTRL12ENET_CTRL25

ENET_VPD_CLK

=PP3V3_S3_ENET

PCIE_A_D2R_PPCIE_A_D2R_NPCIE_A_D2R_C_N

=PP3V3_S3_ENET

ENET_MDI3

PCIE_A_R2D_C_P

ENET_MDI0

PCIE_A_R2D_C_N

ENET_MDI1

ENET_PU_VDD_TTL0

PCIE_A_R2D_P

ENET_LOM_DIS_L

ENET_RSET

=PP3V3_S3_ENET

ENET_PU_VDD_TTL1

PCIE_WAKE_L

=PP2V5_S3_ENET

PCIE_A_D2R_C_P

ENET_PU_VDD_TTL1

ENET_CLK100M_PCIE_PENET_CLK100M_PCIE_N

ENET_RST_L

=PP3V3_S3_ENET

ENET_VPD_DATAENET_VPD_CLK

ENET_MDI_N<0>

=ENET_VMAIN_AVLBL

ENET_PU_VDD_TTL0ENET_VPD_DATA

PP2V5_S3_ENET_AVDDMIN_NECK_WIDTH=0.22MMMIN_LINE_WIDTH=0.4MM

VOLTAGE=2.5V

ENET_MDI_P<0>

=PP3V3_S3_ENET

PCIE_A_R2D_N

ENET_MDI_P<1>

ENET_MDI_N<3>ENET_MDI_P<3>ENET_MDI_N<2>ENET_MDI_P<2>

=PP1V2_S3_ENET

ENET_XTALIENET_XTALO

45

63 63

63

63

23

63

63 63

38

37

6

6

37

37

22

22

37

22

22

37

6

37

37

5

63

37

34

34

26

37

37

37

38

62

37

37

38

38

37

38

38

38

38

38

37

www.vinafix.vn

SYM_VER2

NC2 NC3NC4

LINE

SIDE

CHIP

SIDENC1

SYM_VER2

NC2 NC3NC4

LINE

SIDE

CHIP

SIDENC1

IN

IO

IO

IO

IO

IO

IO

IO

IO

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

mirrored on opposite

- =GND_CHASSIS_ENET

sides of the board

Transformers should be

PHY

ETHERNET

BY

- =PP2V5_ENET

(NONE)

Signal aliases required by this page:(NONE)


Page Notes

SPACINGNET_TYPE

Place one cap at each pin of transformer

ELECTRICAL_CONSTRAINT_SET

PROVIDED

PHYSICAL

Short shielded RJ-45514-0277

Place close to connector


1/16W

NO STUFF

5%MF-LF

0

402

21

R4210

1uF6.3V10%CERM402

2

1 C42031uF6.3V10%CERM402

2

1 C4202

100pF

CERM1808

10%3KV

1 2

C42041/16W5%

402MF-LF

75

2

1R42031/16W5%

402MF-LF

75

2

1R42021/16W

5%

402MF-LF

75

2

1R42011/16W

5%

402MF-LF

75

2

1R4200

6.3V402

1uF10%CERM2

1 C42011uF

CERM6.3V10%

4022

1 C4200

XFR-SM

CRITICAL1000BT-824-00275

13125

4

98

7

6

3

2

16

15

14

11

10

1T4200

XFR-SM

1000BT-824-00275CRITICAL

13125

4

98

7

6

3

2

16

15

14

11

10

1T4201

CRITICAL

JM36113-P2054-7FF-RT-TH-RJ45

8

7

6

5

4

3

2

1

12

11

10

9

J4200


Ethernet Connector

104

051-6941

42

A

ENET_CTAP0

ENETCONN_P<1>

ENETCONN_P<0>

PP2V5_S3_ENET_AVDD

ENET_MDI_N<1>

=GND_CHASSIS_ENET

ENETCONN_N<0>

ENETCONN_P<2>

ENETCONN_N<2>

ENETCONN_N<1>

ENETCONN_N<3>

ENET_CTAP2

ENET_CTAP3

ENET_CTAP1

ENET_100DENETCONN ENETCONN_P<1>

ENET_100DENETCONN ENETCONN_N<3>

ENET_100DENETCONN ENETCONN_N<1>

ENET_100DENETCONN ENETCONN_N<0>ENET_100DENETCONN ENETCONN_P<0>

ENET_100DENETCONN ENETCONN_P<3>ENET_100DENETCONN ENETCONN_N<2>

ENET_MDI_N<0>

ENET_MDI_P<1>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_N<3>

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

ENET_CTAP_COMMON

ENET_MDI_P<3>

ENET_MDI_P<0>

ENET_100DENETCONN ENETCONN_P<2>

ENETCONN_P<3>

38

38

37

37

6

38

38

38

38

38

38

38

38

38

38

38

38

37

37

37

37

37

37

37

38

38

www.vinafix.vn

G

D

S

N-CHN

S

D

G

P-CHN

G

DS

G

D

S

G

D

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Yukon Power Control

G3H 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S5 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S3 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

S0 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

G3H Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S5 Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S5 AC 0V 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)

S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 3.3V (2.5V OFF) 0V (1.2V OFF)

S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS

State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS

When ENETPWR_S3AC BOMOPTION is active:

When ENETPWR_S3 BOMOPTION is active:

1.2V enable has pull-up to 3.3V

Allows powering Yukon down during battery sleep to save power

S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)

5%1/16WMF-LF402

470K

2

1R4302

2N7002DW-X-FSOT-363

4

5

3

Q4304

MF-LF

100K1/16W5%

4022

1R4304

0

ENETPWR_S3AC

402MF-LF1/16W5%

21

R4300

0

402MF-LF1/16W5%

ENETPWR_S3

2

1R4301

SC70-6FDG6332C_NL

1

2

6

Q4300

FDG6332C_NLSC70-6

4

5

3

Q4300

2N7002SOT23-LF

2

1

3

Q4302

SOT-3632N7002DW-X-F

1

2

6

Q4304

402

5%1/16WMF-LF

100K

2

1R4305


Yukon Power Control

051-6941 A

10443

FWPWR_EN_L

=PPBUS_G3H_S3AC

MAKE_BASE=TRUEP2V5S3_EN_L =P2V5S3_EN_LPM_SLP_S3BATT_L

PPVIN_S3_P2V5S3_SVIN

=PP3V3_S3_P3V3S3AC =PP3V3_S3AC_FET

PM_SLP_S4_L

FWPWR_EN_L_OR_GND

PM_SLP_S3BATT

P1V2S3_RUNSS

62 47

59

41

63

59

59

63 63

23

5

www.vinafix.vn

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IN

IN

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

MPCI_ACTN_323

TPB0_P

TPBIAS0

PCI_AD12

RESET*

TPBIAS2

PCI_RST*PCI_INTA*

PCI_PME*

PCI_AD21

PCI_AD31

XO

XI

R1

R0

TPA0_N

TPA0_P

TPB0_NTPBIAS1

TPA1_P

TPB1_PTPA1_N

TPA2_P

TPA2_N

TPB2_PTPB2_N

MODE_AMODE_420

TEST0TEST1

PTEST

SESM

VSS21

VSS22

VSS20

VSS18

VSS19

VSS16

VSS15

VSS17

VSS13

VSS14

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VSSA0

VSSA1

VSSA3

VSSA4

VSSA2

VDDA4

VDDA5

VDDA3

VDDA2

VDDA1

VDDA0

VDD0

VDD2

VDD1

VDD3

VDD4

VDD7

VDD9

PCI_VIOS

PCI_AD0

PCI_AD2

PCI_AD4PCI_AD5

PCI_AD3

PCI_AD6

PCI_AD9PCI_AD10

PCI_AD8

PCI_AD11

PCI_AD14

PCI_AD15

PCI_AD13

PCI_AD16

PCI_AD17

PCI_AD18PCI_AD19

PCI_AD20

PCI_AD23

PCI_AD22

PCI_AD25

PCI_AD28

PCI_AD26

PCI_AD29PCI_AD30

PCI_CBE2*

PCI_CBE1*PCI_CBE0*

PCI_CBE3*

PCI_PARPCI_FRAME*

PCI_IRDY*

PCI_TRDY*PCI_DEVSEL*

PCI_STOP*PCI_IDSEL

PCI_REQ*

PCI_GNT*

PCI_PERR*PCI_SERR*

PCI_CLK

CLKRUN*

VDD5

PCI_AD27

PCI_AD24

VDD6

PCI_AD1

TPB1_N

PC0

PC2CONTENDER

CARDBUSN

PCI_AD7

PC1

IO

IO

IO

IO

IO

IO

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

197S0178 3.2MMX2.5MM

SPEC RECOMMENDS 2.49K

THIS IS FROM ICH-7M

CONNECT TO VDD FOR 3.3V OPERATION

MANUFACTURING TEST PINS

LOW = NOT BUS MANAGERLOW = PCI OPERATION

MODE FOR EXTERNAL LINK

0.001A DURING SLEEP

PLACE ONE CAP PER TWO PINS STARTING WITH C4416 ON VDDA0

PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0

SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)

PCI_GNT3_L - PCI GRANT FROM SB=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)

7/26/2005 - CONNECTED PIN E10 TO GND

5/19/2005 - FIRST REVISION OF PAGE6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)

FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRSPCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_LPCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,

6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)

6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE

INT_PIRQD_L - INTERRUPT TO SBPCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)

FW_PC0 - FIREWIRE POWER CLASS IDENTIFIERPCI_RST_L - PCI RESET FROM SB

PCI_REQ3_L - PCI REQUEST TO SBPM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL

PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE

INPUT/OUTPUT

FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS

6/22/2005 - REMOVED C4421 - REDUNDANT

OUTPUT

6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT

PAGE NOTESINPUT

FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS

6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE

PAGE HISTORY6/20/2005 - BGA VERSION OF FW323-06 ADDED

6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L

NEED TO CHECK CRYSTAL LOAD CAPACITANCE

6.3V20%

603X5R

10UF2

1 C4416

1/16W1%

402MF-LF

2.49K

2

1R4452

10V20%

402CERM

0.1UF2

1 C442810V20%

402CERM

0.1UF2

1 C442610V20%

402CERM

0.1UF2

1 C442210V20%

402CERM

0.1UF2

1 C4418

16V10%

402X5R

0.1UF2

1 C442916V10%

402X5R

0.1UF2

1 C442516V10%

402X5R

0.1UF2

1 C4417

16V10%

402X5R

0.1UF2

1 C4420

1/16W5%

402MF-LF

390 21

R4400

6.3V20%

603X5R

10UF2

1 C4424

0402

600-OHM-300MA21

L4400

CRITICAL

OMITBGA

FW32306B5

A5

D5D7D9E9

E13

F8F7F6F4E5E4D4

N13

K9K8

C3

J10

J9J5H8H7H6G8G7G6G1

B2A1

D6A8A7

B13

A13

D10

A2

H13

L13

K7K6K5N2N1G4

C13

D8

B8

D13D12

B12A12

B10A10

C11C12

A11B11

A9B9

C1C2

B3A3

B4

A6

B7

A4

G13

N7

M7

N9

F1

E2

F2

M8

N10

M6

D2

L2

E1

N6

N8

G2

L1L3M9K12

M13L12K10K13J12J13

H1H4

H12

H2J1J2K1J4K2M1K4N3M2

H10

M3N4N5M4N11M10N12M11M12L11

G10F10

F12F13E12

E10

B6M5

G12

D1

B1

U4400

1/16W5%

402MF-LF

510K

2

1R4420

1/16W5%

402MF-LF

10021

R4432

SM21

XW4400

1/16W5%

402MF-LF

22

2

1R4431

24.576MHZ

CRITICAL

SM-3.2X2.5MM

31

42

Y4403

CERM50V402

5%22pF

2

1C44115%

402CERM50V22pF

2

1 C4412

10V20%

402CERM

0.1UF2

1 C443010V20%

402CERM

0.1UF2

1 C4432

SYNC_MASTER=(M42) SYNC_DATE=08/29/2005

FIREWIRE CONTROLLER

051-6941 A

10444

PCI_PME_FW_L

PCI_C_BE_L<2>

FW_XO_R

FW_R0

FW_R1

=PP3V3_S3_PCI

FW_PWRON_RST_L

PP3V3_S3_FW_AVDD

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MMVOLTAGE=3.3V

=PP3V3_S3_FW

PCI_AD<19>

FW_PCI_IDSEL

FW_A_TPA_N

FW_A_TPBIAS

FW_A_TPB_NFW_B_TPBIAS

FW_B_TPA_NFW_B_TPA_P

FW_B_TPB_PFW_B_TPB_NFW_C_TPBIAS

FW_C_TPA_NFW_C_TPA_P

FW_C_TPB_PFW_C_TPB_N

FW_PC0

PCI_AD<0>PCI_AD<1>PCI_AD<2>

PCI_AD<4>PCI_AD<3>

PCI_AD<5>

PCI_AD<7>PCI_AD<6>

PCI_AD<9>PCI_AD<8>


PCI_AD<14>PCI_AD<13>


PCI_AD<15>

PCI_AD<18>



PCI_AD<25>



PCI_AD<31>

PCI_C_BE_L<0>PCI_C_BE_L<1>

PCI_PAR

PCI_C_BE_L<3>

PCI_FRAME_L

PCI_TRDY_LPCI_DEVSEL_LPCI_STOP_L

PCI_REQ3_LPCI_GNT3_L

PCI_SERR_LPCI_PERR_L

PM_CLKRUN_LPCI_CLK_FW

INT_PIRQD_LFW_PCI_RST_LPCI_RST_L

GND_FW_VSSA

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM

GND_FW_VSSA

PCI_IRDY_L

FW_A_TPB_P

FW_A_TPA_P

FW_XI

FW_XO

26

26

26

26

26

26

26

26

26

22

22

63

63

22

42

42

42

42

42

42

42

42

42

42

42

42

42

42

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

34

22

22

40

40

22

42

42

www.vinafix.vn

OUT

GND

OUT

VIN+ VIN-

V+

G

D

S

G

D

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

FireWire Port Current Sense

Page Notes

- =FWPWR_PWRON (see related text note below)Signal aliases required by this page:


(NONE)BOM options provided by this page:

- =PP3V3_S0_FWPORTPWRSW

1A = 1V50V/V

- =PPBUS_S0_FWPWRSW (system supply for bus power)

Port Power Switch

Enables port power when machineis running or on AC.

402MF-LF

330K5%1/16W

2

1R4566

16V20%

402

0.01uF

CERM 2

1C45651/16W5%

402

470K

MF-LF2

1R4565

CRITICAL

SMB

B340XF

21

D4565NDS9407

CRITICAL

SOI-LF

321

4

8765

Q4565

1uF

CERM402

10%6.3V 2

1C4595

SOT23-5INA194

CRITICAL

43

5 1

2

U4595

0.5%1W

0612MF

0.0221

R4570

2N7002DW-X-FSOT-363

4

5

3

Q4560

SOT-3632N7002DW-X-F

1

2

6

Q4560

MINISMDC

1.1A-24V

CRITICAL

21

F4565


FireWire Port Power

A051-6941

45 104

FWPWR_EN_LMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

=PPBUS_S5_FWPWRSW


FWPWR_EN_L_DIV

SMC_ADAPTER_EN

PM_SLP_S3_L

PPBUS_S5_FWPWRSW_F

VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPBUS_S5_FW_FET_D

VOLTAGE=12.6V

PPBUS_S5_FW_FET_D_RMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

=PPBUS_S5_FW_FET

=PP3V3_S0_FWISENSFWPWR_IOUT

48 47

62

45

47

39

63

5

23

63

63

51

www.vinafix.vn

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

SYM_VER-2

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NOTE: This page is expected to contain

properly terminate unused signals.

to apply to entire TPA/TPB XNets.

"Snapback" & "Late VG" Protection

(TPB-)

- =PPFW_PORT1

NOTE: FireWire TPA/TPB pairs are NOT

514-0255

the necessary aliases to map the

(TPB+)

(TPA+)

(TPA-)

(PPFW_PORT1_VP)

1394b implementation based on Apple


FireWire TPA/TPB pairs to their


(NONE)

(NONE)

FireWire Design Guide (FWDG 0.6, 5/14/03)

appropriate connectors and/or to

BY

PAGEPHY

SPACINGNET_TYPE

PHYSICAL

PROVIDEDELECTRICAL_CONSTRAINT_SET

- =PP3V3_S5_FWLATEVG- =GND_CHASSIS_FW_PORT1


Page Notes

provide the appropriate constraints

Termination

Cable Power

Single-port system sets PC=0

(GND_FW_PORT1_VG)

FW Power Class Strap

Place close to FireWire PHY

assumed that FireWire PHY page will

2nd TPA/TPB pair unused

Late-VG Protection Power

3rd TPA/TPB pair unused

constrained on this page. It is

1394APORT 1

SM-1

400-OHM-EMI21

L4690330

5%1/16W402

MF-LF

21

R4690

FERR-250-OHM

SM

21

L4620

0.001uF

CERM20%50V402

2

1 C4624

SOT-363BAV99DW-X-F

3

5

4

DP4620

0.001uF

CERM40250V20%

2

1C4621

60350V20%CERM

0.01uF2

1 C4625

40216V

0.01uF

CERM20%

2

1C4626

SOT-363BAV99DW-X-F

3

5

4

DP4621

0.001uF

CERM20%50V402

2

1C4623

BAV99DW-X-FSOT-363

6

2

1

DP4620

0.001uF

402

20%CERM50V 2

1C4620

BAV99DW-X-FSOT-363

6

2

1

DP4621

CERM402

20%50V

0.001uF2

1C4622

6.3V10%

402

0.33uF

CERM-X5R2

1 C4650

1/16W

56.2

MF-LF402

1%

2

1R465156.2

MF-LF402

1%1/16W

2

1R4650

56.2

MF-LF402

1%1/16W

2

1R4653

MF-LF402

1%1/16W

56.2

2

1R4652

MF-LF1%

1/16W

4.99K

4022

1R4654220pF25V5%

402CERM2

1 C4654

F-RT-TH-LF1394A

CRITICAL

1

2

5

6

3

4

10987

J4620

260-OHM-330MASM1

CRITICAL

3

21

4

FL4620

260-OHM-330MASM1

CRITICAL

3

21

4

FL4621

0.001uF

CERM402

10%50V 2

1C4692MMBZ5227BSOT23

CRITICAL3

1

D469010V

0.1uF

CERM402

20%2

1C4691

1/16W5%

402MF-LF

0 21

R4699

051-6941 A

46 104

FireWire PortsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

PP3V3_S5_FWLATEVG_R_F

MAKE_BASE=TRUENC_FW_B_TPBIASNO_TEST=YES

FW_PORT1_TPA_FL_NFW FW_110D

FW_A_TPBIAS

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S5_FWLATEVG_R

=PP3V3_S5_FWLATEVG

FW_PC0

FW_C_TPB_N

FW_C_TPB_P

NO_TEST=YESMAKE_BASE=TRUENC_FW_C_TPAP

FW_A_TPA_P

FW_A_TPA_N

FW_PORT1_TPB_NMAKE_BASE=TRUE

FW_PORT1_TPB_FL_NFW FW_110D

FW_C_TPA_P

FW_B_TPB_N

FW_PORT1_TPA_FL_PFW FW_110D

FW_PORT1_TPB_FL_PFW_110DFW

FW_PORT1_TPA_NMAKE_BASE=TRUE

MAKE_BASE=TRUEFW_PORT1_TPA_P

FW_B_TPA_P

FW_B_TPBIAS

FW_B_TPA_N FW_C_TPA_N

=GND_CHASSIS_FW_EMI

MAKE_BASE=TRUEFW_PORT1_TPB_P

NC_FW_B_TPANNO_TEST=YESMAKE_BASE=TRUE

NO_TEST=YESMAKE_BASE=TRUENC_FW_B_TPBP

NC_FW_B_TPBNNO_TEST=YESMAKE_BASE=TRUE

NC_FW_C_TPBNNO_TEST=YESMAKE_BASE=TRUE

NC_FW_C_TPBPNO_TEST=YESMAKE_BASE=TRUE

FW_B_TPB_P

NC_FW_B_TPAPMAKE_BASE=TRUENO_TEST=YES

NC_FW_C_TPANNO_TEST=YESMAKE_BASE=TRUE

MAKE_BASE=TRUENO_TEST=YES

NC_FW_C_TPBIASFW_C_TPBIAS

FW_A_TPB_N

FW_A_TPB_P

PPFW_PORT1_VPMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V

=PPFW_PORT1

FW_PORT1_TPA_FL_P

FW_PORT1_TPA_FL_N

FW_PORT1_TPA_N

FW_PORT1_TPA_P

FW_PORT1_TPB_FL_P

FW_PORT1_TPB_FL_NFW_PORT1_TPB_N

FW_PORT1_TPB_P

=GND_CHASSIS_FW_PORT1

FW_TPA0_C

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S5_FWLATEVG_R_F

42

42

40

63

40

40

40

40

40

42

42

40

40

42

42

42

42

40

40

40 40

6

42

40

40

40

40

63

42

42

42

42

42

42 42

42

6

42

www.vinafix.vn

IO IO

IO

OUT

OUT

IO IO

IO

IN

OUT

SYM_VER-2

SYM_VER-2IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Twin-Ax Pair 1

Camera Connector

518S0371

(40 AWG)

Connector shield

Standard wires

Twin-Ax Pair 2

(28 AWG)

(40 AWG)

Connector shield

516S0350

Top-Case Connector

M-ST-SMQT500166-L020

CRITICAL

98765432

16151413121110

1

J4900

F-RT-SMCAMERA-M1-CUS

CRITICAL

654321

8

7

J4931

SC-75

RCLAMP0502B

CRITICAL

2

1

3

D4900

0402

FERR-220-OHM21

L4931

0402

FERR-220-OHM21

L4930

SM165-OHM

CRITICAL

4

32

1

FL4936

SM165-OHM

CRITICAL

4

32

1

FL4935

SC-75RCLAMP0502B

CRITICAL

NO STUFF2 1

3

D4930

50V20%

402CERM

0.001uF

NO STUFF

PLACEMENT_NOTE=Place next to J4931 pin 7

2

1C4931

50V20%

402CERM

0.001uF

NO STUFF

PLACEMENT_NOTE=Place next to J4931 pin 8

2

1C4930

051-6941 A

10449

Internal USB ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

=PP5V_S3_TOPCASE=PP3V42_G3H_LIDSWITCH=PP3V3_S3_TOPCASE

KBDLED_RETURN

=USB_TRACKPAD_P

SMC_ONOFF_L

=I2C_TRACKPAD_SDA

=SMBUS_TOPCASE_SDA=SMBUS_TOPCASE_SCL=I2C_TRACKPAD_SCL

KBDLED_ANODE

SMC_LID

=USB_TRACKPAD_N

=SMBUS_ATS_SCL

=USB2_CAMERA_P

=USB2_CAMERA_N

=PP5V_S3_CAMERA

=SMBUS_ATS_SDA

SMBUS_ATS_SDA_FUSB2_CAMERA_P_FUSB2_CAMERA_N_F

VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=0VGND_CAMERA

SMBUS_ATS_SCL_F

48

6

6

63

63

63

63

53

6

27

27

27

27

53

47

6

5

5

5

www.vinafix.vn

SYM_VER-2IO

IO

OUT

VBUS

D-

D+

GND

PADTHRMLGND

OUT_2

OUT_1

OUT_0

OC*EN*

IN_0

IN_1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Port Power Switch

514S0115

Place L5200, L5205 and L5206 across moat

Right USB Port

CRITICAL

165-OHMSM

4

32

1

L5200

FERR-250-OHM

SM

21

L5205

6.3V20%

B2POLY

100UF2

1C529610uF

CERM805-16.3V20%

2

1C5295

CERM20%

6.3V10uF

805-12

1C529010V20%

402CERM

0.1UF2

1 C5291

402

16VCERM

20%0.01uF

2

1C5205

0.01uF20%

402

16VCERM 2

1C5206

SM

FERR-250-OHM21

L5206

F-RT-SM-USB-RGT1UAR2X

CRITICAL

8

7

6

5

4

3

2

1

J5200

CRITICAL

RTUSB_ESD

SC-75

RCLAMP0502B

2 1

3

D5200

TPS2051

CRITICAL

MSOP

9

6

7

8

5

3

2

1

4

U5290

0

402MF-LF1/16W5%

21

R5292

402CERM-X5R6.3V20%

NO STUFF

0.47uF2

1 C5292

External USB ConnectorSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10452

PP5V_S3_RTUSB_F


=PP5V_S3_RTUSB

=RTUSB_EN

=USB2_RT_P

=USB2_RT_N

USB2_RT_F_PUSB2_RT_F_N

=GND_CHASSIS_RTUSB

VOLTAGE=0VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mmGND_RTUSB

MIN_NECK_WIDTH=0.5 mmVOLTAGE=5V

PP5V_S3_RTUSB_ILIMMIN_LINE_WIDTH=0.5 mm

RTUSB_OC_L_RC =RTUSB_OC_L

63

62

6

6

6

6

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

(500 mA)

(2 Amps)

NC NC

Place XW5510 at 5V switcher

(500 mA)

(2 Amps)



(Input from LIO)

Left I/O Board Connector

Place XW5515 at 5V switcherNC

516S0361

CRITICAL

F-ST-SMQT510806-L111-7F

9

84

8382

81

80

8

79787776757473727170

7

69686766656463626160

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J5500

SM21

XW5500

SM21

XW5505

SM21

XW5510

SM21

XW5515

55 104

A051-6941

Left I/O Board ConnectorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

SMC_EXCARD_PWR_EN

GND_AUDIO_PWRMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=5V

PP5V_S0_AUDIO_PWR

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmGND_AUDIO

VOLTAGE=0V

=PCIE_EXCARD_D2R_P

=PCIE_EXCARD_R2D_N

ACZ_RST_L

=PCIE_EXCARD_R2D_P

=PCIE_EXCARD_D2R_N

PCIE_CLK100M_EXCARD_NPCIE_CLK100M_EXCARD_P

=PP5V_S5_LIO

ACZ_BITCLK

=PCIE_MINI_D2R_P

=USB2_EXCARD_P

=PP1V5_S0_LIO=PP3V42_G3H_LIO=PPDCIN_G3H_LIO

LTUSB_OC_L

SMC_EXCARD_CP

LIO_P3V3S0_EN_L

SMC_BATT_ISET

=PP5V_S0_AUDIO_XW

SYS_ONEWIRESMC_ADAPTER_ENSMC_BATT_CHG_EN

EXCARD_CLKREQ_LMINI_CLKREQ_L

LIO_BATT_ISENSE

SMC_SYS_ISET

SMC_BC_ACOK

ACZ_SDATAOUT

ACZ_SDATAIN<0>ACZ_SYNC

PCIE_WAKE_L=SMBUS_LIO_SMC_SDA=SMBUS_LIO_SMC_SCL

=USB2_EXCARD_N

=SMBUS_LIO_SB_SCL

PCIE_CLK100M_MINI_NPCIE_CLK100M_MINI_P

=PCIE_MINI_D2R_N

=PCIE_MINI_R2D_N=PCIE_MINI_R2D_P

LIO_DCIN_ISENSE

SMC_BATT_TRICKLE_EN_L

EXCARD_OC_L

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmVOLTAGE=5V

PP5V_S0_AUDIO

LIO_P3V3S3_EN

LIO_PLT_RESET_L=USB2_LT_N=USB2_LT_P

=SMBUS_LIO_SB_SDA

48

79

79

48

48

47

48

48

79

79

79

37

48

48

47

46

46

21

46

46

34

34

63

21

46

6

63

63

63

6

47

62

47

47

41

47

34

34

51

47

47

21

21

21

23

27

27

6

27

34

34

46

46

46

51

47

6

62

26

6

6

27

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

63

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Place caps close to SB

Place caps close to SB

PCI-E x1 Port "A" = Ethernet (Yukon)

PCI-E x1 Port "B" = PCI-E Mini Card

PCI-E x1 Port "C" = ExpressCard

PCI-E x1 Port "D" = Unused

PCI-E x1 Port "E" = Unused

PCI-E x1 Port "F" = Unused

402X5R16V10%

0.1uF21

C5710

402X5R16V10%

0.1uF21

C5711

402X5R16V10%

0.1uF21

C5721402X5R16V10%

0.1uF21

C5720

57 104

A051-6941

PCI-E ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

TP_PCIE_F_D2RPMAKE_BASE=TRUETP_PCIE_F_D2RNMAKE_BASE=TRUE

MAKE_BASE=TRUETP_PCIE_F_R2DP

PCIE_F_D2R_P

PCIE_F_D2R_N

PCIE_F_R2D_C_N

TP_PCIE_E_D2RPMAKE_BASE=TRUETP_PCIE_E_D2RNMAKE_BASE=TRUE

MAKE_BASE=TRUETP_PCIE_E_R2DNMAKE_BASE=TRUETP_PCIE_E_R2DP

PCIE_E_D2R_P

PCIE_E_D2R_N

PCIE_E_R2D_C_N

PCIE_E_R2D_C_P

PCIE_D_R2D_C_P

PCIE_D_R2D_C_N

PCIE_D_D2R_N

PCIE_D_D2R_P

MAKE_BASE=TRUETP_PCIE_D_R2DP

MAKE_BASE=TRUETP_PCIE_D_R2DN

TP_PCIE_D_D2RNMAKE_BASE=TRUE

TP_PCIE_D_D2RPMAKE_BASE=TRUE

PCIE_C_D2R_P

PCIE_C_D2R_N

PCIE_C_R2D_C_N

PCIE_C_R2D_C_P

MAKE_BASE=TRUEPCIE_EXCARD_D2R_N

MAKE_BASE=TRUEPCIE_EXCARD_D2R_P

MAKE_BASE=TRUEPCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUEPCIE_EXCARD_R2D_C_P

=PCIE_EXCARD_D2R_N

=PCIE_EXCARD_D2R_P

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_R2D_P

MAKE_BASE=TRUEPCIE_MINI_R2D_C_P

MAKE_BASE=TRUEPCIE_MINI_D2R_P PCIE_B_D2R_P

MAKE_BASE=TRUEPCIE_MINI_D2R_N

PCIE_MINI_R2D_C_NMAKE_BASE=TRUE

PCIE_B_R2D_C_N

=PCIE_MINI_R2D_P

=PCIE_MINI_R2D_N

=PCIE_MINI_D2R_N

=PCIE_MINI_D2R_P

MAKE_BASE=TRUETP_PCIE_F_R2DN

PCIE_B_D2R_N

PCIE_B_R2D_C_P

PCIE_F_R2D_C_P

45

45

45

45

45

45

45

45

22

22

22

22

22

22

22

22

22

22

22

22

22

22

22

5

5

5

5

22

22

5

5

5

5

22

22

22

www.vinafix.vn

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

P16

P51P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12

P13P14

P15

P17

P31/LAD1P30/LAD0

P32/LAD2

P33/LAD3

P36/LCLKP37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45

P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26P25

P24

P23P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0*

P61/KIN1*P62/KIN2*

P63/KIN3*P64/KIN4*

P65/KIN5*

P66/IRQ6*/KIN6*P67/IRQ7*/KIN7*

P70/AN0

P71/AN1

P72/AN2P73/AN3

P74/AN4

P75/AN5

P84/IRQ3*/TXD1

P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2ACPA3/KIN11*/PS2AD

PA5/KIN13*/PS2BDPA4/KIN12*/PS2BC

PB2

PB3PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7PB6

PH4

PF5/PWM5

PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC

PA7/KIN15*/PS2CD

PD0/AN8PD1/AN9

PD2/AN10PD3/AN11

PD4/AN12

PD5/AN13PD6/AN14

PD7/AN15

PF0/IRQ8*/PWM2PF1/IRQ9*/PWM3

PB0/LSMI*PB1/LSCI

PC0/TIOCA0/WUE8*

PC1/TIOCB0/WUE9*PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12*PC5/TIOCB1/TCLKC/WUE13*

PC6/TIOCA2/WUE14*

PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK

PE2*/ETDIPE3*/ETDO

PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

VCC

VCC

AVCC

XTAL

EXTAL

AVCC

VCC

MD1

MD2

NMI

RES*

ETRST*

AVREF

AVSSVSS

(3 OF 4)

NC22NC21

NC20

NC19NC18

NC17NC16

NC15

NC14NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5NC4

NC3

NC2NC1

NC0

(4 OF 4)

OUT

OUT

IO

OUT

IN

IN

IN

OUT

IN

IO

IN

IO

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

ININ

OUT

OUT

IO

IO

IO

IO

IN

IN

IN

OUT

OUT

OUT

IO

IN

IN

IN

IN

IO

IO

IN

IN

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SMC_XXX WHERE XXX IS THE PORT NUMBER.

CAN BE LEFT NO-CONNECTED.

UNUSED PINS HAVE THE FORMAT

LAYOUT NOTE:

SMC

PLACE R5899 AND C5820 NEAR SMC PIN N14,N15VCL IS INTERNAL RAIL

PLACE C5807 NEAR PIN F1LAYOUT NOTE:

DRIVEN OUTPUTS ALWAYS SO THEYTHEY ARE SET BY SOFTWARE TO BE

805

20%6.3VX5R

22UF2

1C5802

402

0.47UF20%6.3VCERM-X5R2

1C5807

10V0.1UF20%CERM402

2

1 C5803

0.1UF20%CERM10V402

2

1C58205%

1/16W

4.7

402MF-LF

21R5899

0.1UF20%10VCERM402

2

1 C5804

SM21

XW5800

40210V20%0.1UFCERM2

1 C580520%10VCERM402

0.1UF2

1C5806BGA

OMIT

SMC_H8S2116

G2H1H2J4J3J1J2K4

B6A6C6D6B7A7C7

P15N13R15P14R14P13R13N12

J13J12K14K13K12L15L14L13

F2G4G1

C1D3C2B1C3D5B5A5

D7A8C8D8B9A9C9D9

F14E13E15E14E12D15D14D13

C15D12C14B15B14A15C13B12 U5800

OMIT

SMC_H8S2116BGA

B3D4C4K2F3E1

R7P7M8R8P8N9R9P9

N5P5R5M6N6R6P6M7

L2L4M1M2M3

M10N10R10P10N11R11P11M11

H12H13H15H14G12G13G15G14

D11A12C11B11A11D10A10B10

N1M4N2R1N3R2P3R3 U5800

BGASMC_H8S2116

OMIT

A2

D2B4A4

A13

B13

F13

F12R4P4D1

F1

A1J15

P1

P2

E3

F4

K1E2

B2

L1

R12P12

M15

M14

N15

N14

U5800

BGASMC_H8S2116

OMIT

L12M13M12N7M5N4L3

N8M9H4

K3

E4B8A3C5C10C12A14F15

J14K15

H3G3

U5800

MF-LF5%4021/16W10K2

1R5809MF-LF4025%10K1/16W2

1R5801

1/16W5%10KMF-LF4022

1R5802NOSTUFF

402MF-LF1/16W5%02

1R580310KMF-LF5%1/16W4022

1R5898

051-6941 A

58 104

SMC_TX_L

SMC_SYS_LEDSMC_SYS_KBDLED

SMB_B_S0_CLKSMB_B_S0_DATASMB_A_S3_CLKSMB_A_S3_DATASMB_BSA_CLKSMB_BSA_DATA

SMB_0_S0_CLK

SMC_RSTGATE_LPM_LAN_ENABLE

ALL_SYS_PWRGDRSMRST_PWRGDSMC_SB_NMIPM_RSMRST_LIMVP_VR_ONPM_PWRBTN_L

SMC_WAKE_SCI_L

SMB_BSB_CLKSMC_ONOFF_L

SC_RX_LSC_TX_LPM_SUS_STAT_LPM_CLKRUN_LSMC_TPM_GPIO

INT_SERIRQPCI_CLK_SMCSMC_LRESET_LLPC_FRAME_LLPC_AD<3>LPC_AD<2>LPC_AD<1>LPC_AD<0>SMC_P27

SMC_RCIN_LBOOT_LPC_SPI_L

SMC_TPM_RESET_LPM_EXTTS_LPM_THRM_LSYS_ONEWIREPM_BATLOW_L

SMC_FAN_0_TACHSMC_FAN_1_TACHSMC_FAN_2_TACH

SMC_FAN_3_CTL

SMC_TPM_PPSMB_BSB_DATA

SMC_XDP_TMS

SMC_XDP_TCK

SMC_RX_L

SMC_EXTSMI_L

ISENSE_CAL_EN

SMC_EXCARD_PWR_EN

SMC_FWIRE_ISENSESMC_BATT_ISENSESMC_PBUS_VSENSE

SMC_GPU_VSENSE

SMC_PROCHOT_3_3_LSPI_SO

SPI_SCLK

SMC_SUS_CLK

PM_SYSRST_L

SMC_XDP_TRST_L

SMC_THRMTRIP

ALS_GAIN

SMC_RST_LPM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L

=PP3V3_S5_SMC

SMC_VCL

SMC_EXCARD_CP

SMC_DCIN_ISENSE

SMC_GPU_ISENSE

SMC_CPU_RESET_3_3_L

SMC_XDP_TCK_3_3SPI_CE_L

SMC_PF0

SMC_ADAPTER_EN

SMC_CPU_VSENSE

SMB_0_S0_DATA

SMC_RUNTIME_SCI_LSMC_ODD_DETECT SMC_BATT_VSET

SMC_SYS_ISET

SMC_TMSSMC_TDOSMC_TDISMC_TCKSMC_CASE_OPEN

SMC_P26SMC_BATT_CHG_EN

SMC_P20


SMC_P21

SMC_FAN_0_CTLSMC_FAN_1_CTL

SMC_FAN_3_TACH

SMS_Y_AXIS

ALS_RIGHT

SMC_FWE

SMC_BC_ACOK

SMC_P23

SMC_CPU_INIT_3_3_L

=PP3V3_S5_SMC

GND_SMC_AVSS

SMC_SYS_LED_16B

SMC_XDP_TDO_3_3

SPI_ARB

GND_SMC_AVSS

SMC_NMI

SMC_TRST_L

SMC_PROCHOT

PP3V3_AVREF_SMC

SMC_MD1

ALS_LEFT

KBC_MDE

=PP3V3_S5_SMCPP3V3_AVCC_SMC

MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM

SMC_EXTALSMC_XTAL

SMC_P22

SMC_PM_G2_EN

SMC_EXCARD_OC_L

SMC_FAN_2_CTL

SPI_SI

SMC_CPU_ISENSE

SMS_INT_L

SMC_BS_ALRT_L

SMC_MEM_ISENSESMC_NB_ISENSESMC_ANALOG_IDSMS_Z_AXIS

SMS_X_AXIS

SMS_ONOFF_L

SMC_PF1SMC_LID

SMC_BATT_ISET

SMC_SYS_VSET

56

56

51

49

49

56

56

56

56

56

56

48

53

53

49

48

48

40

49

49

49

49

49

49

49

48

49

26

76

49 62

62

63

48

45

49

49

49

49

48

48

48

63

51

51

63

64

48

62

43

23

23

23

21

21

21

21

21

22

56

48

45

48

51

45

52

52

23

6

48 41

39

48

48

45

52

41

45

48

48

48

48

45

45

45

48

48

48

49

48

52

48

48

48

45

5

48

53

27

27

27

27

27

27

27

6

23

26

48

23

23

57

23

23

27

5

48

48

5

5

48

5

34

26

5

5

5

5

5

48

21

5

48

14

23

5

23

54

54

48

48

48

27

48

48

5

23

5

5

51

51

51

51

48

22

22

35

5

48

48

5

5 23

23

23

47

5

51

51

48

48

22

48

5

51

27

23

36 48

5

5

5

5

5

48

48

5

48

5

48

54

54

48

55

53

48

5

48

48

47

47

48

48

22

47

48

48

5

53

47

48

48

48

62

48

48

22

51

23

5

48

48

48

55

55

55

48

43

5

48

www.vinafix.vn

G

D

S

G

D

S

IN OUT

GND

IN OUT

V-

V+

V-

V+OUT

NCCD

GND

OUT

VDD

OUT

OUT

G

D

SIN

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Reports when 5V S5 and 3.3V S5 are in regulation

SMC PWRGD Circuit

SMC Crystal Circuit

5V Comp threshold set to 4.480V (89.6%)

ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)

SMC AVREF Supply

SMC 3.3V to 1.05V Level ShiftingDebug Power Button

Silk: "PWR BTN"

1.71V Reference

NOTE: R5965 acts as 10K pull-up for PGOOD signal

System (Sleep) LED Circuit

NC

SMC Reset Button / Brownout Detect

Silk: "SMC RST"

1.05V Mid-Reference

SMC 1.05V to 3.3V Level Shifting

10V20%

402CERM

0.1uF2

1C5900

402MF-LF5%

0

SMC_TPM_GPIO1

1/16W

21

R5990

402MF-LF1/16W5%

SMC_TPM_GPIO2

0 21

R5991

SOT-3632N7002DW-X-F

1

2

6

Q5995

SOT-3632N7002DW-X-F

4

5

3

Q5995

5%

0

MF-LF1/16W402

21

R5992

402

5%

0

MF-LF1/16W

21

R5993

10V20%

402CERM

0.1uF2

1C5977

1/16W5%

402MF-LF

1K

2

1R5971

MF-LF1/16W

6.2K

402

5%

2

1R5970

402CERM-X5R20%6.3V0.47uF

2

1 C5965 402CERM16V20%0.01uF

2

1 C5967

603

10uF

X5R20%

6.3V 2

1C5966

CRITICAL

REF3133SOT23-3

21

3

VR5965

CERM402

20%10V

0.1uF2

1C5960

1/16W1%

402MF-LF

10K

2

1R5961

10K1/16W

1%

402MF-LF

2

1R5962 1/16W

10K

MF-LF402

5%

2

1R5965

SM-LFLMC7211

2

5

1

3

4U5977

LMC7211SM-LF

2

5

1

3

4U5960

402MF-LF5%

1/16W

0 21

R5994

0

402

5%

SMC_TPM_PP

MF-LF1/16W

21

R5995

10K1/16W5% MF-LF 402

21R5931

MF-LF5% 1/16W10K

40221R5932

1/16W5% MF-LF 402100K 21R5933

402MF-LF5% 1/16W10K 21R593410K

1/16W5% MF-LF 40221R5935

1/16W 402MF-LF5%100K 21R5936

1/16W5% MF-LF 4022.0K

ONEWIRE_PU21R5937

100K1/16W5% MF-LF 402

21R593810K

1/16W5% MF-LF 40221R5939

MF-LF 4025% 1/16W10K 21R5940

MF-LF1/16W5% 40210K 21R5941

MF-LF 4025% 1/16W10K 21R5942

402MF-LF5% 1/16W10K 21R5943

402MF-LF5% 1/16W10K 21R594410K

1/16W5% MF-LF 40221R5945

10K402MF-LF5% 1/16W

21R59461/16W5% MF-LF 402

470K 21R5947402MF-LF5% 1/16W

10K 21R5948

10K1/16W5% MF-LF 402

21R5930

CRITICAL

5X3.2-SM20.00MHZ

2

1Y5920

CRITICAL

RN5VD30A-FSOT23-5

2

1

4

3

5

U5900

MF-LF402

1%1/16W

10K

2

1R5964

1/16W1%

402MF-LF

16.2K

2

1R5963

50V10%0.0022uF

402CERM2

1 C5969

10K1/16W5% MF-LF 402

21R5980402MF-LF1/16W

10K5%

21R5981402MF-LF5%

10K1/16W

21R5982

100K1/16W5% MF-LF 402

21R5983100K

1/16W5% MF-LF 40221R5984

1K

MF-LF402

5%1/16W

2

1R5900

1/10W5%

603MF-LF

0

OMIT

2

1R5901

1/10W

0

OMIT

5%

603MF-LF

2

1R5910

SOT23-LF2N7002

2

1

3

Q5952

SOT23-LF2N3906

2

3

1 Q5950

1/16W5%

402MF-LF

100

2

1R59501/16W

5%

402MF-LF

2.2K

2

1R5951

1/16W5%

402MF-LF

4.7K

2

1R5952

50V5%

402CERM

15pF21

C5920

5%50VCERM402

15pF21

C5921

402

0.01UF16V10%

CERM 2

1C5901

SMC Support

104

A051-6941

59


SMC_TX_L

TPM_GPIO1

SMC_RX_L

TPM_PP

SC_RX_L

SMC_TPM_PP

SMC_EXCARD_OC_L

SC_TX_L

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L

=PP3V3_S0_SMC_LS

P0V46_SMC_LSREFVOLTAGE=0.46V

SMC_PF1 TP_SMC_PF1MAKE_BASE=TRUE

SMC_PF0MAKE_BASE=TRUETP_SMC_PF0

SMC_P27MAKE_BASE=TRUETP_SMC_P27




SMC_P21 TP_SMC_P21MAKE_BASE=TRUE

SMC_P20 TP_SMC_P20MAKE_BASE=TRUE

SMC_XDP_TRST_L TP_SMC_XDP_TRST_LMAKE_BASE=TRUE

SMC_XDP_TDO_LMAKE_BASE=TRUETP_SMC_XDP_TDO_L

SMC_XDP_TMS TP_SMC_XDP_TMSMAKE_BASE=TRUE

SMC_XDP_TCK TP_SMC_XDP_TCKMAKE_BASE=TRUE

SMC_FAN_3_CTL TP_SMC_FAN_3_CTLMAKE_BASE=TRUE

SMC_FAN_3_TACHMAKE_BASE=TRUETP_SMC_FAN_3_TACH

SMC_FAN_2_TACHMAKE_BASE=TRUETP_SMC_FAN_2_TACH

SMC_FAN_2_CTLMAKE_BASE=TRUETP_SMC_FAN_2_CTL

SMC_SYS_VSET TP_SMC_SYS_VSETMAKE_BASE=TRUE

SMC_BATT_VSET TP_SMC_BATT_VSETMAKE_BASE=TRUE

SMC_SYS_LED TP_SMC_SYS_LEDMAKE_BASE=TRUE

SMC_ANALOG_IDMAKE_BASE=TRUETP_SMC_ANALOG_ID

SMC_MEM_ISENSEMAKE_BASE=TRUESMC_P1V8S3_ISENSE

PM_EXTTS_LMAKE_BASE=TRUE

DIMM_OVERTEMP_L

SMC_NB_ISENSEMAKE_BASE=TRUESMC_P1V05S0_ISENSE

SMC_CPU_INIT_3_3_L FWH_INIT_LMAKE_BASE=TRUE

SMC_RST_LSMC_MANUAL_RST_L

=PP3V3_S5_SMC

SMC_SYS_LED_16B

SYS_LED_L_VDIV

SYS_LED_ANODE

SYS_LED_L

=PP5V_S3_SYSLED

SYS_LED_ILIM

=P3V3S5_PGOOD

P5VS5_COMP_POS

P1V71_SMC_REF

P5VS5_PGOOD

RSMRST_PWRGDMAKE_BASE=TRUE

=PP3V42_G3H_SMC_PWRGDPP5V_S5

SMC_ONOFF_L

SMC_THRMTRIP

SMC_PROCHOT

PM_THRMTRIP_L

CPU_PROCHOT_L

=PP3V42_G3H_SMCVREF

VOLTAGE=3.3VMIN_LINE_WIDTH=0.4 mmPP3V3_AVREF_SMCMIN_NECK_WIDTH=0.2 mm


SMC_EXCARD_CPPM_SUS_STAT_LPM_SLP_S5_L

EXCARD_OC_L

VOLTAGE=0VMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

GND_SMC_AVSS

SMC_BC_ACOKSMC_CASE_OPENSMC_ADAPTER_ENSMC_BATT_CHG_EN

SMC_XDP_TDO_3_3

SMC_CPU_RESET_3_3_LSMC_TCK

SMC_XDP_TCK_3_3

SMC_TDISMC_TDO

SMC_BS_ALRT_LSMC_TMS

SMC_XTAL

SMC_EXTAL

SYS_ONEWIRE

=PP3V3_S3_TPM=PP3V3_S3_SMS

=PP3V3_S5_SMC

SMC_RX_LSMC_TX_LSMC_FWE

SMC_ONOFF_LSMC_LID

SMC_TPM_RESET_LSMS_INT_L

SMC_TPM_GPIO

TPM_GPIO2

51

56

51 49

49

48

49

47

49

49

48 48

48

49

63

47

21

47

47

47

45

53

47

45

47

49

49

49

64

49

47

63

48

48

47 47

47

48

47 29

21

48

61

43

14

48

45

45

23

47

6

51

45

41

45

47

47

47

47

47

45

63

63

48

47

47

43

47

56

47

5

56

5

56

47

47

47

47

47

7

63

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47 51

14 28

47 51

5

47

47

76

63

62

47

63

63

5

47

47

7

7

63 47

5

5

5

23

5

47

5

47

5

5

47

47

5

47

5

5

5

5

47

47

5

56

55

47

5

5

47

5

43

47

23

47

56

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DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC NC

NC

516S0384NC

(GPIO15)

QT500306-L021-9FM-ST-SM

LPCPLUSCRITICAL

9

8 7

6 5

4

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J6000

LPC+ Debug ConnectorSYNC_DATE=07/20/2005SYNC_MASTER=M42

051-6941 A

10460

SMC_TX_LSMC_MD1SMC_TDOSMC_TRST_LDEBUG_RST_LSMC_TMS

PM_CLKRUN_LLPC_FRAME_L

BOOT_LPC_SPI_L

LPC_AD<1>LPC_AD<0>

SV_SET_UP

SMC_RX_LSMC_NMISMC_RST_LSMC_TCKSMC_TDIPM_SUS_STAT_LINT_SERIRQ

LPC_AD<3>LPC_AD<2>

PCI_CLK_PORT80_LPCFWH_INIT_L

=PP5V_S0_LPCPLUS=PP3V3_S5_LPCPLUS

56

56

47

56

56

56

48

56

56

56

48

48

48

40

47

47

47

47

48

48

48

48

47

47

47

47

48

47

47

47

47

26

47

23

21

22

21

21

23

47

47

47

47

47

23

23

21

21

34

21

63

63

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

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SMBDATASMBCLK

ALERT*

OT2*

DXP2

OT1*

DXNDXP1

GND

VCC

IO

IO

D+D-

ALERT*/

THM*

SCLKSDATA

VDD

GND

THM2*

SYM_1

SYM_1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE


Placement note:Keep all 4 XWs as closeto U6100 as possible

R1001 / R1002 are not currently BOMOPTIONed. Can not

CPU Back-Up Thermal Diode

Place near CPU centerPlacement note:

programatically unstuff those parts to stuff these.

Layout note:Minimize stubs betweenthese R’s and R1001 & R1002

NCNC

NC

left of the speaker hole.

GPU / Heat Pipe Thermal Sensor

Placement note:Place U6150 below and to the

Layout note:Minimize stubs

Place near GPU centerPlacement note:

NC

NC

518S0226

Place in between VRAMPlacement note:

NC

NC

518S0226

Placement note:Place near speaker hole

Right-Side/Fin Stack Thermal Sensor

UMAXMAX6695AUB

CRITICAL

1

97

105

6

4

23

8

U6100

HSTHMSNS_HAS

402CERM50V10%

0.0022uF2

1C6120

SM21

XW6120

SM21

XW6121

SM21

XW6111

GPUTHM_A_GPU

402MF-LF1/16W5%0

2

1R6110GPUTHM_A_GPU

402MF-LF1/16W

5%0

2

1R6111

1/16W

GPUTHM_A_DIODE

MF-LF

5%

402

021

R6115

0

5%1/16WMF-LF402

GPUTHM_A_DIODE

21

R6116SOT23

2N3904LF2

3

1Q6115

SM21

XW6110

5%1/16WMF-LF402

0

CPUTHM_DIODE

21

R6190

CPUTHM_DIODE

402

0

5%1/16WMF-LF

21

R6191SOT23

2N3904LF2

3

1Q6190

10K

MF-LF402

5%1/16W

2

1R61521/16W

5%

402MF-LF

10K

2

1R6151

MSOPADT7461

CRITICAL

1

4

78

5

32

6

U6150

0.1UF

X5R402

10%16V 2

1C6150

0.001UF

CERM402

20%50V2

1 C61601%

499

402MF-LF1/16W

21

R6160

1%

499

MF-LF402

1/16W

21

R6161

10V20%

402CERM

0.1uF2

1 C6100

CRITICAL

88460-0201F-RT-SM

2

1

4

3

J6120

88460-0201F-RT-SM

CRITICAL

2

1

4

3

J6160

1/16W5%

402MF-LF

47 21

R6100

50V0.0022uF

CERM402

10%2

1C6110

Thermal Sensors

61 104

A051-6941


116S0004 1 RES,0,1/16W,0402 C6120 HSTHMSNS_NOT

RSFSTHMSNS_D_R_NRSFSTHMSNS_D_R_P

RSFSTHMSNS_D_N

RSFSTHMSNS_D_P

HSTHMSNS_DX_N

GPUTHMSNS_DX_A_DIO_N

GPUTHMSNS_DX_A_DIO_P GPUTHMSNS_DX_A_P

ATI_TDIODE_PATI_TDIODE_N

HSTHMSNS_DX_P

=PP3V3_S0_GPUTHMSNS

=SMBUS_RSTHMSNS_SDA=SMBUS_RSTHMSNS_SCL

RSTHMSNS_ALERT_L

RSTHMSNS_THM_L

=PP3V3_S0_RSTHMSNS

=SMBUS_GPUTHMSNS_SCL=SMBUS_GPUTHMSNS_SDA

GPUTHMSNS_DXN

PP3V3_S0_GPUTHMSNS_R

GPUTHMSNS_DXP2

GPUTHMSNS_DXP1

CPUTHMSNS_DIO_P THRM_CPU_DX_P

THRM_CPU_DX_NCPUTHMSNS_DIO_N

GPUTHMSNS_DX_A_N

5

5

5

72

72

5

63

27

27

63

27

27

10

10

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IN

OUT

G

S DD S

G

N-CHN

S

D

G

P-CHN

G

DS

N-CHN

S

D

G

P-CHN

G

DS

OUT

OUTIN OUTIN

OUTIN IN OUT

OUTINOUTIN

OUTIN

OUT

GD

S

GD

S

GD

S

GD

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

R5808 is pull-up

This half of Q6216 actsas a level-shifterbetween PBUS and 3.42V

pressed or driven low by SMC)

GPU Voltage Sense / Filter

DCIN Current Sense Filter

pulling SMC_ONOFF_L low.diode to keep Q6215 fromThis half of Q6216 acts as a

CPU Current Sense Filter

Place short near U8400 center

Current Sense Calibration Circuit

Place RC close to SMC

Battery Current Sense Filter


GPU Current Sense Filter

FireWire Current Sense Filter

1.05A / 1.1W1.2A / 1.44W



1.05V S0 (NB) Current Sense Filter

Place RC close to SMCPlace RC close to SMC

Place RC close to SMCPlace RC close to SMC

CPU Voltage Sense / Filter

1.0A / 1.8W

Place short near U0700 center

Switches in fixed load on power supplies to calibrate current sense circuits

1.8V S3 (Memory) Current Sense Filter

Enables PBUS VSense divider when high.

Enables PBUS VSense divider whenSMC_ONOFF_L is low (power button


PBUS Voltage Sense Enable & Filter

Rthevanin = 4573 ohms


470K5%1/16WMF-LF4022

1R6228

402MF-LF1/16W

5%100K

2

1R6227

1%1/16WMF-LF

402

100K

2

1R621527.4K

1%1/16WMF-LF

4022

1R6285

6.3V

0.22UF

402X5R

20%2

1 C62855.49K

402MF-LF1/16W

1%

2

1R6286

2N7002DW-X-FSOT-363

4

5

3

Q6216

2N7002DW-X-FSOT-363

1

2

6

Q6216

FDG6332C_NLSC70-6

1

2

6

Q6229

FDG6332C_NLSC70-6

4

5

3

Q6229

FDG6332C_NLSC70-6

1

2

6

Q6215

FDG6332C_NLSC70-6

4

5

3

Q6215

0.22UF20%6.3VX5R402

2

1 C62591%

1/16WMF-LF402

4.53K21

R6259

1/16W

4.53K

402MF-LF

1%

21

R6270

6.3V

0.22UF

402X5R

20%2

1 C627020%

X5R402

0.22UF6.3V2

1 C62751%

1/16WMF-LF402

4.53K21

R6275

6.3V

0.22UF

402X5R

20%2

1 C6280

4.53K

402MF-LF1/16W1%

21

R6280

1%1/16WMF-LF402

4.53K21

R6290

20%

X5R402

0.22UF6.3V2

1 C6290

20%

X5R402

0.22UF6.3V2

1 C62401%

1/16WMF-LF402

4.53K21

R6240

6.3V

0.22UF

402X5R

20%2

1 C6235

4.53K

402MF-LF

1%1/16W

21

R6235

20%

X5R402

0.22UF6.3V2

1 C62301%

1/16WMF-LF402

4.53K21

R6230

SM21

XW6259

4.53K

402MF-LF1/16W1%

21

R6209

402X5R6.3V20%0.22UF

2

1 C6209

SM21

XW6209

1206MF-LF1/4W

1%1.00

2

1R6220

470K5%

1/16WMF-LF

4022

1R6229

CRITICAL

FDC796NSUPERSOT-6

65321

4

7

Q6220

1206MF-LF1/4W

1%1.00

2

1R6221

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q6221

1.821%

1/4WMF-LF12062

1R6222

FDC796N

CRITICAL

SUPERSOT-6

65321

4

7

Q6222

1.001%

1/4WMF-LF12062

1R6223

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q6223 Current & Voltage Sensing

62 104

A051-6941


GND_SMC_AVSS

SMC_PBUS_VSENSE

VOLTAGE=12.6VPPBUS_G3H_VSENSE

PBUSVSENS_EN_L

PPBUS_G3H

=PBUSVSENS_EN

ISENSE_CAL_EN

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN_L

ISENSE_CAL_EN_LS5V

GND_SMC_AVSS

=PP1V8_S3_REG

P1V8S3_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

LIO_DCIN_ISENSE

GND_SMC_AVSS

=PPVCORE_S0_CPU

FWPWR_IOUT SMC_DCIN_ISENSE

GND_SMC_AVSS

LIO_BATT_ISENSE SMC_BATT_ISENSE

GND_SMC_AVSS

CPUVCORE_IOUT SMC_CPU_ISENSE GPUVCORE_IOUT SMC_GPU_ISENSE P1V8S3_IOUT SMC_P1V8S3_ISENSE SMC_P1V05S0_ISENSE

GND_SMC_AVSS GND_SMC_AVSS GND_SMC_AVSS

GPUVSENSE_IN

CPUVSENSE_IN

SMC_GPU_VSENSE

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_GPU

GND_SMC_AVSS

=PPVCORE_S0_CPU

GPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

=PPVCORE_S0_GPU

P1V05S0_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

=PP1V05_S0_REG

CPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

P1V05S0_IOUT

SMC_FWIRE_ISENSE

PBUSVSENS_PWRBTN_LSMC_ONOFF_L

=PP3V42_G3H_PBUSVSENS

53

53

53

63

53 53

53 53 53

53

72

53

63 72

48

51

51

63

51

51

51 51

51 51 51

51

67

51

51 67 63

47

48

47

63

48

60

45

48

9

48

45

48

48 48 48

48

63

48

9 63 61

43

47

47

63

62

5

5

47

5

5

47

8

41 47

47

5 47

47

57 47 66 47 60 48 48

47 47 47

47

47

47

51

47

8 51 5

61

47

5

63

www.vinafix.vn

SCK

SOWP*

SI

VDD

CE*

HOLD*VSS

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH ICH7M AND TEKOA(LAN CHIP)

R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M

402CERM10V20%0.1UF2

1 C6312

1/16W402

5%MF-LF

3.3K

2

1R6301

402

3.3K5%1/16WMF-LF2

1R6302

22pF

402CERM5%50V2

1C6301

MF-LF402

5%1/16W

47 21R6307

402

22pF50V5%CERM2

1C63085%CERM50V402

22pF2

1C6309 402MF-LF

475%1/16W

21R6303

47

1/16WMF-LF5%

402

21R6306

22pF

402CERM5%50V2

1C6311

OMITCRITICAL

16MBIT

SST25VF016B

SOI

3

4

8

2

56

7

1

U6301 402

5%10K1/16WMF-LF

21

R6308

NOSTUFF

10K5%1/16WMF-LF402

21

R6309

63

SPI BOOTROM

051-6941 A

104

SYNC_MASTER=M42SYNC_DATE=11/16/2005

SPI_WP_LSPI_HOLD_L

SPI_CE_L SPI_SO

SPI_SISPI_SCLK_RSPI_SCLK SPI_SI_R

SPI_SO_R

=PP3V3_S5_ROM

47 47

47 47

22 22

22 22

63

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V+

V-

G

D

SIN

OUT

NC

CNTRL

THRML_PAD

VDD SW

AGNDPGND

FB

VOUT

ININ

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

RTALS_OP_IN and RTALS_OP_COMP need to be matched

Right ALS Circuit

NC

NC

Keyboard LED Driver

Left ALS Filter

Left ALS circuit has 1K series-R

MAX4236EUTTSOT23-6-LF

CRITICAL

2

6

5

1

4

3

U6405

CERM402

20%10V

0.1UF2

1C6405

120K

MF-LF402

5%1/16W

2

1R64060.22UF

X5R402

20%6.3V 2

1C6406

15.0K

MF-LF402

1%1/16W

2

1R64071K

MF-LF402

1%1/16W

2

1R6408

MF-LF402

1%1/16W

1K 21

R6401

BS520EOFTH

CRITICAL

2

1

PD64005.1M

MF-LF402

5%1/16W

2

1R64000.01UF

CERM20%16V402

2

1 C6400

2N7002SOT23-LF

2

1

3

Q6408

4.53K

MF-LF402

1%1/16W

21

R6410

0.22UF

X5R20%6.3V402

2

1 C6410

MM3120LLP

CRITICAL

8

1

9

7

5

6 4

3

2

U6450

22uH

3.8x3.8x1.5MM

CRITICAL

21

L6450

1uF

CERM402

10%6.3V 2

1C6450KBDLED_NOT

10K

MF-LF402

5%1/16W

2

1R6451

MF-LF5%

1/16W

KBDLED_HAS

10K

4022

1R64520.22uF20%25VX5R603

2

1 C6455 25.5

805

1%1/8WMF-LF

2

1R6455

6.3V20%

402X5R

0.22UF2

1 C64301/16W1%

402MF-LF

3.48K21

R6430

ALS Support

64 104

051-6941 A


ALS_LEFTLTALS_OUT

GND_SMC_AVSS

=PP5V_S0_KBDLEDKBDLED_SW

KBDLED_ANODE

KBDLED_RETURN

=PP3V3_S0_KBDLED

SMC_SYS_KBDLED

RTALS_GAIN_L

RTALS_PHOTODIODE RTALS_OP_IN

GND_SMC_AVSS

ALS_RIGHTALS_RT_OUT

=PP3V3_S3_RTALS

RTALS_OP_COMP

=RTALS_GAIN

53

53

51

51

76

48

48

47 5

47

63

43

43

63

47

47

47

63

6

www.vinafix.vn

G

S D

G

S D

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Right Fan

NC

NC

NC

NC

518S0293 518S0293

Left Fan

1/16W

47K

402MF-LF

5%

2

1R6550

5%1/16WMF-LF402

47K21

R6555 402MF-LF1/16W

5%47K

2

1R6560

47K

402MF-LF1/16W5%

21

R6565

402MF-LF

5%1/16W

100K

2

1R6551

CRITICAL

SM-2MT-LF

4321

6

5

J6550SM-2MT-LF

CRITICAL

4321

6

5

J6560

2N7002DW-X-FSOT-363

4

5

3

Q6560100K1/16W

5%

MF-LF4022

1R6561

SOT-3632N7002DW-X-F

1

2

6

Q6560

Fan Connectors

A051-6941

10465


=PP5V_S0_FAN_RT=PP3V3_S0_FAN_RT

SMC_FAN_1_TACH

FAN_RT_PWMSMC_FAN_1_CTLFAN_LT_PWM

=PP3V3_S0_FAN_LT

SMC_FAN_0_CTL

SMC_FAN_0_TACH

=PP5V_S0_FAN_LT

FAN_LT_TACH FAN_RT_TACH

63 63

63

47

5 47 5

63

47

47

5

5 5

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OUTPUTY

OUTPUTZ

DNCRSVD

TESTSELF

PS

PARITY

RSVDRSVD

RSVD

GND PADTHRML

OUTPUTX

VDD

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

+X

+Z (up)

+Y1

Package Top Top-through View

+Y

+Z (dn)

+X

Desired orientation whenDesired orientation when

1

placed on board top-side: placed on board bottom-side:

M1 placement: Bottom-side

0.1uF

CERM402

20%10V2

1 C6620

QFNKXM52-2050

CRITICAL

8

15

10

11764

9

5 14

13

2

123

1

U6620

4021/16W5%MF-LF

10K

1

2R6621

10K

MF-LF402

5%1/16W

2

1R6620

0.033UF

X7R402

20%10V2

1 C660510V20%

402X7R

0.033UF2

1 C660610V20%

402X7R

0.033UF2

1 C6604

66 104

A051-6941

Sudden Motion Sensor (SMS)SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

SMS_ACC_SELFTEST

SMS_ONOFF_L SMS_Y_AXIS

SMS_X_AXIS

=PP3V3_S3_SMS

SMS_Z_AXIS

63

47 47

47

48

47

www.vinafix.vn

IN

IO

IO

IO LAD1

LAD2

LCLK

LFRAME*

LRESET*LPCPD*

SERRIRQ

LAD0

CLKRUN/GPIO*

PP/GPIO

GPIO_EXPRESS_00

GPIO/SM_DATGPIO/SM_CLK

XTALI/32K_IN

TESTBI/BADD/GPIO

TESTI

3V0

3V1

3V2

3VSB

VNC

VBAT

XTALO

GND2

GND3

GND0

GND1

LAD3

IO

IO

IN

IN

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(INT PD)

GND

NC

NC

VSB

VDDVDDVDD

NC

PPGPIO

CLKRUN*

NC

NC

NC

BASE ADDR = 0X2E/2F

LAYOUT NOTE:PLACE WHERE ACCESSIBLE

LAYOUT NOTE:PLACE R6702-03 WHERE ACCESSIBLE

NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC,1/8W (R6704/R6705) IS USED FOR NOW

TESTBI/BADDGPIO2

BASE ADDR = 0X4E/4F

402X5R16V10%0.1UF

2

1C67000.1UF

402X5R16V10%

2

1C67010.1UF10%16VX5R402

2

1 C6702

0.1UF10%16VX5R402

2

1C6703NOSTUFF

05%1/16WMF-LF4022

1R6700

OMIT

TSSOPTPM

1413

3

12

89

27

7

1628

2221

17202326

612

2518114

15

5

241910U6700

MF-LF1/16W5%10K

4022

1 R6702

NOSTUFF

5%1/16WMF-LF

10K

4022

1 R6703

805MF-LF1/8W5%

0 21R6704

NOSTUFF

805MF-LF1/8W5%0

2

1R6705

05%

MF-LF1/16W402

21R6798

MF-LF5%

0

NOSTUFF

1/16W402

21R6799

TPMSYNC_DATE=11/16/2005SYNC_MASTER=M38

051-6941 A

67 104

MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.3VPP3V3_TPM_3VSB

TPM_PPTPM_GPIO1

TPM_GPIO2

LPC_AD<3>

=PP3V3_S0_TPM

=PP3V3_S3_TPM

PM_CLKRUN_L

TPM_XTALITPM_XTALO

=PP3V3_S0_TPM

INT_SERIRQPM_SUS_STAT_L

LPC_FRAME_LPCI_CLK_TPM

LPC_AD<2>LPC_AD<1>LPC_AD<0>

TPM_BADD

TPM_RST_L

TPM_LRESET_L

SMC_TPM_RESET_L

49

49

49

47

49

48

49

49

49

49

47

40

47

47

47

47

47

47

21

63

63

23

63

23

23

21

21

21

21

48

48

48

48

5

56

48

5

35

35

56

5

5

5

34

5

5

5

26

47

www.vinafix.vn

TPADVSS

BOOT2

BOOT1

PHASE1

UGATE1

LGATE1

PGND1

ISEN1

UGATE2

PHASE2

LGATE2

PVCCVDDVIN

PGND2

VID6

VID5

VID4

VID2

VID3

VID1

VID0

ISEN2

VSUM

OCSET

VO

DROOP

DFB

VSEN

RTN

DPRSTP*

DPRSLPVR

PSI*

PGD_IN

3V3

CLK_EN*

PGOOD

VR_ON

NTC

VR_TT*

SOFT

RBIAS

VDIFF

FB2

FB

COMP

VW

NC

IN

IN

IN

IN

OUT

IN

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1 0 1 1-Phase DCM

0 1 0 1-Phase CCM

DPRSLPVR DPRSTP* PSI* Operation Mode

(GND)

(IMVP6_COMP)

(GND_IMVP6_SGND)

(GND_IMVP6_SGND)

(GND)

(IMVP6_VW)

These caps for Q7550

(Inductors limit)

Vout = Variable36A max output

These caps for Q7500

(IMVP6_PHASE2)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

<Rb>

(IMVP6_ISEN2)

<Ra>

(IMVP6_VSUM)

(IMVP6_VO)

<Rc>Voffset = (Vdrp_offset * Kdroop) + Vamp_offset

Voffset worst-case ~2.3mV (+/- ~1A offset)

Gain = Rc / (Ra + Rb)

Vout @ 36A = 2.44V-2.60V

1 1 0 1-Phase DCM

0 1 1 2-Phase CCM

(IMVP6_NTC)

(IMVP6_VO)

(IMVP6_FB)

Vout = Gain * ((2.1 mV/A * Iload) + Voffset)

<Rc>

<Ra + Rb>

CPU VCore Current Sense

50V0.0022UF10%

NO STUFF

CERM402

2

1 C75010.0022UF

NO STUFF

50V10%CERM402

2

1 C7502

1%1/16WMF-LF

10K

402

21

R7505 0.22UF

6.3VX5R402

20%

21

C7505

1/10W

603

1%

MF-LF

3.65K

2

1R7506

MF-LF4021/16W1%147K

2

1R7532

CERM20%

0.01uF16V402

2

1C7532

16V10%X5R

0.1uF

4022

1C7531

ISL6262

OMIT

QFN

9

19

21

14

5

44

18

20

43424140393837

13

22

27

35

49

7

15

4

31

2

28

34

129

33

3

8

6

25

30

32

23

24

1211

16

4645

17

10

47

2636

48

U7530

1/16W1%

1.82K

402MF-LF

2

1R7535

3.57K

402

1%MF-LF1/16W

2

1R7537

CERM402

10%25V

0.0047uF2

1C7537182K1/16W

402MF-LF

1%

2

1R7534

330pF

CERM402

10%50V 2

1C7535

20%0.22uF

603X5R25V2

1 C750020%

0.22uF25VX5R603

2

1C7550

9.31K

4021/16W1%MF-LF

2

1R7542MF-LF402

1%1/16W

3.01K21

R7540

1/16W1%1K

MF-LF4022

1R7541

CERM402

5%50V

180pF2

1C7540

4021/16W1%

MF-LF

49921

R7545

21 7

79 23 14

7

62

26

47

26 14

CRITICAL

HAT2165HLFPAK

321

4

5

Q7501

LFPAK

CRITICAL

HAT2165H

321

4

5

Q7502

LFPAK

CRITICAL

HAT2168H

321

4

5

Q750016V20%

1210X7R

22uF2

1C751022uF

20%X7R16V

12102

1C751116VX7R

1210

22uF20%

2

1C7512

1%MF-LF1/16W

10K

402

21

R7555

HAT2168HLFPAK

CRITICAL

321

4

5

Q7550

6.3VX5R402

20%

0.22UF21

C7555

1/10W

603

3.65K1%

MF-LF2

1R7556LFPAKHAT2165H

CRITICAL

321

4

5

Q7552

NO STUFF

40250V10%CERM

0.0022UF2

1 C7552

LFPAKHAT2165H

CRITICAL

321

4

5

Q7551

NO STUFF

50V10%0.0022UF

CERM402

2

1 C7551

CERM6.3V402

10%1uF

2

1C7530402

10

5%1/16WMF-LF

21

R7530 22uF16V20%

1210X7R

C7513

NO STUFF

2.0K1%1/16WMF-LF4022

1R7536

MF-LF4021/16W

1.40K1%

2

1R7533

402

10%470pF

50VCERM 2

1C7533

20%X5R

0.22uF

4026.3V 2

1C7544

MF-LF1%1/16W

11K

4022

1R7543

30.1K

1%1/16W402

MF-LF

21

R7593

30.1K

1%

4021/16WMF-LF

21

R7591

16V1uF10%X5R603

2

1C7528

603

20%6.3VCERM

4.7uF2

1 C7529

5%

10

MF-LF1/16W402

21

R7531

MF-LF402

10

5%1/16W

21

R7528

402

0.01uF10%16V

CERM 2

1C7546

MF-LF

4.02K1%

4021/16W

2

1R7547

4991%1/16WMF-LF4022

1R7544

0.22UF

402X5R

6.3V20%

2

1C7541

25V

0.0068uF

402CERM

10%2

1C7580

CERM402

10%50V

0.001uF

NO STUFF

2

1C7542

1%

4021/16W

3.92K

MF-LF2

1R7548

402CERM16V10%0.01uF

2

1 C7543

402

5%1

1/16WMF-LF

2

1R7507

402

1

MF-LF1/16W

5%

2

1R7557

402

0.01uF16V10%

CERM

NO STUFF

2

1 C758110%16V

0.01uF

CERM402

2

1C7582

0

402

5%

MF-LF1/16W

21

R7581

0

402MF-LF1/16W5%

21

R7582

402

1M

1%1/16WMF-LF

21

R7598

LMV2011MFSOT23-5

2

5

1

4

3

U7595

1%

1M

MF-LF402

1/16W

21

R7592

51

CERM6.3V10%

402

1uF2

1C7595

CRITICAL

0603-LF

10KOHM-5%

2

1

R7549

470pF

50V10%

CERM402

21

C7598

402

470pF

CERM50V10%

21

C7592

CERM50V10%390pF

4022

1 C7534

B340LBXFSMB

CRITICAL 2

1

D7500

SMBB340LBXF

CRITICAL 2

1

D7550

CRITICAL

402

470K

2

1

R7546

20%16VX7R

1210

22uFC7563

20%16VX7R

22uF

12102

1C756220%X7R

121016V

22uF2

1C756116V20%

1210X7R

22uF2

1C7560

0.36uH

SM-PCC

CRITICAL

21

L7505

SM-PCC

0.36uH

CRITICAL

21

L7555

5%

0

1/16W

402MF-LF

21

R7594

0.1uF

NO STUFF

20%10VCERM402

2

1 C7594

SM2 1

XW7530


10475

A051-6941

IMVP6 CPU VCore Regulator

IMVP6_OCSET

IMVP6_DROOP

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_LGATE2

IMVP6_ISEN2

IMVP6_VO

IMVP6_VSUM

IMVP6_VSEN_PIMVP6_VSEN_N

IMVP6_VO_R

IMVP6_DFB

=PP3V3R5V_S0_CPUISENSCPUISENS_NEG_RCCPUISENS_NEG

CPU_PSI_LMIN_LINE_WIDTH=0.5 mmIMVP6_UGATE2 MIN_NECK_WIDTH=0.25 mm

PP5V_S0_IMVP6_VDDMIN_LINE_WIDTH=0.25 mmVOLTAGE=5VMIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_S0_IMVP6_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

GND_IMVP6_SGND

IMVP6_VW

IMVP6_BOOT1IMVP6_BOOT2

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_PHASE2

IMVP6_DROOP

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUVCORE_IOUT

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_LGATE1

CPUISENS_POS

=PPVOUT_S0_IMVP6_REG

=PPVIN_S0_IMVP6

IMVP6_ISEN1

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_UGATE1

IMVP6_VR_TT

=PP5V_S0_IMVP6

VOLTAGE=12V

PPVIN_S0_IMVP6_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

=PPVIN_S0_IMVP6

=PP3V3_S0_IMVP6

IMVP6_FB2

IMVP6_VDIFF

IMVP6_VDIFF_RC

IMVP6_FBIMVP6_COMP

IMVP6_NTC

IMVP6_SOFT

IMVP6_RBIAS

IMVP6_NTC_R

IMVP_PWRGD_IN

IMVP_VR_ON

IMVP6_COMP_RC

IMVP6_VID<2>IMVP6_VID<1>

IMVP6_VID<3>

VR_PWRGD_CK410_L

CPU_DPRSTP_L

IMVP6_VID<0>

IMVP6_VID<4>IMVP6_VID<5>IMVP6_VID<6>

VR_PWRGOOD_DELAY

PM_DPRSLPVR

IMVP_DPRSLPVR

IMVP6_PHASE1 MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

79

79

63

63

57

79

79

63

57

8

8

63

57

63

57

63

5

5

9

9

9

9

9

9

9

79

www.vinafix.vn

NC4NC3

NC2

NC1

EXTVCC

FCB

INTVCC

PGOOD

3_3VOUT

RUN_SS2

ITH2

RUN_SS1

ITH1

SW1

TG1

BOOST1

BG1

PLLIN

SENSE1+

SENSE1-

VOSENSE1

BOOST2

TG2

BG2

SW2

PLLFLTR

SENSE2+

VOSENSE2

SENSE2-

THRML_PAD

SGND

PGND

VING

D

S

GD

S

GD

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

5V S0 FET

<Ra>

8A max output(L7620 limit)

Vout = 4.98V

NC

NCNCNC

NC

NC

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

<Rb>

Vout = 1.49V8A max output(L7660 & Q7660 limit)

If unconnected, powers up with VIN.

5V S3 FET

<Rb>

NOTE: Be aware of pull-ups to VIN on these signals.

Connect to RUNSS pins to control outputs.

CRITICAL

CMDSH-3SOD-323

2

1D7624

1uF

CERM402

10%6.3V 2

1C7605

16V10%

402

0.01uF

CERM2

1 C7607

22uF20%16VX7R1210

2

1 C7640

1/16W5%

402MF-LF

1M

2

1R7630

0.1uF20%CERM40210V2

1 C763022K5%1/16W402MF-LF

2

1R7625

50V10%

402

470pF

CERM 2

1C762550V5%

402

47pF

CERM2

1 C7626

10

4021/16WMF-LF5%

2

1R7600

10%X5R603

1uF16V2

1 C7600

CRITICAL

QFNLTC3728LXC

91

33

1426

15

6

111230

1328

2

27

19

32291610

85

20

4

21

17

18

7

U7600

CRITICAL

CMDSH-3SOD-323

2

1D7664

10V20%

402CERM

0.1uF2

1C7670

CERM50V10%

402

470pF2

1 C7665100pF

CERM402

5%50V 2

1C7666

10K

MF-LF402

5%1/16W

2

1R7665

CERM50V

0.001uF

402

10%2

1 C7662

470pF

CERM402

10%50V2

1 C762752.3K1/16W

402MF-LF

1%

2

1R7627

25V402X7R

1000pF

NO STUFF

10%2

1 C762810K1/16WMF-LF

402

1%

2

1R7628

IHLP2525CZ-SM

CRITICAL

2.2uH-14A21

L7660

39.2K

402

1%1/16WMF-LF

2

1R7668NO STUFF

25V10%

402X7R

1000pF2

1C7668

34.0K1/16W1%MF-LF4022

1R7667470pF

50V10%

402CERM 2

1C7667

MF-LF1/16W

5%

402

1M

2

1R7670

4026.3V10%1uF

CERM2

1 C7602

6036.3V20%

4.7uF

CERM 2

1C7601

MF-LF402

5%1/16W

30K

2

1R7603

1K

MF-LF402

5%1/16W

2

1R76040.01uF

CERM402

10%16V2

1 C7604

22uF20%16VX7R1210

2

1 C764122uF

20%16VX7R

12102

1C7680

X7R

22uF20%16V

12102

1C7681

MF-LF4021/16W

05%

2

1R7664

MF-LF

0

402

5%1/16W

2

1R7624CRITICAL

FDC796NSUPERSOT-6

65321

4

7

Q7660

B240-X-FSMB

CRITICAL 2

1

D7621

SUPERSOT-6FDC796N

CRITICAL

6 5 3 2 1

4

7

Q7620

SUPERSOT-6FDC796N

CRITICAL

6 5 3 2 1

4

7

Q7621

NO STUFF

10%25VX7R402

1000pF2

1C7661

402

0.1uF

CERM10V20%

2

1C7664

805X5R6.3V20%22uF

2

1 C7690

805X5R

6.3V20%

22uF2

1C7691

20%10VCERM402

0.1uF2

1 C7624

NO STUFF

402X7R25V10%1000pF

2

1 C7621 10%

CERM50V

0.001uF

4022

1C762220%

CRITICAL

SMC-LFPOLY6.3V

150uF2

1C765220%

22uF6.3VX5R805

2

1C7650

X5R805

22uF20%6.3V2

1 C7651

1/16W5%

402MF-LF

0

P5VP1V5_SKIP

2

1R7606

0

MF-LF402

P5VP1V5_CONT

5%1/16W

2

1R7607

SM21

XW7600

0.1uF10%16VX5R402

2

1C7620 3.9K5%1/16WMF-LF4022

1R7620

0.1uF10%16VX5R402

2

1 C76231%

402MF-LF

1.33K1/16W

2

1R7623

0.1uF10%16VX5R402

2

1 C76601%

402

1/16WMF-LF

3.65K

2

1R7660

0.1uF

402X5R16V10%

2

1C76631%909

402MF-LF1/16W

2

1R7663

CASE-D2E-LF

330uF

CRITICAL

POLY20%2.5V-ESR9V2

1C7692

CRITICAL

IRF7832PBFSO-8

321

4

8765

Q7661

SM5

4.7uH

CRITICAL

21

L7620

1%1.21K

MF-LF1/16W

402 2

1R76691%1.21K

MF-LF1/16W

4022

1R7629

22uF

805X5R6.3V20%

2

1 C7617

22uF

805X5R

6.3V20%

2

1C7616

0.0022uF

402CERM50V10%

21

C7615

FDC638PSM-LF

4

3

6

5

2

1

Q7615

100K

5%1/16WMF-LF402

21

R7615

FDC638PSM-LF

4

3

6

5

2

1

Q7610

0.0022uF

402CERM

10%50V

21

C7610

MF-LF1/16W5%

402

100K21

R7610


5V / 1.5V Power Supply

051-6941 A

10476

=PPVIN_S5_P5VP1V5

=PP5V_S5_P5VP1V5_VCC

=P5VS3_EN_L

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_BOOST_RC

P1V5S0_ITH

=P5VP1V5_PGOOD

P5VS5_RUNSS

PP5V_S5_P5VP1V5_INTVCC

MIN_LINE_WIDTH=0.6 mmP5VS5_BOOST_RC

MIN_NECK_WIDTH=0.25 mm

P5VS5_TGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

P5VS5_BOOSTMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_SW

P5VP1V5_FCB

P5VS0_EN_L_RC

=PP5V_S3_FET

=P5VS0_EN_L

=PP5V_S0_FET

=PP5V_S0_P5VS0

P5VS3_EN_L_RC

=PP5V_S3_P5VS3

PP5V_S5_P5VP1V5_INTVCC

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_TG

P1V5S0_ITH_RCP5VS5_ITH_RC

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BG

P1V5S0_RUNSS

MIN_LINE_WIDTH=0.6 mmVOLTAGE=12VMIN_NECK_WIDTH=0.25 mm

PPVIN_S5_P5VP1V5_R

MIN_NECK_WIDTH=0.25 mmVOLTAGE=5VPP5V_S5_P5VP1V5_INTVCC

MIN_LINE_WIDTH=0.6 mm

P5VP1V5_FSEL

P5VS5_ITH

MIN_LINE_WIDTH=0.6 mm P5VS5_BGMIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BOOST

P5VP1V5_FSEL

P1V5S0_SNS_R_N


P1V5S0_SNS_R_P


=PP1V5_S0_REG

MIN_LINE_WIDTH=0.6 mmVOLTAGE=0VMIN_NECK_WIDTH=0.25 mm

GND_P5VP1V5_SGND

P1V5S0_VOSNSP5VS5_VOSNS

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm P5VS5_SW

P5VS5_SNS_P


=PP5V_S5_REG

P5VS5_SNS_N


62

63

63

63

62

62

5

58

63

62

63

63

63

58

58

58

58

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PVINSVIN

SHDN/RT

SYNC/MODE

SW

VFB

ITHPGOODPGND SGND

SW

SGND PGND PADTHERM

SVIN PVIN

PGOOD

VFB

ITHSYNC/MODE

RUN/SSRT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Continuous

Burst

NOTE: Be aware of pull-up on this signal.

Connect RUNSS off-page to controlIf unconnected, powers up with PVIN.

ContinuousMode

2.5V S3 Regulator

2.5V S0 FET

1.2V S0 FET

Vout = 0.8V * (1 + Ra / Rb)

Vout = 0.8V * (1 + Ra / (Rb + Rc))

<Rc>

<Rb>

<Ra>

1.2V S3 Regulator

<Ra> Vout = 2.52V1.25A max output(Switcher limit)

Vout = 1.205V2.5A max output(Switcher limit)

<Rb>

LTC3411

CRITICAL

MSOP-LF

92

4

7

1

3

6

8

5

10

U7700

CERM

100pF

402

5%50V 2

1C7703

4.99K

MF-LF402

1%1/16W

2

1R7706

0.0033uF

CERM402

10%50V2

1 C7704

2.2uH-1.32A

CDRH4D18-SM

CRITICAL

21

L7700

22pF5%

CERM40250V 2

1C7706 10K1/16W1%MF-LF4022

1R7707

4.7K

MF-LF402

1%1/16W

2

1R7708

805X5R

22uF20%6.3V2

1 C7709

1uF

CERM402

10%6.3V2

1 C7701

1/16W5%

402MF-LF

1021

R770010UF

603X5R6.3V20%

2

1 C7700

MF-LF402

1%324K1/16W

2

1R77051M

MF-LF402

5%1/16W

2

1R7704

1/16W5%

402MF-LF

1M

2

1R7701

SM21

XW7700

6.3V20%

805X5R

22uF2

1 C77566.3V20%

805X5R

22uF2

1C7755

22uF

X5R805

20%6.3V2

1 C7752

805

22uF

X5R6.3V20%

2

1C7751

50V5%

402CERM

22pF2

1 C77501/16W

1%

402MF-LF

47.0K

2

1R7750

MF-LF402

1%1/16W

61.9K

2

1R7751

SM-LF

CRITICAL

1.0UH-3.48A21

L7750

MF-LF402

1%1/16W

30.9K

2

1R7752

CRITICAL

TSSOP-LFLTC3412

4

17

6

15141110

1

875

16

9

2

13

12

3

U7750

SM21

XW7750

309K

MF-LF402

1%1/16W

2

1R7754

50V470pF

CERM402

10%2

1C7757

1/16W5%

402MF-LF

0

NO STUFF

2

1R77555.1M1/16W

5%

402MF-LF

2

1R7757

0

MF-LF402

5%1/16W

2

1R7756

CERM402

5%50V

22pF2

1C7754

MF-LF402

1%1/16W

8.25K

2

1R7753

CERM402

10%50V0.0022uF

2

1 C7753

SI3446DVTSOP-LF

4

36

5

2

1

Q7720

50V

0.0022uF10%

CERM402

2

1C7720

402

5%1/16WMF-LF

100K21

R7720

TSOP-LFSI3446DV

4

36

5

2

1

Q7770

10%50V

402

0.0022uF

CERM 2

1C7770

5%1/16WMF-LF

0

402

21

R7770


2.5V & 1.2V Regulators

A051-6941

77 104

PPVIN_S3_P2V5S3_SVIN

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3V

P2V5S3_ITH=P2V5S3_PGOOD

P2V5S3_ITH_RC

=PP2V5_S3_REG

P2V5S3_VFB

=PP1V2_S3_REG

P1V2S3_VFB

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V2S3_SW

MIN_NECK_WIDTH=0.25 mmP2V5S3_SW


=P1V2S3_PGOOD

P2V5S0_EN_RC=P2V5S0_EN

=PP1V2_S0_FET=PP1V2_S0_P1V2S0


=PP2V5_S0_FET=PP2V5_S0_P2V5S0

=P2V5S3_EN_L

=PPVIN_S3_P2V5S3

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=0VGND_P2V5S3_SGND

P2V5S3_MODE

P2V5S3_SHDNRT

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=0VGND_P1V2S3_SGND

P1V2S3_ITHP1V2S3_MODE

P1V2S3_RUNSS

P1V2S3_ITH_RC

P1V2S3_VFB_DIV

P1V2S3_RT

=PPVIN_S3_P1V2S3

39

39

62

63

63

62

62

63 63

62

63 63

39

63

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5

5

5

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PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOODCOMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

OUT

GD S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Vout = 1.83V

1.8V S0 FET

Keep C7890, R7890,Placement Note:

close to inductor

NC

<Ra>

R7894 and R7897

(P1V8S3_FB)

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

17A max output(Q7820 limit)

1.8V S3 Current Sense

20%2.5V-ESR9VCASE-D2E-LF

POLY

330uF2

1C7842

1/16WMF-LF

402

3.32K1%

2

1R7821

1.62K

MF-LF402

1%1/16W

2

1R7822

1.0uH-20.5

SM1

CRITICAL

3

2

1

L7820

LFPAKHAT2168H

CRITICAL

321

4

5

Q7820

CRITICAL

B340LBXFSMB

2

1

D7820

3.01K

1/16W1%

402MF-LF

21

R7810

6.3V2.2UF

603CERM1

20%2

1C7802

603CERM1

2.2UF20%

6.3V 2

1C7800603

10%1uF16VX5R 2

1C7801

CRITICALQFN

ISL6269

8

1

2

14

17

12

1516

10

11

9

7

3

6

4

5

13

U7800

15PF

CERM402

5%50V 2

1C780764.9K

MF-LF402

1%1/16W

2

1R7808

50V10%

0.0022uF

402CERM 2

1C7808

MF-LF

05%

1/16W

NO STUFF

4022

1R7804

1/16W5%

402MF-LF

0

2

1R7805

57.6K

MF-LF402

1%1/16W

2

1R78060.01UF

CERM402

10%16V 2

1C7806

22uF

X7R16V1210

20%2

1 C7831

1210X7R16V22uF20%

2

1 C7830

22uF20%X5R

6.3V805

2

1C7840

8056.3VX5R

22uF20%

2

1 C7841

CASE-D2E-LF

330uF20%2.5V-ESR9VPOLY2

1 C78431000pF

402X7R25V10%

NO STUFF

2

1C7822

402

10%1000pF

X7R25V

NO STUFF

2

1 C7821

SM21

XW7800

22uF20%X7R16V1210

2

1 C783316VX7R1210

20%22uF

2

1 C7832402

NO STUFF

MF-LF1/16W5%0

2

1R7802

LFPAKHAT2165H

CRITICAL

321

4

5

Q7822

HAT2165HLFPAK

CRITICAL

321

4

5

Q7821

51

1uF

CERM402

10%6.3V2

1 C789510%

CERM402

470pF

50V

2 1

C7898

1/16W1%

1M

MF-LF402

21

R7898

LMV2011MFSOT23-5

2

5

1

4

3

U7895

50VCERM

10%

402

470pF2 1

C78921%

1M

1/16WMF-LF402

21

R7892

10KOHM-5%

CRITICAL

0603-LF

2

1

R78971%1K

402

1/16WMF-LF

2

1R7896

20.0K

MF-LF402

1/16W1%

21

R7893

1/16W

20.0K

402MF-LF1%

21

R7891

NO STUFF

1/16WMF-LF402

1K

1%

21

R7894

1uF

402CERM6.3V10%

2 1

C7890

6491%

MF-LF402

1/16W

2

1R7890

SUPERSOT-6FDC796N

6

5

3

2

1

4

7

Q7845

22uF6.3V

805X5R

20%2

1 C784720%

6.3V

805

22uF

X5R 2

1C7846402CERM50V10%0.0022uF

2

1 C7845

5%1/16WMF-LF402

021

R7845

X5R

0.22uF

402

6.3V20%

2

1 C780905%

1/16WMF-LF

4022

1R7809

402CERM10%

0.0022uF50V

NO STUFF

2

1C7820

5%

NO STUFF

01/16WMF-LF4022

1R7820

402MF-LF1/16W

5%470K

2

1R7846


1.8V Supply

051-6941

78 104

A

P1V8S3_PHASE

SWITCH_NODE=TRUEMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

=PPBUS_S0_P1V8S0

=PPVIN_S3_P1V8S3

=PP1V8_S0_P1V8S0


=P1V8S3_PGOOD

=P1V8S3_ENP1V8S3_FCCM

MIN_LINE_WIDTH=0.25 mmP1V8S3_BOOT_R


P1V8S3_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

P1V8S3_FB_RC

P1V8S3_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

P1V8S3_FSET

PP5V_S3_P1V8S3_VCC


P1V8S3_COMP_R

P1V8ISENS_RC

GND_P1V8S3_SGND

=PP1V8_S0_FET

P1V8S3_COMP P1V8S3_ISEN

=PP5V_S3_P1V8S3

P1V8ISENS_NTC

P1V8ISENS_NEG

P1V8S3_IOUT

P1V8ISENS_POS

=PP3V3R5V_S3_P1V8ISENS

P1V8S3_FB

=PP1V8_S3_REG


P1V8S3_UGMIN_LINE_WIDTH=0.6 mm

63 51

63

63

63

62

62

62

5

63

5

63

63

5

www.vinafix.vn

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOODCOMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

OUT

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOODCOMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

GD

S

GD

S

GD

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(Q7970 & L7970 limit)

close to inductorR7994 and R7997

4.5A max output

3.3V S3 FET

Vout = 3.32V

<Rb>

<Ra>

3.3V S0 FET

(L7920 limit)

3.3V S5 Regulator

1.05V S0 Regulator

10A max outputVout = 1.05V

Placement Note:Keep C7990, R7990,

NC

<Ra>

(P1V05S0_FB)

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

1.05V Current Sense

Vout = 0.6V * (1 + Ra / Rb)

603X5R10%1uF16V 2

1C7951

QFNISL6269

CRITICAL

8

1

2

14

17

12

1516

10

11

9

7

3

6

4

5

13

U7950

50V5%

402CERM

15PF2

1C7957

CERM402

20%16V

0.01uF2

1C7958

MF-LF402

1%1/16W

30.9K

2

1R7958

1/16W5%MF-LF

0

NO STUFF

4022

1R7954

0

MF-LF402

5%1/16W

2

1R7955

57.6K1%

402MF-LF1/16W

2

1R7956

16V10%

402CERM

0.01UF2

1C7956

SO-8

CRITICAL

IRF7832PBF

321

4

8765

Q7971

CASE-D2E-LF2.5V-ESR9V

330uF20%POLY2

1 C7989

20%22uF

X7R16V1210

2

1 C7982

MBRS140XXGSMB

CRITICAL 2

1

D7920

20%X7R16V1210

22uF2

1 C7930

NO STUFF

1/16WMF-LF402

5%0

2

1R7902

NO STUFF

402

0

MF-LF5%1/16W

2

1R7952

50V

470pF

CERM

10%

402

2 1

C7998

1uF

CERM402

10%6.3V2

1 C7995

402MF-LF1/16W

1M

1%

21

R7998

LMV2011MFSOT23-5

2

5

1

4

3

U7995

50V

470pF

402CERM

10%

2 1

C7992402

MF-LF1/16W

1M

1%

21

R7992

CRITICAL

0603-LF

10KOHM-5%

2

1

R7997

402MF-LF1/16W

1K1%

2

1R7996

1%1/16W402

MF-LF

20.0K21

R7993

10%6.3VCERM402

1uF2 1

C7990

MF-LF1%

1/16W

20.0K

402

21

R7991

1%

1K

402MF-LF1/16W

NO STUFF

21

R7994

1%1/16W

402MF-LF

649

2

1R7990

51

0

402

5%1/16WMF-LF

21

R7949

NO STUFF

20%16V0.01uF

402CERM2

1 C7949

402

10%25VCERM

0.0047uF2

1 C7920

0

1/16WMF-LF402

5%

2 1

R7920

402CERM

10%

0.0047uF

25V

21

C7947

SM-LFFDC638P

4

3

6

5

2

1

Q7947

402MF-LF1/16W5%

100K21

R7947

0.0022uF

402CERM50V10%

21

C7945

SM-LFFDC638P

4

3

6

5

2

1

Q7945

402MF-LF1/16W5%

100K21

R79455%0

1/16WMF-LF

4022

1R79090.22uF

402X5R6.3V20%

2

1 C7909

05%

1/16WMF-LF

4022

1R795920%6.3VX5R402

0.22uF2

1 C7959

402CERM10%

0.0022uF50V

NO STUFF

2

1C7970

402MF-LF1/16W

05%

NO STUFF

2

1R7970

1210

22uF20%X7R16V 2

1C7980

121016VX7R20%22uF

2

1 C7981

3.01K

MF-LF402

1%1/16W

21

R7910

SMC-LFPOLY20%150uF6.3V2

1C7942

603

2.2UF

CERM120%

6.3V 2

1C7902

10%25VX7R402

NO STUFF

1000pF2

1C7921

SM21

XW7900

2.2UF

CERM1603

20%6.3V 2

1C790010%X5R

1uF

60316V 2

1C7901

ISL6269QFN

CRITICAL

8

1

2

14

17

12

1516

10

11

9

7

3

6

4

5

13

U7900

50V470pF

10%CERM402

2

1C7907

0.022uF

CERM-X5R10%16V402

2

1C7908

NO STUFF

MF-LF1/16W5%0

4022

1R7904

51.1K

402MF-LF1/16W1%

2

1R7908

1/16W5%

402MF-LF

0

2

1R7905

1/16W

57.6K

MF-LF1%

4022

1R7906

16V10%

402CERM

0.01UF2

1C7906

22uF

8056.3VX5R20%

2

1C7941

805

22uF20%6.3VX5R2

1 C79403.32K

MF-LF402

1%1/16W

2

1R7921

MF-LF402

1%1/16W

732

2

1R7922

FDC796NSUPERSOT-6

CRITICAL

65321

4

7

Q7920

4.7uH

CRITICAL

IHLP

21

L7920

SUPERSOT-6

CRITICAL

FDC796N

65321

4

7

Q7921

2.2UF

CERM1603

20%6.3V 2

1C7952

20%22uF

X5R6.3V805

2

1C7986

805

22uF20%6.3VX5R2

1 C79851/16W

1%

402MF-LF

3.32K

2

1R7971

1/16W1%

MF-LF

4.42K

4022

1R7972

SM

1.53uH

CRITICAL

3

2

1

L7970

CRITICAL

SUPERSOT-6FDC796N

65321

4

7

Q7970

402MF-LF1%

1/16W

2.8K21

R7960

1000pF

402X7R25V10%

NO STUFF

2

1C7971

SM21

XW7950

2.2UF

CERM1603

20%6.3V 2

1C7950

051-6941

79 104

A

SYNC_DATE=(MASTER)

3.3V / 1.05V Power SuppliesSYNC_MASTER=(MASTER)

=PPVIN_S5_P3V3S5

P1V05S0_IOUT

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP3V3S5_UG

P3V3S5_FSET

=PPVIN_S0_P1V05S0

P1V05ISENS_NTC

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmSWITCH_NODE=TRUE

P1V05S0_PHASE

P1V05ISENS_RC

P1V05S0_FB

P1V05ISENS_NEG

=PP3V3R5V_S0_P1V05ISENS

P1V05S0_FB_RC

P3V3S5_FCCM


PP5V_S5_P3V3S5_VCC


PP5V_S0_P1V05S0_VCC

P1V05S0_FCCM=P1V05S0_PGOOD

=P1V05S0_EN

GND_P1V05S0_SGND

P1V05S0_FSET

P1V05S0_COMP

=PP5V_S0_P1V05S0

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_LG

P1V05S0_COMP_R


P1V05S0_BOOT

P1V05S0_ISEN

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_UG

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmP1V05S0_BOOT_R

=PP5V_S5_P3V3S5

=PP3V3_S5_REG

GND_P3V3S5_SGND

P3V3S5_FB_RC

P3V3S5_FB

=P3V3S0_EN_L P3V3S0_EN_L_RC

=PP3V3_S0_FET

=PP3V3_S0_P3V3S0

P3V3S5_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm


P3V3S5_PHASE

P3V3S5_BOOT_RMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm

P3V3S5_COMP

=P3V3S5_EN

=P3V3S5_PGOOD

=P3V3S3_EN_L

P3V3S5_EN_RC

P3V3S5_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

P3V3S3_EN_L_RC

=PP3V3_S3_FET

P3V3S5_COMP_R

P3V3S5_ISEN

=PP3V3_S3_P3V3S3

P1V05ISENS_POS

=PP1V05_S0_REG 63 51

63

5

63

63

62

62

5

5

63

63

63

62

63

63

5

62

48

62

63

63

5

www.vinafix.vn

FB

BIAS

SWSHDN*

NC

VIN BOOST

GND

G

D

S

V-

V+

OUT

THRML

V2V1

RST*

V3

V4

VADJ1

VADJ2

GND PAD

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

0.89V Reference

3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Run (S0)

Battery Off (G3Hot) 01

11

SMC_PM_G2_ENABLE

00

11

PM_SLP_S4_L

0001

PM_SLP_S3_L

(Switcher limit)200mA max outputVout = 3.425

<Ra>

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

before enabling GPU VCore to supportremoving ethernet power in battery sleep.

Ensure 1.2V and 2.5V S3 supplies are up

by ethernet power control circuit.2.5V S3 and 1.2V S3 supplies are controlled

5V Enable has pull-up to PBUS

(PM_SLP_S3_L)

(P5VS5_PGOOD)

(PM_SLP_S4_L)

PowerPlay is changingdeassert while GPU

GPU core voltage.

Need to ensure that

Power Control Signals

LTC2908 sources 6uA at 5.0V

and 3.3V level-shifter.

1.5V Comp threshold set to 1.32V (88%)

LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)

ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)NOTE: R8065 acts as 10K pull-up for PGOOD signal

Reports when 1.5V S0 and 1.05V S0 are in regulation

ISL6269 PGOOD does not

1.8V Enable has pull-up to PBUS

Unused PGOOD Signals

3.3V rise after VCore is up.GPU requires 1.2V, 1.8V, 2.5V and

1.5V Enable has pull-up to PBUS 1.5V / 1.05V PWRGD Circuit

Reports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation

Other S0 Rails PWRGD Circuit

R8076 serves as pull-down

LT3470

CRITICAL

TSOT23-8

3

51

2

4

8

6

7

U8000

NO STUFF

MF-LF1/16W5%

402

021

R8060

SOT-3632N7002DW-X-F

4

5

3

Q8056

25V10%

1206X5R

10uF2

1C8000

6.3V20%

805X5R

22uF2

1 C8015

1/16W1%

402MF-LF

200K

2

1R8011

10K

MF-LF402

5%1/16W

2

1R8065

0.1uF

CERM402

20%10V 2

1C8060

LMC7211SM-LF

2

5

1

3

4U8060

MC74VHC1G08SC70

5

41

2

3

U8080

20%0.1UF

10VCERM402

2

1C8080

57

0.1uF

CERM402

20%10V2

1 C8071

CRITICAL

LTC2908LLP

8

6

3

7

45

9

2

1

U8070

1/16W402MF-LF1%549K

2

1R8076

4.99K

MF-LF402

1%1/16W

2

1R806327.4K

MF-LF402

1%1/16W

2

1R8061

10K

MF-LF402

1%1/16W

2

1R806410K

MF-LF402

1%1/16W

2

1R8062

0.1uF

CERM402

20%10V 2

1C8070

MF-LF402

1%1/16W

124K

2

1R8072

MF-LF402

1%1/16W

100K

2

1R8073

61

68.1K

MF-LF402

1%1/16W

2

1R8074

100K

MF-LF402

1%1/16W

2

1R8075

10K

MF-LF402

5%1/16W

2

1R805110K

MF-LF402

5%1/16W

2

1R8050

2N7002DW-X-FSOT-363

1

2

6

Q8057

2N7002DW-X-FSOT-363

1

2

6

Q8050

47 26

100K

MF-LF402

5%1/16W

2

1R8054

2N7002DW-X-FSOT-363

4

5

3

Q8057

1/16W1%

402MF-LF

348K

2

1R8010

1/16W

10K

MF-LF402

5%

2

1R8055

2N7002DW-X-FSOT-363

1

2

6

Q8055

SOT-3632N7002DW-X-F

4

5

3

Q8055

CDPH4D19F-SM

33uH

CRITICAL

21

L8010

SOT-3632N7002DW-X-F

4

5

3

Q80591/16W5%

402MF-LF

470K

2

1R8059

SOT-3632N7002DW-X-F

1

2

6

Q8059

2N7002DW-X-FSOT-363

4

5

3

Q8050

66

50V5%

402CERM

22pF2

1C8010

MF-LF

100K

402

5%1/16W

2

1R8056

47 41 23

100K

MF-LF402

5%1/16W

2

1R8057

47 39 23

100K

MF-LF402

5%1/16W

2

1R8058

48

47

6.3V20%

402X5R

0.22uF2

1C8005

59

59 10K1/16W5%

402MF-LF

2

1R8053

1/16W5%

402MF-LF

10K

2

1R8052

SYNC_DATE=(MASTER)

10480

051-6941 A


3.3V G3Hot Supply & Power Control

S0PGOOD_PWROK

PP3V3_S0

P2V5S3_P1V2S3_PGOODMAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

=PP5V_S5_PWRCTL

MAKE_BASE=TRUEPM_SLP_S3_LS5V_L

P3V3S0_EN_LMAKE_BASE=TRUE

=P1V8S3_PGOODMAKE_BASE=TRUETP_P1V8S3_PGOOD

=P5VP1V5_PGOODMAKE_BASE=TRUETP_P5V_P1V5_PGOOD

=P1V8S0_ENP1V8S0_ENMAKE_BASE=TRUE

=P2V5S0_EN=P1V2S0_EN

=P3V3S0_EN_L

PM_SLP_S3_LS5VMAKE_BASE=TRUE

=P1V05S0_PGOOD

S0PGOOD_1V2_DIV

S0PGOOD_0V9_DIV

P1V5S0_COMP_POS

P1V0_P1V5PG_REF

P1V5S0_PGOOD

IMVP_PWRGD_IN

ALL_SYS_PWRGD

=PP3V3_S5_P1V5PG

PP5V_S0

P1V5P1V05S0_PGOODMAKE_BASE=TRUE

=PP3V3_S0_ALLSYSPG

PP1V8_S0PP2V5_S0

PP1V2_S0PP0V9_S0

PP1V5_S0

=GPUVCORE_PGOOD

P5VS5_PGOODMAKE_BASE=TRUE

=P2V5S3_PGOOD=P1V2S3_PGOOD

SMC_PM_G2_EN

SMC_PM_G2_EN_L

=P3V3S5_EN

LIO_P3V3S3_EN=RTUSB_EN=P1V8S3_EN

=P5VS3_EN_L=P3V3S3_EN_L

GPUVCORE_ENMAKE_BASE=TRUE

=GPUVCORE_EN

PM_SLP_S3

=PBUSVSENS_EN=MEMVREF_EN=ENET_VMAIN_AVLBL=P1V05S0_EN

LIO_P3V3S0_EN_L=P5VS0_EN_L

PM_SLP_S4_L

MAKE_BASE=TRUE

PM_SLP_S4_LS5VMAKE_BASE=TRUE

MAKE_BASE=TRUE

PM_SLP_S3_L

=PP3V42_G3H_PWRCTL

P5VS5_RUNSS

=PP5V_S5_PWRCTL

P1V5S0_RUNSS

=PP3V42_G3H_REG

P3V42G3H_FB

MIN_LINE_WIDTH=0.5 mmP3V42G3H_SW

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm

=PPVIN_G3H_P3V42G3HP3V42G3H5_BOOST

63

63

45

45

63

58

63

58

63

62

62

60

58

60

59

59

61

63

63

63

63

63

63

63

63

61

5

44

60

58

61

66

51

32

37

61

5

58

62

5

62

5

63

5

63

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

"S3AC" rail is ON in S3 on AC, OFF in S3 on battery


Power Aliases

104

051-6941 A

81

VOLTAGE=0VMIN_LINE_WIDTH=0.5 mmGNDMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUEVOLTAGE=1.8V

PP1V8_S0

PP1V5_S0

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=0

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.22 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

PP1V2_S3

=PP1V5_S0_NB_PCIE

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_LIO

=PP3V3_S3_SMS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PCI

=PP2V5_S0_NB_VCCA_3GBG

=PP2V5_S0_GPU_VDD25



=PP1V8_S0_FB_VDD=PP1V8_S0_FB_VDDQ

=PP1V8_S0_P1V8S0

=PP2V5_S3_ENET=PP2V5_S0_P2V5S0

=PP1V05_S0_FSB_NB=PP1V05_S0_CPU

=PP0V9_S0_MEM_TERM

=PP1V05_S0_NB_VTT

=PP1V2_S0_PCIE_GPU_VDDR

=PP1V5_S0_CPU=PP1V5_S0_NB=PP1V5_S0_NB_3G=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL

=PP1V5_S0_NB_VCCAUX=PP1V5_S0_NB_VCCD_HMPLL=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A_ARX=PP1V5_S0_SB_VCC1_5_A_ATX=PP1V5_S0_SB_VCC1_5_A_USB_CORE=PP1V5_S0_SB_VCCSATAPLL

=PP1V8_S3_MEM=PP1V8_S3_MEM_NB=PP1V8_S3_MEMVREF=PP1V8_S0_MEMVTT

=PP1V8R2V0_S0_FB_GPU

=PP2V5_S0_GPU=PP2V5_S0_GPU_PVDD

=PP2V5_S0_GPU_VDDC_CT

=PPVCORE_S0_GPU=PPVCORE_S0_GPU_BBP

=PPVIN_G3H_P3V42G3H


=PP1V2_S0_P1V2S0=PP1V2_S3_ENET

=PP1V05_S0_NB_CRT

=PP1V2_S0_PCIE_GPU=PP1V2_S0_GPU_VDDPLL

=PP1V2_S0_PCIE_GPU_PVDD

MAKE_BASE=TRUE

PP0V9_S0


=PP1V05_S0_REG

=PP1V2_S3_REG

VOLTAGE=1.2VMAKE_BASE=TRUE


PP1V2_S0

=PP1V2_S0_FET

=PP1V5_S0_REG

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUE

PP1V8_S3

VOLTAGE=1.8V

=PP1V8_S3_REG

=PP1V8_S0_FET

MIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUE

PP2V5_S3

VOLTAGE=2.5VMIN_LINE_WIDTH=0.6 mm

=PP2V5_S3_REG

VOLTAGE=0MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP2V5_S0MIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_FET

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.2VMAKE_BASE=TRUE

PPVCORE_S0_GPU

=PPVCORE_S0_GPU_REG

PPDCIN_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=18.5V

=PPDCIN_G3H_LIO

=PP0V9_S0_MEMVTT_LDO

=PPVCORE_S0_NB=PPVCORE_S0_SB

MAKE_BASE=TRUE

PP1V05_S0

VOLTAGE=1.05VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

PP3V3_S3AC

MAKE_BASE=TRUE


MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmMAKE_BASE=TRUE

PNBB_S0_GPU

VOLTAGE=-0.7V

MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.9V

PPBB_S0_GPU

MAKE_BASE=TRUE



PPVCORE_S0_CPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.1V

PP3V42_G3H



PPBUS_G3H



MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.3 mmMAKE_BASE=TRUEVOLTAGE=33V

PPBUS_S5_FW_FET

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP5V_S5

VOLTAGE=5V


PP5V_S3

MAKE_BASE=TRUEVOLTAGE=5V

PP5V_S0


MAKE_BASE=TRUE

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_LINE_WIDTH=0.4 mmPP3V3_S5MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 MMMAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_S3MIN_LINE_WIDTH=0.5 MM

PP3V3_S0MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V

=PP3V3_S3_ENET=PP3V3_S3AC_FET

=PNBB_S0_GPU=PNVOUT_S0_GPUBBN_REG

=PPBB_S0_GPU=PPVOUT_S0_GPUBBP_LDO

=PPVCORE_S0_CPU=PPVOUT_S0_IMVP6_REG

=PP3V42_G3H_SMCVREF

=PP3V42_G3H_SB_RTC=PP3V42_G3H_PWRCTL=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_SMC_CLK=PP3V42_G3H_SMC_PWRGD

=PP3V42_G3H_LIO=PP3V42_G3H_PBUSVSENS=PP3V42_G3H_LIDSWITCH

=PP3V3_S5_LPCPLUS=PP3V3_S5_SMC

=PP3V3_S5_SB=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S5_SB_PM=PP3V3_S5_SB_USB

=PP3V3_S5_SB_IO

=PP3V3_S5_SB_VCCSUS3_3_USB=PP3V3_S5_SB_VCCSUS3_3

=PP3V42_G3H_REG

=PP3V3_S5_REG

=PPVIN_S0_IMVP6=PPVIN_S5_P5VP1V5=PPBUS_G3H_S3AC=PPBUS_G3H_LIO_CONN

=PPBUS_S5_FWPWRSW=PPVIN_S5_P3V3S5

=PPVIN_S3_P1V8S3

=PPVIN_S0_GPUVCORE=PPVIN_S0_P1V05S0

=PPBUS_S0_P1V8S0=PPBUS_S0_INVERTER

=PPFW_PORT1=PPBUS_S5_FW_FET

=PP5V_S5_SB=PP5V_S5_P3V3S5=PP5V_S5_P5VP1V5_VCC=PP5V_S5_LIO

=PP5V_S5_REG

=PP5V_S3_P1V8S3

=PP5V_S5_PWRCTL=PP5V_S3_P5VS3

=PP5V_S0_P5VS0=PP5V_S3_RTUSB

=PP5V_S0_GPUVCORE=PP5V_S0_P1V05S0

=PP5V_S3_CAMERA=PP5V_S3_SYSLED

=PP5V_S3_IR=PP5V_S3_TOPCASE

=PP5V_S3_FET

=PP5V_S0_DVI_DDC=PP5V_S0_IDE

=PP5V_S0_FET

=PP5V_S0_HDD=PP5V_S0_IMVP6=PP5V_S0_INVERTER

=PP5V_S0_SB=PP5V_S0_MEMVTT

=PP5V_S0_FAN_RT=PP5V_S0_FAN_LT

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS=PP5V_S0_GPUBBCTL

=PP5V_S0_ISENSECAL=PP5V_S0_AUDIO_XW

=PP3V3_S5_FWLATEVG=PP3V3_S5_P1V5PG=PP3V3_S5_ROM

=PPVIN_S3_P2V5S3=PP3V3_S3_P3V3S3

=PP3V3_S0_P3V3S0=PP3V3_S0_LCD

=PP3V3_S3_P3V3S3AC=PP3V3_S3_RTALS

=PP3V3_S3_TPM

=PP3V3_S3_TOPCASE=PP3V3_S3_BT

=PP3V3_S3_LTALS

=PP3V3_S3_FW=PP3V3_S3_MEMVREF

=PPVIN_S3_P1V2S3=PP3V3R5V_S3_P1V8ISENS

=PP3V3_S0_DDC_DVI=PP3V3_S0_DDC_LCD=PP3V3_S0_CK410=PP3V3_S0_IDE

=PP3V3_S0_INVERTER=PP3V3_S0_IMVP6

=PP3V3_S0_NB=PP3V3_S0_NB_VCC_HV=PP3V3_S0_SB

=PP3V3_S0_SB_GPIO=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_PCI=PP3V3_S0_SB_PM=PP3V3_S0_SB_VCC3_3

=PP3V3_S3_FET

=PP3V3_S0_FET

=PP3V3_S0_SB_VCCLAN3_3=PP3V3_S0_SB_VCC3_3_PCI=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0_TPM=PP3V3_S0_VGASYNC

=PP3V3_S0_THRM_SNR=PP3V3_S0_KBDLED

=PP3V3_S0_GPUTHMSNS=PP3V3_S0_RSTHMSNS=PP3V3_S0_SMBUS_SB=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_BSB=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMC_LS=PP3V3_S0_RSTBUF

=PP3V3_S0_ALLSYSPG

=PP3V3_S0_FAN_RT=PP3V3_S0_FAN_LT

=PP3V3R5V_S0_GPUISENS=PP3V3R5V_S0_CPUISENS=PP3V3_S0_FWISENS

=PPSPD_S0_MEM=PP3V3R5V_S0_P1V05ISENS

=PP3V3_S0_GPU=PP3V3_S0_GPUBBP=PP3V3_S0_GPUBBN=PP3V3_S0_GPU_VDDR3

=PP1V8R3V3_S0_GPU_VDDR5

=PP3V3_S0_GPU_GPIOS=PP1V8R3V3_S0_GPU_VDDR4

11

34

9

19

19

72

25

61

60

51

26

20

72

19

45

55

19

25

25

71

71

19

8

19

9

17

19

25

25

25

25

29

16

68

67

24

51

58

51

45

19

25

9

45

49

48

25

23

25

25

64

45

43

54

49

51

56

76

34

19

19

25

23

25

25

25

25

25

29

69

62

62

13

19

5

48

27

40

17

72

24

24

70

70

60

37

59

12

7

30

17

65

8

19

19

19

19

16

17

25

24

24

24

24

28

14

32

31

67

73

72

72

51

66

62

21

59

37

19

65

72

65

62

5

59

62

59

5

5

60

59

62

59

5

66

5

31

16

24

5

51

48

62

62

37 39

67 66

67 66

8 57

48

26

62

27

35

48

5

51

43

5

47

23

24

11

22

22

24

24

62

61

57

58

39 5

41

61

60

66

61

60

74

42 41

25

61

58

5

58

60

62

58

58

44

66

61

5

48

76

43

58

75

36

58

76

57

74

25

31

54

5

53

5

66

5

45

42

62

52

59

61

61

74

39

53

48

43

76

5

40

32

59

60

75

74

33

36

74

57

14

17

22

21

24

26

26

24

61

61

24

24

24

56

75

10

53

50

50

27

27

27

27

48

26

62

54

54

66

57

41

28

61

66

66

66

72

72

69

72

www.vinafix.vn

OUT

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Left I/O Power Connector

NC

NC

Battery Connector (Digital Signals)

518S0293

518S0368

CRITICAL

SM-2MT-LF

4321

6

5

J8250

CRITICAL

M-RT-SM87438

6

54

3

21

J8200

5%1/16WMF-LF402

10

2

1R8250

051-6941 A

10482


PBus-In & Battery Connectors

=PPBUS_G3H_LIO_CONN

GND_BATT=SMBUS_BATT_SCL=SMBUS_BATT_SDASMC_BS_ALRT_L

63

27

27

5

5

5

5

www.vinafix.vn

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PCIE_PVSS

PCIE_VDDR_12

PCIE_PVDD_12

PCIE_VSS

(1.2V)

(1.2V)

PCIE_VSS

(2 OF 7)

PCI EXPRESS POWER & GROUND

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

PCIE_REFCLKPPCIE_REFCLKN

PERST*PERST*_MASK

PCIE_TEST

PCIE_RX15N

PCIE_RX14P

PCIE_RX13N

PCIE_RX12NPCIE_RX12P

PCIE_RX1P

PCIE_TX0PPCIE_TX0N

PCIE_TX1P

PCIE_TX2N

PCIE_TX1N

PCIE_TX2P

PCIE_TX3PPCIE_TX3N

PCIE_TX4PPCIE_TX4N

PCIE_TX5PPCIE_TX5N

PCIE_TX6PPCIE_TX6N

PCIE_TX7PPCIE_TX7N

PCIE_TX8NPCIE_TX8P

PCIE_TX9P

PCIE_TX10P

PCIE_TX9N

PCIE_TX10N

PCIE_TX11PPCIE_TX11N

PCIE_TX12PPCIE_TX12N

PCIE_TX13NPCIE_TX13P



PCIE_CALRPPCIE_CALRN

PCIE_CALI

PCIE_RX1N

PCIE_RX2NPCIE_RX2P

PCIE_RX3PPCIE_RX3N

PCIE_RX4PPCIE_RX4N

PCIE_RX5PPCIE_RX5N

PCIE_RX6NPCIE_RX6P

PCIE_RX7NPCIE_RX7P

PCIE_RX8PPCIE_RX8N

PCIE_RX9PPCIE_RX9N

PCIE_RX10PPCIE_RX10N

PCIE_RX11PPCIE_RX11N

PCIE_RX13P

PCIE_RX14N

PCIE_RX0NPCIE_RX0P

PCIE_RX15P

PCI-EXPRESS BUS INTERFACE

(1 OF 7)

OUT

OUT

OUT

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

100mA

NC

2000mA

X5R 402

0.1uF16V10%

21C8481

402

0.1uFX5R16V10%

21C8482

0.1uF40216V10% X5R

21C8479

402

0.1uFX5R16V10%

21C8480

402

0.1uFX5R16V10%

21C8477

402X5R16V10%

0.1uF 21C8478

402

0.1uFX5R16V10%

21C8475

402

0.1uFX5R16V10%

21C8476

402

0.1uFX5R16V10%

21C8473

402

0.1uFX5R16V10%

21C8474

40210% 16V X5R

0.1uF 21C8420

402

0.1uFX5R16V10%

21C8471

402

0.1uFX5R16V10%

21C8472

402

0.1uFX5R16V10%

21C8469

402

0.1uFX5R16V10%

21C8470

402

0.1uFX5R16V10%

21C8467

10%

0.1uF16V X5R 402

21C8421

402

0.1uFX5R16V10%

21C8468

402

0.1uFX5R16V10%

21C8465

402

0.1uFX5R16V10%

21C8466

402

0.1uFX5R16V10%

21C8463

402

0.1uFX5R16V10%

21C8464

10% 16V X5R

0.1uF402

21C8450

402

0.1uFX5R16V10%

21C84610.1uF

402X5R16V10%

21C8462

402

0.1uFX5R16V10%

21C8459

402

0.1uFX5R16V10%

21C8460

402

0.1uFX5R16V10%

21C8457

10% 16V X5R 402

0.1uF 21C8451

0.1uF402X5R16V10%

21C8458

MF-LF1/16W

402

1%562

2

1R8496

1%2.0K

MF-LF402

1/16W

2

1R8495

1.47K1%

402MF-LF1/16W

2

1R8497

BGAM56P

OMIT

R24

AL27AK32

R23

AK31AK30AK29AK26AJ32AJ30AJ29AJ28AJ26AH29

P30

AH27AH26AH24AG31AG29AG26AG25AF30AF29AF28

P29AF26AE29AE27AE26AD31AD29AD26AD25AC30AC29

P28

AC28AC26AC24AC23AB29AB27AB26AB23AA31AA29

P26

AA26AA25AA23Y30Y29Y28Y26Y24W29W27

P25

W26W24V31V29V26V25V24U30U29U28

P24

U26U24T29T27T26T24R31R29R26R25

N30N24

AM27AL32AL31AL30AL29N29N28N27

AM31AM30AM29AM28

N26N25

W23

V23U23P23N23

U8400

CERM

1uF6.3V

402

10%2

1C8402

10% 16V X5R

0.1uF402

21C8448

402CERM

10%6.3V

1uF2

1C8401

10%6.3VCERM402

1uF2

1C8407

10% 16V X5R

0.1uF402

21C8449

10%6.3VCERM402

1uF2

1C8413

1uF

402CERM6.3V10%

2

1C8406

1uF

402CERM6.3V10%

2

1C841110%

6.3VCERM402

1uF2

1C8412

20%

X5R805

6.3V

22uF2

1 C8400

22uF6.3V

805X5R

20%2

1 C8410

10% 16V X5R

0.1uF402

21C8446

22uF6.3V

805X5R

20%2

1 C8405

200-OHM-EMI0402

2

1

L8400

10% 16V X5R

0.1uF402

21C8447

10% 16V X5R

0.1uF402

21C8444

10% 16V X5R

0.1uF402

21C8445

10% 16V X5R

0.1uF402

21C8442

10% 16V X5R

0.1uF402

21C8443

10% 16V X5R

0.1uF402

21C8440

10% 16V X5R

0.1uF402

21C8441

10% 16V X5R

0.1uF402

21C8438

10% 16V X5R 402

0.1uF 21C8439

10% 16V X5R

0.1uF402

21C8436

10% 16V X5R

0.1uF402

21C8437

10% 16V X5R

0.1uF402

21C8434

10% 16V X5R

0.1uF402

21C8435

10% 16V X5R

0.1uF402

21C8432

10% 16V X5R

0.1uF402

21C8433

10% 16V X5R

0.1uF402

21C8430

10% 16V X5R 402

0.1uF 21C8431

10% 16V X5R

0.1uF402

21C8428

10% 16V X5R

0.1uF402

21C8429

10% 16V X5R

0.1uF402

21C8426

10% 16V X5R

0.1uF402

21C8427

16V X5R

0.1uF40210%

21C8424

10% 16V X5R

0.1uF402

21C8425

0.1uF10% X5R 40216V

21C8422

10% 16V X5R

0.1uF402

21C8423

10% 16V X5R

0.1uF402

21C8455

10% 16V X5R

0.1uF402

21C8456

M56PBGA

OMIT

AF24AG24

AA27Y27

AB28AA28

AC25AB25

AD27AC27

AE28AD28

AF25AE25

AG27AF27

AH28AG28

AJ25AH25

R27P27

T28R28

U25T25

V27U27

W28V28

Y25W25

AK27AJ27

AA24

Y31W31

AA32Y32

AB30AA30

AC31AB31

AD32AC32

AE30AD30

AF31AE31

AG32AF32

AH30AG30

P31N31

R32P32

T30R30

U31T31

V32U32

W30V30

AJ31AH31

AL28AK28

AD24AE24

AB24

U8400

402

0.1uFX5R16V10%

21C8485

402

0.1uFX5R16V10%

21C8486

402

0.1uFX5R16V10%

21C8483

402

0.1uFX5R16V10%

21C8484

051-6941

SYNC_DATE=(MASTER)

A

10484

ATI M56 PCI-ESYNC_MASTER=(MASTER)

=PP1V2_S0_PCIE_GPU

PEG_D2R_C_P<15>

PEG_D2R_C_P<14>

PEG_D2R_C_P<13>

PEG_D2R_C_P<12>

PEG_D2R_C_P<11>

PEG_D2R_C_P<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<8>

PEG_D2R_C_P<7>

PEG_D2R_C_P<6>

PEG_D2R_C_P<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<3>

PEG_D2R_C_P<2>

PEG_D2R_C_P<1>

PEG_D2R_C_P<0>

PEG_D2R_N<15>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_P<10>

PEG_D2R_N<10>

PEG_D2R_P<9>

PEG_D2R_N<9>

PEG_D2R_N<8>

PEG_D2R_P<8>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_N<6>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_D2R_C_N<15>

PEG_D2R_C_N<14>

PEG_D2R_C_N<13>

PEG_D2R_C_N<12>

PEG_D2R_C_N<11>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_N<8>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_N<3>

PEG_D2R_C_N<1>

PEG_D2R_C_N<0>

GPU_PCIE_CALRN

PEG_R2D_C_N<15>

PEG_CLK100M_GPU_N

PEG_RESET_L

PEG_CLK100M_GPU_P

PEG_R2D_C_P<15>

PEG_R2D_C_N<12>

PEG_R2D_C_P<13>

PEG_R2D_C_P<12>

PEG_R2D_C_N<11>

PEG_R2D_C_P<11>

PEG_R2D_C_N<10>

PEG_R2D_C_P<10>

PEG_R2D_C_N<9>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_C_N<4>

PEG_R2D_C_P<4>

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_P<15>

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_P<12>

PEG_R2D_P<11>

PEG_R2D_P<10>

PEG_R2D_P<9>

PEG_R2D_P<8>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_N<15>

PEG_R2D_N<14>

PEG_R2D_N<13>

PEG_R2D_N<12>

PEG_R2D_N<10>

PEG_R2D_N<11>

PEG_R2D_N<7>

PEG_R2D_N<8>

PEG_R2D_N<9>

PEG_R2D_N<5>

PEG_R2D_N<6>

PEG_R2D_N<3>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_R2D_N<0>

GPU_PCIE_CALI

GPU_PCIE_CALRP

PEG_R2D_C_N<14>

PEG_R2D_C_P<14>

PEG_R2D_C_N<13>

PEG_R2D_C_P<5>

PEG_R2D_N<4>

PEG_D2R_C_N<2>

=PP1V2_S0_PCIE_GPU_VDDR

PEG_R2D_C_P<9>

PEG_R2D_P<5>

PEG_D2R_N<12>

PEG_D2R_N<1>

PP1V2_S0_PCIE_GPU_PVDD_F


=PP1V2_S0_PCIE_GPU_PVDD

63

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

34

26

34

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

63

13

13

13

63

www.vinafix.vn

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOODCOMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

PGEN

VIN

ADJ

VOUT

GND

G

D

S

OUT

G

D

S

G

D

S

G

D

S

CAP-

FB

OUT

SHDN_L

CAP+

LIN/SKIP_L

IN

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

GPU VCore Current Sense

Back-bias negative supply provides VSS - 0.55V when active.

Vout = -0.55V

(Q8520 limit)17A max outputVout = 1.10V / 0.95V

<Rb> Recommended values:Ra = Vin / 50 uARb = -Vout / 50 uA

Back-Bias Negative SupplyWhen inactive, provides VSS to BBN pins.

(LDO limit)180mA max outputVout = (1.58V /) 1.50V

Req = Rb || Rc

Vout(low) = 0.59V * (1 + Ra/Rb)

<Rc>

(GPUVCORE_FB)

Keep C8590, R8590,R8594 and R8597

<Ra>

Vout(low) = 0.6V * (1 + Ra / Rb)

Placement Note:

GPU VCore Supply

close to inductor

125mA max output(Regulator limit)

Vout = -Vin * Rb / Ra

<Ra>

NC

satisfy BBP FET Vgs (where Vs = 1.2V)

<Ra>

<Rb>

When inactive, provides VDDC to BBP pins.

For proper M56 power sequence, this Vin must be > 2.8VSI3446DV max Vgs is 1.6V

Pull-up voltage must be high enough to

NOTE: BBP tracks VDDC based on GPU voltage GPIO.

pull-up must be powered before VCore

Vout(high) = 0.59V * (1 + Ra/Req)

Req = Rb || RcVout(high) = 0.6V * (1 + Ra / Req)

Back-bias positive supply provides VDDC + 0.5V when active.

Back-Bias Positive Supply

<Rb>

<Rc>

330uF

POLYCASE-D2E-LF

20%2.5V-ESR9V 2

1C85423.01K1/16WMF-LF

1%

4022

1R8521

1/16WMF-LF

5.11K1%

4022

1R8522

1210X7R20%16V22uF

2

1 C8532

CRITICAL

1.0uH-20.5

SM1

3

2

1

L8520

LFPAKHAT2168H

CRITICAL

321

4

5

Q8520

SMBB340LBXF

CRITICAL 2

1

D8520HAT2165HLFPAK

CRITICAL

321

4

5

Q8522

1/16W1%

3.01K

402MF-LF

21

R8510

CERM1

2.2UF6.3V20%

6032

1C8502

6.3VCERM1

20%

603

2.2UF2

1C850060316V10%X5R

1uF2

1C8501

QFNISL6269

CRITICAL

8

1

2

14

17

12

1516

10

11

9

7

3

6

4

5

13

U8500

CERM40250V

15pF5%

2

1C8507

MF-LF402

1%1/16W

150K

2

1R8508

10%

40250V

CERM

470pF2

1C8508

1/16W

0

MF-LF5%

4022

1R8504

NO STUFF

MF-LF402

5%1/16W

0

2

1R85051/16W1%

402MF-LF

57.6K

2

1R8506

16V10%

402CERM

0.01UF2

1C8506

X7R

22uF

1210

20%16V2

1 C853120%22uF16VX7R1210

2

1 C8530

6.3V20%X5R805

22uF2

1C8540

22uF

X5R20%6.3V805

2

1 C8541

LFPAKHAT2165H

CRITICAL

321

4

5

Q8521

SM21

XW8500

NO STUFF

10%

402X7R

1000pF25V 2

1C8522NO STUFF

1000pF

X7R10%25V402

2

1 C8521

22uF

X5R805

20%6.3V 2

1C8556

22uF20%X5R6.3V805

2

1 C8557

1/16WMF-LF402

1%24.9K

2

1R8555

16.2K1/16W1%

402MF-LF

2

1R8556

16V10%

402CERM

0.01UF2

1C8555

FAN2558SOT23-6-LF

CRITICAL

614

2

3 5

U8550

CERM1603

2.2uF6.3V20%

2

1C8551

330uF20%2.5V-ESR9VCASE-D2E-LFPOLY2

1C8543

12.4K

402

1%

MF-LF1/16W

21

R8523

NO STUFF

1/16W5%MF-LF

0

4022

1R8502

1/16W5%

402MF-LF

10K

2

1R8560

2N7002SOT23-LF

2

1

3

Q8570

100K

MF-LF5%

1/16W4022

1R8570

50V0.0022uF10%

402CERM2

1 C8570GPU_BB_CTL

0

MF-LF402

5%1/16W

21

R8561

50V

470pF

402CERM

10%

2 1

C8598

51

402

50V

470pF

CERM

10%

2 1

C8592

402MF-LF

1M

1%1/16W

21

R8598

LMV2011MFSOT23-5

2

5

1

4

3

U8595

402

1M

1%

MF-LF1/16W

21

R8592

1uF

CERM402

10%6.3V2

1 C8595

20.0K

MF-LF402

1/16W1%

21

R8593

20.0K

1%MF-LF402

1/16W

21

R8591

1/16WMF-LF

402

1%649

2

1R8590

1%

1K

402MF-LF1/16W

NO STUFF

21

R8594

CERM

10%

402

1uF

6.3V

2 1

C8590

10KOHM-5%

CRITICAL

0603-LF

2

1

R8597

402MF-LF1/16W

1K1%

2

1R8596

NO STUFF

1%1/16W

174K

402MF-LF

2

1R8554

CERM-X5R

0.022uF16V10%

4022

1C8523

5%1/16WMF-LF

402

10K

2

1R8524

10K

402MF-LF

5%1/16W

21

R8525

0.0022uF

NO STUFF

10%50V

CERM402

2

1C8520

10K

MF-LF1/16W

5%

4022

1R8526

2N7002DW-X-FSOT-363

4

5

3

Q8523

2N7002DW-X-FSOT-363

1

2

6

Q8523

NO STUFF

2N7002SOT23-LF

2

1

3

Q8554 68.1K

402

1/16WMF-LF

1%

2

1R8587

11.3K1%

402

1/16WMF-LF

2

1R85882.2uF

603CERM16.3V20%

2

1 C8581

6.3VX5R

10uF20%

6032

1C8580

805

22uF

X5R20%6.3V2

1 C8589

CRITICALSOI

MAX1673

4

5

1

8

7

62

3

U8580

SI3446DVTSOP-LF

4

3 6

5

2

1

Q8575

1/16W5%

402MF-LF

0

NO STUFF

2

1R8520

0.22UF

402X5R6.3V20%

2

1 C8509

402MF-LF1/16W

05%

2

1R8509

051-6941


104

A

85

GPU (M56) Core SuppliesSYNC_DATE=(MASTER)

GND_GPUVCORE_SGND

GPUBBP_ADJ

GPUBB_EN_L

=PPVCORE_S0_GPU_BBP

GPUBB_EN_L

=PPVOUT_S0_GPUBBP_LDO

GPUBB_ENGPU_GENERICD

=PP5V_S0_GPUBBCTL

GPU_VCORE_HIGH

GPUBB_EN

=PP3V3_S0_GPUBBP

GPUBBP_ADJ_LOW

GPUVCORE_COMP_R

GPUVCORE_FSET

GPUVCORE_COMP

GPUVCORE_FCCM=GPUVCORE_EN

=GPUVCORE_PGOOD

=PP3V3R5V_S0_GPUISENS

GPUVCORE_IOUT


GPUVCORE_LGMIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mmGPUVCORE_UG


GPUVCORE_ISEN

GPU_VCORE_HIGH

GPU_VCORE_LOW

GPU_VCORE_HIGH_RC

=PP3V3_S0_GPUBBN

GPUBBN_CAPNMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

GPUBBN_CAPPMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

GPUBB_EN

PP5V_S0_GPUVCORE_VCC


MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmGPUVCORE_BOOT

GPUVCORE_BOOT_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

GPUISENS_RC

GPUISENS_NEG

GPUISENS_POS

GPUVCORE_FB_RC

GPUVCORE_FB_LOW

GPUISENS_NTC

=PP5V_S0_GPUVCORE=PPVIN_S0_GPUVCORE

GPUVCORE_PHASE


=PNVOUT_S0_GPUBBN_REG

=PP3V3_S0_GPU

GPUVCORE_FB

GPUBBN_FB

=PPVCORE_S0_GPU_REG

72 69

5

66

63

66

63

66

72

63

66

66

63

5

5

62

62

63

66

69

63

66

63

63

63

63

63

www.vinafix.vn

MEMORY & CORE POWER / GROUND

(1.0V/1.2V)

(1.0V/1.2V)

(7 OF 7)

VDDR1VSS

VSS

(1.8V/2.0V) VSS

VDDC

BBP BBN

VDDCI

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

100mA (Preliminary)

100mA (Preliminary)

2.0A @ 500MHz 1.8V GDDR3

14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

- =PP1V5_GPU_VDD15Power aliases required by this page:

Page Notes



- =PP1VR1V3_GPU_VCORE

(NONE)

(NONE)

OMIT

BGAM56P

P17P15P7P6P5P1N8N7N3M32

A31

M28M24M9M8M7M6

M3L29L7L6

A25

L1K30K27K17K16K12K10J30J28J24

A22

J21J16J12J9J6J3H32H28H21H20

A19

H16H7H5H1G25G22G21G20G19G16

A16

G13F30F27F24F22F21F19F18

F16F15

A13

F13F10F6F3E32E30E28E25E19E16

A11

E13E12E9E8E5D30D11C27C24C21

A8

C20C18C15C10

AM13AM2AL13AL1AK16AJ10AH16AH11AH10

C9

AG23AG16AG11AF16AF14AE17AE16AE15AE14AE8

C6

AD17AD16AD15AD14AD13AD10AD9AD8AD7AD6C5AC10AC9AA6AA4Y7Y6Y5Y1W18W16

C4

V19V17V6V3U18U14U10U9U8U7

B32

U6U5U1T19T15T10R16R14R6R3

B1

A2K23

C32C1A30A24A21

AA1Y10Y9Y8

A18

V1R9R1P10P9P8N10N9M10M1

A15

L32L24L23K24K21K20K19K13K11J32

A12

J20J19J18J13J11J10J1H19H13F32

A9A3

W17W10U19T23T14P16K14

T18T17T16R19R18R17R15

AD11AC12AC11

P19

W19W15W14V18V16V15V14U17U16U15

P18P14

AC14V10M23K18

AC17Y23R10K15

U8400

0.1uF

402X5R16V10%

2

1C869710%

402

1uF

CERM6.3V 2

1C8696

10%

402

1uF

CERM6.3V2

1 C86910.1uF

402X5R16V10%

2

1 C8692

CERM6.3V

1uF

402

10%2

1 C86106.3VCERM

1uF

402

10%2

1 C86096.3VCERM

1uF

402

10%2

1 C86086.3VCERM

1uF

402

10%2

1 C86076.3VCERM

1uF

402

10%2

1 C86066.3VCERM

1uF

402

10%2

1 C8605

402

6.3VCERM

1uF10%

2

1 C8604

10%

402

1uF

CERM6.3V2

1 C861610%

402

1uF

CERM6.3V2

1 C861510%

402

1uF

CERM6.3V2

1 C861410%

402

1uF

CERM6.3V2

1 C861310%

402

1uF

CERM6.3V2

1 C8612

1/10W

603

05%

MF-LF2

1R8630

6.3VCERM

1uF

402

10%2

1 C86346.3VCERM

1uF

402

10%2

1 C86336.3VCERM

1uF

402

10%2

1 C86326.3VCERM

1uF

402

10%2

1 C8631

6.3VCERM

1uF

402

10%2

1 C8660

10%

402

1uF

CERM6.3V2

1 C8666

6.3VCERM

1uF

402

10%2

1 C86596.3VCERM

1uF

402

10%2

1 C86586.3VCERM

1uF

402

10%2

1 C8657

10%

402

1uF

CERM6.3V2

1 C866510%

402

1uF

CERM6.3V2

1 C866410%

402

1uF

CERM6.3V2

1 C8663

6.3VCERM

1uF

402

10%2

1 C8656

10%

402

1uF

CERM6.3V2

1 C8662

6.3VCERM

1uF

402

10%2

1 C8655

10%

402

1uF

CERM6.3V2

1 C8661

6.3VCERM

1uF

402

10%2

1 C8672

10%

402

1uF

CERM6.3V2

1 C8678

6.3VCERM

1uF

402

10%2

1 C86716.3VCERM

1uF

402

10%2

1 C86706.3VCERM

1uF

402

10%2

1 C8669

10%

402

1uF

CERM6.3V2

1 C867710%

402

1uF

CERM6.3V2

1 C867610%

402

1uF

CERM6.3V2

1 C8675

6.3VCERM

1uF

402

10%2

1 C8668

10%

402

1uF

CERM6.3V2

1 C8674

CERM6.3V

1uF

402

10%2

1 C8667

10%

402

1uF

CERM6.3V2

1 C8673

6.3VX5R

22uF

805

20%2

1C865320%

6.3VX5R805

22uF2

1C8652

X5R6.3V

22uF

805

20%2

1C865122uF

805X5R

6.3V20%

2

1C8650

10%

402

1uF

CERM6.3V2

1 C868310%

402

1uF

CERM6.3V2

1 C868210%

402

1uF

CERM6.3V2

1 C868110%

402

1uF

CERM6.3V2

1 C86806.3VCERM

1uF

402

10%2

1 C8679

22uF

805X5R

6.3V20%

2

1C8601

6.3VCERM

1uF

402

10%2

1 C8611

20%6.3VX5R805

22uF2

1C869020%6.3VX5R805

22uF2

1 C8695

20%6.3VX5R805

22uF2

1C8630

20%6.3VX5R805

22uF2

1C8600

ATI M56 Core PowerSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

A051-6941

10486

=PNBB_S0_GPU

=PP1V8R2V0_S0_FB_GPU

=PPBB_S0_GPU

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

PPVCORE_S0_GPU_VDDCIVOLTAGE=1.2V

=PPVCORE_S0_GPU72

68

63

63

63

63

51

www.vinafix.vn

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DQA_58DQA_59

WEA1*

DQA_61DQA_62

MVREFD_0MVREFS_0

VDDRH0

MAA_0MAA_1MAA_2MAA_3MAA_4MAA_5MAA_6MAA_7MAA_8MAA_9MAA_10MAA_11MAA_12MAA_13MAA_14MAA_15

DQMA_0*DQMA_1*DQMA_2*DQMA_3*DQMA_4*DQMA_5*DQMA_6*DQMA_7*

QSA_1QSA_2

QSA_0

QSA_3QSA_4QSA_5QSA_6QSA_7

QSA_0*QSA_1*QSA_2*QSA_3*QSA_4*QSA_5*QSA_6*QSA_7*

CLKA0CLKA0*

CSA0_0*

CKEA0

RASA0*

CASA0*

WEA0*

ODTA0

CLKA1*

CSA1_0*

CKEA1

RASA1*

CASA1*

ODTA1

DQA_0DQA_1DQA_2DQA_3DQA_4DQA_5DQA_6DQA_7DQA_8DQA_9DQA_10DQA_11DQA_12DQA_13DQA_14DQA_15DQA_16DQA_17DQA_18DQA_19DQA_20DQA_21DQA_22DQA_23DQA_24DQA_25DQA_26DQA_27DQA_28DQA_29DQA_30DQA_31DQA_32DQA_33DQA_34DQA_35DQA_36DQA_37DQA_38DQA_39DQA_40DQA_41DQA_42DQA_43

DQA_45DQA_44

DQA_46DQA_47DQA_48

DQA_50DQA_51

DQA_49

DQA_52DQA_53DQA_54DQA_55DQA_56DQA_57

DQA_60

DQA_63

VSSRH0

CLKA1

CSA0_1*

CSA1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE A

(3 OF 7)

2.0V)(1.8V/

DQB_62

VDDRH1

MVREFS_1

MAB_0MAB_1MAB_2MAB_3MAB_4MAB_5MAB_6MAB_7MAB_8MAB_9MAB_10MAB_11MAB_12

MAB_15MAB_14MAB_13

DQMB_0*DQMB_1*DQMB_2*DQMB_3*DQMB_4*DQMB_5*DQMB_6*DQMB_7*

QSB_0QSB_1QSB_2

QSB_4QSB_3

QSB_5QSB_6QSB_7

QSB_0*QSB_1*QSB_2*QSB_3*QSB_4*QSB_5*QSB_6*QSB_7*

CLKB0*CLKB0

CSB0_0*

CKEB0

RASB0*

WEB0*

CASB0*

ODTB0

CLKB1CLKB1*

CKEB1

RASB1*

WEB1*

CASB1*

ODTB1

DRAM_RST

DQB_0DQB_1DQB_2DQB_3DQB_4DQB_5DQB_6DQB_7DQB_8DQB_9DQB_10DQB_11DQB_12

DQB_15DQB_14DQB_13

DQB_16DQB_17DQB_18

DQB_20DQB_19

DQB_22DQB_21

DQB_23

DQB_25DQB_24

DQB_27DQB_26

DQB_28

DQB_30DQB_29

DQB_33

DQB_31DQB_32

DQB_35DQB_34

DQB_37DQB_36

DQB_38

DQB_40DQB_41DQB_42DQB_43DQB_44DQB_45DQB_46

DQB_48DQB_47

DQB_52DQB_53

DQB_56DQB_55DQB_54

DQB_58DQB_57

DQB_60DQB_59

DQB_61

DQB_63

MVREFD_1

VSSRH1

TEST_MCLKTEST_YCLKMEMTEST

DQB_39

CSB1_0*

DQB_51DQB_50DQB_49

CSB0_1*

CSB1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE B

(4 OF 7)

(1.8V/ 2.0V)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Page Notes

NC

NCNC

NC

(NONE)

(NONE)




- =PP1V8R2V0_S0_FB_GPU

1%1/16WMF-LF402

40.2

2

1R87221%

1/16WMF-LF

402

40.2

2

1R8720

0.1uF

402X5R16V10%

2

1 C8723100

402MF-LF1/16W1%

2

1R87231/16W

100

402MF-LF

1%

2

1R8721

16V

0.1uF

402X5R

10%2

1C872110%16VX5R402

0.1uF2

1 C8713

1%1/16WMF-LF402

40.2

2

1R8712

100

402MF-LF

1%1/16W

2

1R8713

402X5R16V10%

0.1uF2

1C8711

1%1/16WMF-LF

402

40.2

2

1R8710

100

402MF-LF1/16W

1%

2

1R8711

402

2431%1/16WMF-LF

2

1R8732

MF-LF1/16W

5%4.7K

4022

1R8731

4.7K

402

5%1/16WMF-LF

2

1R8730

5%1/16WMF-LF402

4.7K

2

1R8733

M56PBGA

OMIT

B21

B31

A28A27

B24

B28

J15

H15

D15

D16

C16

B16

D21

D20

G24

F23

K26

K25

K28

K29

K31

J31

D24

F29

C30C31

B26C26F25D27E26E24D25D28

C25B25E29E27B27D29

F28D26

J17D14B15E21G23J26J29H31

M29M27F31

J14H14G14G15

G30

G17G18H17H18D13F14E14E15F17E17

G31

E18D17B13C13B14C14B17C17B18B19

H30

D18D19F20E20E22D23D22E23J22J23

L30

H22H23H24H25G26F26H26H27G28J25

L31

L25M25L26M26G27G29H29J27L27L28

M30M31

C23B23

C28B29

C19B20

E31D31

C22

B30

B22

C29

U8400M56PBGA

OMIT

M2

B2

E1F1

AA2AA5

J2

E2

V9

V8

V4

U4

U3

U2

M4

N4

J7

K6

G10

H10

E10

D10

B10

B9

J4

D6

C3B3

AA7

G2G3H6F4G5J5H4E4

H3H2D5F5F2D4

E6G4

AA3

T9W4V2M5K7G9D9B8

D12F12B6

W9W8W7V7

C7

T7R7T8R8Y4W6W5V5T6T5

B7

R5T4Y2Y3W2W3T2T3R2P2

C8

R4P4N6N5L5K4L4K5L9K9

C11

L8K8J8H8G7G6G8F8E7H9

B11

H11H12G11G12F7D7D8F9F11E11

C12B12

K3K2

E3D2

P3N2

B5B4

L3

C2

L2

D3

U8400

6.3V

402

10%

CERM

1uF2

1C871610%

402CERM6.3V

1uF2

1C871510%

402

1uF

CERM6.3V 2

1C87266.3VCERM

1uF

402

10%2

1C8725

FERR-220-OHM

0402

21

L8725FERR-220-OHM

0402

21

L8715

SM21

XW8725SM

21

XW8715


ATI M56 Frame Buffer I/FSYNC_DATE=(MASTER)

A051-6941

10487


GND_GPU_VSSRH0

GPU_MVREFS0

FB_A_DQ<57>

FB_A_DQM_L<5>

FB_A_DQ<60>

FB_A_WDQS<7>FB_A_WDQS<6>FB_A_WDQS<5>FB_A_WDQS<4>

FB_A_WDQS<2>FB_A_WDQS<3>


FB_A_RDQS<6>FB_A_RDQS<7>

FB_A_RDQS<5>FB_A_RDQS<4>FB_A_RDQS<3>FB_A_RDQS<2>FB_A_RDQS<1>FB_A_RDQS<0>

FB_A_DQM_L<6>FB_A_DQM_L<7>

FB_A_BA<1>

FB_A_MA<10>

FB_A_MA<8>FB_A_MA<9>

FB_A_CLK_P<1>

FB_A_DQ<63>

FB_A_DQ<56>FB_A_DQ<55>FB_A_DQ<54>FB_A_DQ<53>FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>FB_A_DQ<50>

FB_A_DQ<48>FB_A_DQ<47>FB_A_DQ<46>


FB_A_DQ<43>FB_A_DQ<42>FB_A_DQ<41>FB_A_DQ<40>FB_A_DQ<39>FB_A_DQ<38>FB_A_DQ<37>FB_A_DQ<36>FB_A_DQ<35>FB_A_DQ<34>FB_A_DQ<33>FB_A_DQ<32>FB_A_DQ<31>FB_A_DQ<30>FB_A_DQ<29>FB_A_DQ<28>FB_A_DQ<27>FB_A_DQ<26>FB_A_DQ<25>FB_A_DQ<24>FB_A_DQ<23>FB_A_DQ<22>FB_A_DQ<21>FB_A_DQ<20>FB_A_DQ<19>FB_A_DQ<18>FB_A_DQ<17>FB_A_DQ<16>FB_A_DQ<15>FB_A_DQ<14>FB_A_DQ<13>FB_A_DQ<12>FB_A_DQ<11>FB_A_DQ<10>FB_A_DQ<9>FB_A_DQ<8>FB_A_DQ<7>FB_A_DQ<6>FB_A_DQ<5>FB_A_DQ<4>FB_A_DQ<3>FB_A_DQ<2>FB_A_DQ<1>

TP_FB_A_ODT<1>

FB_A_CAS_L<1>

FB_A_RAS_L<1>

FB_A_CKE<1>

FB_A_CS_L<1>

FB_A_CLK_N<1>

TP_FB_A_ODT<0>

FB_A_WE_L<0>

FB_A_CAS_L<0>

FB_A_RAS_L<0>

FB_A_CKE<0>

FB_A_DQM_L<4>FB_A_DQM_L<3>FB_A_DQM_L<2>FB_A_DQM_L<1>FB_A_DQM_L<0>

TP_FB_A_MA12FB_A_MA<11>

FB_A_MA<7>FB_A_MA<6>FB_A_MA<5>

FB_A_MA<2>FB_A_MA<1>FB_A_MA<0>

GPU_MVREFD0


FB_A_WE_L<1>


FB_B_DQ<49>FB_B_DQ<50>FB_B_DQ<51>

FB_B_CS_L<1>

FB_B_DQ<39>

GPU_MEMTESTGPU_TEST_YCLKGPU_TEST_MCLK

GPU_MVREFD1

FB_B_DQ<63>

FB_B_DQ<61>

FB_B_DQ<59>FB_B_DQ<60>





FB_B_DQ<46>FB_B_DQ<45>FB_B_DQ<44>FB_B_DQ<43>FB_B_DQ<42>FB_B_DQ<41>FB_B_DQ<40>

FB_B_DQ<38>




FB_B_DQ<33>


FB_B_DQ<28>



FB_B_DQ<23>



FB_B_DQ<16>


FB_B_DQ<12>FB_B_DQ<11>FB_B_DQ<10>FB_B_DQ<9>FB_B_DQ<8>FB_B_DQ<7>FB_B_DQ<6>FB_B_DQ<5>FB_B_DQ<4>FB_B_DQ<3>FB_B_DQ<2>FB_B_DQ<1>FB_B_DQ<0>

FB_DRAM_RST

TP_FB_B_ODT<1>

FB_B_CAS_L<1>

FB_B_WE_L<1>

FB_B_RAS_L<1>

FB_B_CKE<1>

FB_B_CLK_N<1>FB_B_CLK_P<1>

TP_FB_B_ODT<0>

FB_B_CAS_L<0>

FB_B_WE_L<0>

FB_B_RAS_L<0>

FB_B_CKE<0>

FB_B_CS_L<0>

FB_B_CLK_P<0>FB_B_CLK_N<0>

FB_B_WDQS<7>FB_B_WDQS<6>FB_B_WDQS<5>FB_B_WDQS<4>FB_B_WDQS<3>FB_B_WDQS<2>FB_B_WDQS<1>FB_B_WDQS<0>

FB_B_RDQS<7>FB_B_RDQS<6>FB_B_RDQS<5>

FB_B_RDQS<3>FB_B_RDQS<4>


FB_B_DQM_L<7>FB_B_DQM_L<6>FB_B_DQM_L<5>FB_B_DQM_L<4>FB_B_DQM_L<3>FB_B_DQM_L<2>FB_B_DQM_L<1>FB_B_DQM_L<0>

FB_B_BA<2>FB_B_BA<0>FB_B_BA<1>

TP_FB_B_MA12

FB_B_MA<9>FB_B_MA<8>FB_B_MA<7>FB_B_MA<6>FB_B_MA<5>FB_B_MA<4>FB_B_MA<3>FB_B_MA<2>FB_B_MA<1>FB_B_MA<0>

GPU_MVREFS1

FB_B_DQ<62>

FB_A_DQ<0>


FB_B_MA<10>FB_B_MA<11>

FB_A_BA<0>

FB_A_CLK_N<0>

=PP1V8R2V0_S0_FB_GPU =PP1V8R2V0_S0_FB_GPU

GND_GPU_VSSRH1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

FB_A_BA<2>

FB_A_CS_L<0>

FB_A_CLK_P<0>


PP1V8R2V0_S0_GPU_VDDRH1


=PP1V8R2V0_S0_FB_GPUVOLTAGE=1.8VPP1V8R2V0_S0_GPU_VDDRH0

MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm=PP1V8R2V0_S0_FB_GPU

68 68

68 68

71

67 67

67 67

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

69

70

70

70

70

70

70

70

70

70

70

70

70

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

70

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

69

71

71

71

71

71

71

71

71

71

71

71

70

70

70

71

71

70

70

63 63

70

70

70

71

71

63 63

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Thm Mon Int

SS_IN

TESTOUT[9] ROMIDCFG[0]

IPD

ENA_BL TESTIN[7]

ROMSO TESTWR Reserved

ROMSI ROMIDCFG[3]

ROMSCK TESTOUT[8]


IPD

IPD

IPD

IPD

TESTIN[8]

IPD

TESTIN[1] TX_DEEMPH_EN

Serial ROM TestBus Misc Straps

IPD

TESTIN[9] PWRCNTL

TESTIN[4] DEBUG_ACCESS


VDD_VCL TESTIN[2] Reserved

TESTIN[3] Reserved

TESTIN[5] Reserved

TESTIN[6] Reserved

TESTIN[0] TX_PWRS_ENb

Unused signals

Renamed signals

Also required: GPIO10 - GPIO13

Required for debug access

ROMCFGID[3..0]

0100 = 64MB0110 = Reserved

0010 = 256MB0000 = 128MB





402MF-LF

10K5%

1/16W

2

1R8800

GPU_DEEPMH_EN

10K5%1/16WMF-LF4022

1R8801

MF-LF

5%1/16W

10K

402

NO STUFF

2

1R8802

5%1/16WMF-LF402

10K

NO STUFF

2

1R8803

5%10K1/16W

402MF-LF

NO STUFF

2

1R8806

402

1/16W5%

10K

MF-LF

NO STUFF

2

1R8804

1/16WMF-LF

10K

402

5%

NO STUFF

2

1R880810K

402MF-LF1/16W5%

2

1R8805

5%

GPU_MEM_256M

1/16WMF-LF

402

10K

2

1R88121/16WMF-LF

402

5%10K

NO STUFF

2

1R8809

NO STUFF

5%1/16W

10K

402MF-LF

2

1R8811

402MF-LF

10K1/16W5%

GPU_MEM_64M

2

1R8813

1/16W402

MF-LF

4.7K5%

2

1R9391

MF-LF402

1/16W

4.7K5%

2

1R9390

MF-LF402

1/16W

10K5%

GPU_MEM_256M

2

1R8824

1/16WMF-LF

10K

402

5%

GPU_MEM_HYNIX

2

1R8827

GPU StrapsSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-6941 A

10488

=PP3V3_S0_GPU_GPIOS

MAKE_BASE=TRUEGPU_MEMID

MAKE_BASE=TRUEGPU_MEM_256M

GPU_GPIO_13

GPU_GPIO_2

GPU_GPIO_9

GPU_GPIO_3

GPU_GPIO_11

GPU_GPIO_6

GPU_GPIO_8

GPU_GPIO_12

GPU_GPIO_4

GPU_GPIO_5

MAKE_BASE=TRUETP_ATI_DVPDATA<23..16> ATI_DVPDATA<23..16>

MAKE_BASE=TRUEGPU_CLK27M GPU_XTALIN

MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_XTALOUT GPU_XTALOUT

MAKE_BASE=TRUE NO_TEST=TRUENC_ATI_ROMCS_L TP_ATI_ROMCS_L

MAKE_BASE=TRUE NO_TEST=TRUENC_FB_A_MA12 TP_FB_A_MA12

MAKE_BASE=TRUE NO_TEST=TRUENC_FB_B_MA12 TP_FB_B_MA12

NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_GENERICA GPU_GENERICA

MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GENERICB GPU_GENERICB

NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_GENERICC GPU_GENERICC

NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_VGA_G GPU_VGA_GMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_VGA_R GPU_VGA_R

NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_VGA_B GPU_VGA_B

MAKE_BASE=TRUETP_GPU_VGA_HSYNC GPU_VGA_HSYNC

MAKE_BASE=TRUETP_GPU_VGA_VSYNC GPU_VGA_VSYNC

MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_TV_C GPU_TV_C

NO_TEST=TRUEMAKE_BASE=TRUENC_GPU_TV_Y GPU_TV_Y

MAKE_BASE=TRUE NO_TEST=TRUENC_GPU_TV_COMP GPU_TV_COMP

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_U_DATAP<3> LVDS_U_DATA_P<3>

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_U_DATAN<3> LVDS_U_DATA_N<3>

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_L_DATAP<3> LVDS_L_DATA_P<3>

NO_TEST=TRUEMAKE_BASE=TRUENC_ATI_DVPCLK ATI_DVPCLK

NO_TEST=TRUEMAKE_BASE=TRUENC_LVDS_L_DATAN<3> LVDS_L_DATA_N<3>

MAKE_BASE=TRUE NO_TEST=TRUENC_ATI_DVPCNTL<2..0> ATI_DVPCNTL<2..0>

MAKE_BASE=TRUE NO_TEST=TRUENC_ATI_DVPDATA<15..0> ATI_DVPDATA<15..0>

=PP3V3_S0_GPU

GPU_DDC_B_DATAGPU_DDC_B_CLK

MAKE_BASE=TRUEGPU_VCORE_LOW

GPU_GPIO_27

GPU_GPIO_24


NC_GPU_GPIO_25

NC_GPU_GPIO_21MAKE_BASE=TRUENO_TEST=TRUE

GPU_GPIO_1

GPU_GPIO_0

MAKE_BASE=TRUEGPU_BLON

TP_GPU_GPIO_10MAKE_BASE=TRUE

MAKE_BASE=TRUEGPU_CLK27MSS_IN

GPU_GPIO_32

GPU_GPIO_33

GPU_GPIO_34

GPU_GPIO_29

GPU_GPIO_30

GPU_GPIO_31

GPU_GPIO_28

GPU_GPIO_25

GPU_GPIO_26

GPU_GPIO_22

GPU_GPIO_23

GPU_GPIO_21

GPU_GPIO_15MAKE_BASE=TRUENC_GPU_GPIO_14 NO_TEST=TRUE

MAKE_BASE=TRUENC_GPU_GPIO_17 NO_TEST=TRUE

MAKE_BASE=TRUENC_GPU_GPIO_18

NO_TEST=TRUE


NC_GPU_GPIO_20NO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_GPIO_19

NO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_GPIO_23

NO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_GPIO_26


NC_GPU_GPIO_28


NC_GPU_GPIO_31NO_TEST=TRUE

NC_GPU_GPIO_30MAKE_BASE=TRUE


NC_GPU_GPIO_29




NC_GPU_GPIO_32


NC_GPU_GPIO_22

GPU_GPIO_10

GPU_GPIO_7

GPU_GPIO_14

GPU_GPIO_20

GPU_GPIO_19

GPU_GPIO_18

GPU_GPIO_17

GPU_GPIO_16

72 66

63

72

72

72

72

72

72

72

72

72

72

72

34 72

72

72

68

68

72

72

72

73

73

73

73

73

73

73

73

73

73

73

72

73

72

72

63

73

73

66

72

72

72

72

74

34

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

www.vinafix.vn

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8DQ7

DQ9

DQ10DQ11

DQ12DQ13

DQ14

DQ15DQ16

DQ17

DQ18DQ19

DQ20

DQ21

DQ24DQ23

DQ22

DQ25

DQ26DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3RDQS2

RDQS1RDQS0

SEN

RESET

MFZQ

RAS*

CAS*WE*

CS*CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1RFU2

DM3DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1VSS2

VSS5

VSS3

VSS4

VSS7VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9VSSQ10

VSSQ11

VSSQ12VSSQ13

VSSQ14

VSSQ16VSSQ15

VSSQ17VSSQ18

VSSQ19VDDQ19

VDDQ20VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6VDDQ7

VDDQ8

VDD0

VDD1VDD2

VDD5

VDD3

VDD4

VDD6VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8DQ7

DQ9

DQ10DQ11

DQ12DQ13

DQ14

DQ15DQ16

DQ17

DQ18DQ19

DQ20

DQ21

DQ24DQ23

DQ22

DQ25

DQ26DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3RDQS2

RDQS1RDQS0

SEN

RESET

MFZQ

RAS*

CAS*WE*

CS*CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1RFU2

DM3DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1VSS2

VSS5

VSS3

VSS4

VSS7VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9VSSQ10

VSSQ11

VSSQ12VSSQ13

VSSQ14

VSSQ16VSSQ15

VSSQ17VSSQ18

VSSQ19VDDQ19

VDDQ20VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6VDDQ7

VDDQ8

VDD0

VDD1VDD2

VDD5

VDD3

VDD4

VDD6VDD7

VDDA0

(2 OF 2)

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IO

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE




Page Notes

NOTE: U8900 DQ0-7 MUST connect to GPU

within byte-lane, but software must know

U8900.J12U8900.J1Connect to designated pin, then GND

NCNCNC

NC

U8900.J1 U8900.J12

- =PP1V8_S0_FB_VDDQ- =PP1V8_S0_FB_VDD

(NONE)

(NONE)

GDDR3 vendor/device identification scheme.how these bits are mapped for GPU to support

DQA0-7 or DQA8-15. Bits can be swapped

Connect to designated pin, then GND

1/16W1%

402MF-LF

2.37K

2

1R8930

4021/16W

1%MF-LF

5.49K

2

1R8931

16V10%

402X5R

0.1uF2

1 C89030.1uF16V10%

402X5R2

1 C890216V10%

402X5R

0.1uF2

1 C890416V10%

402X5R

0.1uF2

1 C8901

16V10%

402X5R

0.1uF2

1 C8922

X5R16V10%

402

0.1uF2

1 C892316V10%

402X5R

0.1uF2

1 C892416V10%

402X5R

0.1uF2

1 C89250.1uF16V10%

402X5R2

1 C8926

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMITCRITICAL

FBGA

A4

H4

P2

P11D11

D2

V4

J3

J2

V9

P3

P10D10

D3

H10

A9

B10B11

G3F2

F3

E2

T3T2

C3

R3R2

M3

N2L3

M2

T10T11

R10

R11

C2

M10

N11L10

M11

G10F11

F10

E11C10

C11

B3B2

N3

N10

E10E3

F4

H9

J10

J11

F9

H3

G4G9

M4

K2

L4K3

H2

K4M9

K10

L9

K11

H11K9 U8900

OMITCRITICAL

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

G11

G2D12

D9

D4D1

B12

B9

T12T9

T4

T1P12

P9

P4P1

L11

L2

B4

B1

J12J1

V10

V3

L12L1

G12

G1A10

A3

H12

H1

E12E9

E4

E1C12

C9C4

V12

V1

C1

R12

R9

R4R1

N12N9

N4

N1J9

J4

A12A1

K12

K1

V11

V2M12

M1F12

F1

A11A2

U8900

1/16W5%

402MF-LF

0

2

1R8949

1/16W

0

MF-LF402

5%

2

1R8941

1/16W1%

402MF-LF

243

2

1R8948

1/16W1%

402MF-LF

60.4

2

1R8945

60.4

MF-LF402

1%1/16W

2

1R8946

0.1uF

X5R402

10%16V2

1 C8933

2.37K

MF-LF402

1%1/16W

2

1R8932

1/16W1%

402MF-LF

5.49K

2

1R8933

10%0.1uF

X5R40216V2

1 C8921

FERR-220-OHM

0402

21

L8910

FERR-220-OHM

0402

21

L8915

16V10%

402X5R

0.1uF2

1 C891510%16V402X5R

0.1uF2

1 C8910

1%121

MF-LF402

1/16W

2

1R8940

1%121

MF-LF4021/16W

2

1R8947

1/16W402

MF-LF

1211%

2

1R8944

MF-LF1%121

4021/16W

2

1R8943

1/16W402

MF-LF

1211%

2

1R8942

1/16W5%

402MF-LF

0

2

1R8991

1/16W402

MF-LF

1211%

2

1R89901%

121

MF-LF402

1/16W

2

1R8992

10%0.1uF

X5R40216V2

1 C89710.1uF

X5R402

10%16V2

1 C8972

243

MF-LF402

1%1/16W

2

1R89980

MF-LF402

5%1/16W

2

1R8999

CRITICALOMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

A4

H4

P2

P11D11

D2

V4

J3

J2

V9

P3

P10D10

D3

H10

A9

B10B11

G3F2

F3

E2

T3T2

C3

R3R2

M3

N2L3

M2

T10T11

R10

R11

C2

M10

N11L10

M11

G10F11

F10

E11C10

C11

B3B2

N3

N10

E10E3

F4

H9

J10

J11

F9

H3

G4G9

M4

K2

L4K3

H2

K4M9

K10

L9

K11

H11K9 U8950

1/16W402MF-LF

1211%

2

1R899360.4

MF-LF402

1%1/16W

2

1R8995

1%121

MF-LF402

1/16W

2

1R8994

1/16W402MF-LF

1211%

2

1R8997

1/16W1%

402MF-LF

60.4

2

1R8996

5.49K

MF-LF402

1%1/16W

2

1R8981

2.37K

MF-LF402

1%1/16W

2

1R8980

5.49K

MF-LF402

1%1/16W

2

1R8983

1/16W1%

402MF-LF

2.37K

2

1R8982

0.1uF

X5R402

10%16V2

1 C8973

0.1uF

X5R402

10%16V2

1 C8981

0.1uF

X5R402

10%16V2

1 C89740.1uF

X5R402

10%16V2

1 C8975

16V10%

402X5R

0.1uF2

1 C8983

CRITICALOMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

G11

G2D12

D9

D4D1

B12

B9

T12T9

T4

T1P12

P9

P4P1

L11

L2

B4

B1

J12J1

V10

V3

L12L1

G12

G1A10

A3

H12

H1

E12E9

E4

E1C12

C9C4

V12

V1

C1

R12

R9

R4R1

N12N9

N4

N1J9

J4

A12A1

K12

K1

V11

V2M12

M1F12

F1

A11A2

U8950

0.1uF

X5R402

10%16V2

1 C8976

0402

FERR-220-OHM21

L89650402

FERR-220-OHM21

L8960

X5R

0.1uF

402

10%16V2

1 C8951

402

0.1uF

X5R10%16V2

1 C8952

0.1uF

X5R402

10%16V2

1 C8960

0.1uF

X5R402

10%16V2

1 C8953

0.1uF

X5R402

10%16V2

1 C8965

0.1uF

X5R402

10%16V2

1 C895422uF

20%

805X5R

6.3V 2

1C8900

X5R

22uF

805

6.3V20%

2

1C8920

20%6.3VX5R805

22uF2

1C8950

805

20%6.3VX5R

22uF2

1C8970

16V10%

402X5R

0.1uF2

1 C8931

GDDR3 Frame Buffer A

89 104

A051-6941


=PP1V8_S0_FB_VDDQ

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A0_VREF0


FB_A_CKE<1>

FB_A_MA<10>

FB_A_MA<8>

FB_A_MA<11>

FB_A_MA<5>

FB_A_DQM_L<4>FB_A_DQM_L<5>FB_A_DQM_L<6>FB_A_DQM_L<7>

FB_A_BA<1>FB_A_BA<0>

FB_A_WDQS<7>

FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>

FB_A_CLK_P<1>


FB_A_MA<2>



FB_A_MA<9>

FB_A_CLK_N<1>FB_A_CS_L<1>FB_A_WE_L<1>FB_A_CAS_L<1>

FB_A1_ZQFB_A1_MF

FB_DRAM_RSTFB_A1_SEN

FB_A_RDQS<4>FB_A_RDQS<5>FB_A_RDQS<6>FB_A_RDQS<7>





FB_A_DQ<55>FB_A_DQ<52>FB_A_DQ<51>FB_A_DQ<50>FB_A_DQ<49>FB_A_DQ<48>FB_A_DQ<45>FB_A_DQ<47>FB_A_DQ<44>

FB_A_DQ<39>

FB_A_DQ<35>

FB_A_DQ<32>

FB_A_MA<10>

FB_A_MA<8>

FB_A_DQM_L<0>

FB_A_DQM_L<2>FB_A_DQM_L<3>


FB_A_WDQS<3>

FB_A_WDQS<0>


FB_A_MA<3>

FB_A_MA<9>

FB_A_CLK_N<0>FB_A_CS_L<0>FB_A_WE_L<0>

FB_A0_ZQFB_A0_MF





FB_A_DQ<21>FB_A_DQ<23>FB_A_DQ<17>FB_A_DQ<18>FB_A_DQ<16>FB_A_DQ<19>FB_A_DQ<13>FB_A_DQ<12>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<11>FB_A_DQ<10>FB_A_DQ<9>


FB_A_DQ<4>




FB_A_MA<7>

FB_A_MA<2>

FB_A_MA<6>

FB_A_MA<11>



=PP1V8_S0_FB_VDDQ

FB_A_RAS_L<1>


FB_A_DQM_L<1>

FB_A_CLK_P<0>

FB_A_RDQS<3>FB_A_RDQS<2>FB_A_RDQS<1>

FB_A0_SEN

FB_A_RDQS<0>

FB_DRAM_RST

FB_A_RAS_L<0>FB_A_CAS_L<0>

FB_A_CKE<0>

FB_A_MA<4>FB_A_MA<5> FB_A_DQ<34>

FB_A_DQ<33>


FB_A_DQ<40>FB_A_DQ<41>FB_A_DQ<42>FB_A_DQ<43>FB_A_DQ<46>


PP1V8_S0_FB_A1_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V


=PP1V8_S0_FB_VDD



=PP1V8_S0_FB_VDD

71

71

71

71

71 71

70

70

70

70

70

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70

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70

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70 70

70

70

70

70 70

63

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

63

68

68 68

68

68

68

68

68

68

68

68

68

68

68

68 68

68

68

68

68

68

68

68

68

68

63 63

www.vinafix.vn

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8DQ7

DQ9

DQ10DQ11

DQ12DQ13

DQ14

DQ15DQ16

DQ17

DQ18DQ19

DQ20

DQ21

DQ24DQ23

DQ22

DQ25

DQ26DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3RDQS2

RDQS1RDQS0

SEN

RESET

MFZQ

RAS*

CAS*WE*

CS*CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1RFU2

DM3DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1VSS2

VSS5

VSS3

VSS4

VSS7VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9VSSQ10

VSSQ11

VSSQ12VSSQ13

VSSQ14

VSSQ16VSSQ15

VSSQ17VSSQ18

VSSQ19VDDQ19

VDDQ20VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6VDDQ7

VDDQ8

VDD0

VDD1VDD2

VDD5

VDD3

VDD4

VDD6VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8DQ7

DQ9

DQ10DQ11

DQ12DQ13

DQ14

DQ15DQ16

DQ17

DQ18DQ19

DQ20

DQ21

DQ24DQ23

DQ22

DQ25

DQ26DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3RDQS2

RDQS1RDQS0

SEN

RESET

MFZQ

RAS*

CAS*WE*

CS*CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1RFU2

DM3DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1VSS2

VSS5

VSS3

VSS4

VSS7VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9VSSQ10

VSSQ11

VSSQ12VSSQ13

VSSQ14

VSSQ16VSSQ15

VSSQ17VSSQ18

VSSQ19VDDQ19

VDDQ20VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6VDDQ7

VDDQ8

VDD0

VDD1VDD2

VDD5

VDD3

VDD4

VDD6VDD7

VDDA0

(2 OF 2)

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IO

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Page NotesPower aliases required by this page:


Signal aliases required by this page:(NONE)

(NONE)

- =PP1V8_S0_FB_VDD- =PP1V8_S0_FB_VDDQ

U9000.J12U9000.J1

NCNC NC

NC

U9000.J1 U9000.J12Connect to designated pin, then GNDConnect to designated pin, then GND

2.37K

MF-LF402

1%1/16W

2

1R9030

5.49K

MF-LF402

1%1/16W

2

1R9031

402

0.1uF

X5R10%16V2

1 C90030.1uF

X5R402

10%16V2

1 C90020.1uF

X5R402

10%16V2

1 C90040.1uF

X5R10%16V402

2

1 C9001

0.1uF

X5R402

10%16V2

1 C90220.1uF

X5R402

10%16V2

1 C90230.1uF

X5R402

10%16V2

1 C90240.1uF

X5R402

10%16V2

1 C902516V402

0.1uF

X5R10%

2

1 C9026

OMITCRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11D11

D2

V4

J3

J2

V9

P3

P10D10

D3

H10

A9

B10B11

G3F2

F3

E2

T3T2

C3

R3R2

M3

N2L3

M2

T10T11

R10

R11

C2

M10

N11L10

M11

G10F11

F10

E11C10

C11

B3B2

N3

N10

E10E3

F4

H9

J10

J11

F9

H3

G4G9

M4

K2

L4K3

H2

K4M9

K10

L9

K11

H11K9 U9000

FBGA

OMITCRITICAL

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

G11

G2D12

D9

D4D1

B12

B9

T12T9

T4

T1P12

P9

P4P1

L11

L2

B4

B1

J12J1

V10

V3

L12L1

G12

G1A10

A3

H12

H1

E12E9

E4

E1C12

C9C4

V12

V1

C1

R12

R9

R4R1

N12N9

N4

N1J9

J4

A12A1

K12

K1

V11

V2M12

M1F12

F1

A11A2

U9000

0

MF-LF402

5%1/16W

2

1R9049

1/16W5%

402MF-LF

0

2

1R9041

243

MF-LF402

1%1/16W

2

1R9048

60.4

MF-LF402

1%1/16W

2

1R9045

1/16W1%

402MF-LF

60.4

2

1R9046

16V10%

402X5R

0.1uF2

1 C9033

2.37K1/16W

1%

402MF-LF

2

1R9032

5.49K

MF-LF402

1%1/16W

2

1R9033

402

0.1uF

X5R10%16V2

1 C9021

0402

FERR-220-OHM21

L9010

0402

FERR-220-OHM21

L90150.1uF

X5R402

10%16V2

1 C90150.1uF

X5R402

10%16V2

1 C9010

1/16W402

MF-LF

1211%

2

1R9040

1/16W402MF-LF

1211%

2

1R9047

1%121

MF-LF402

1/16W

2

1R9044

1/16W402MF-LF

1211%

2

1R9043

1%121

MF-LF402

1/16W

2

1R9042

MF-LF402

5%1/16W

0

2

1R9091

1%121

MF-LF402

1/16W

2

1R90901/16W

402

1%121

MF-LF2

1R9092

0.1uF16V10%

402X5R2

1 C90710.1uF16V10%

402X5R2

1 C9072

1%243

MF-LF402

1/16W

2

1R90985%0

MF-LF4021/16W

2

1R9099

FBGA

CRITICALOMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

A4

H4

P2

P11D11

D2

V4

J3

J2

V9

P3

P10D10

D3

H10

A9

B10B11

G3F2

F3

E2

T3T2

C3

R3R2

M3

N2L3

M2

T10T11

R10

R11

C2

M10

N11L10

M11

G10F11

F10

E11C10

C11

B3B2

N3

N10

E10E3

F4

H9

J10

J11

F9

H3

G4G9

M4

K2

L4K3

H2

K4M9

K10

L9

K11

H11K9 U9050

1211/16W402MF-LF1%

2

1R909360.41/16W1%

402MF-LF

2

1R9095402

1%1/16WMF-LF

121

2

1R9094

121

MF-LF1/16W1%

4022

1R9097

60.4

MF-LF402

1%1/16W

2

1R9096

1/16W1%

5.49K

MF-LF4022

1R9081

1/16W1%

2.37K

MF-LF4022

1R9080

1%1/16W

402

5.49K

MF-LF2

1R9083

2.37K1%

1/16W402

MF-LF2

1R9082

0.1uF16VX5R402

10%2

1 C9073

16V10%

402X5R

0.1uF2

1 C9081

0.1uF

X5R402

10%16V2

1 C90740.1uF16V10%

402X5R2

1 C9075

0.1uF

X5R16V10%

4022

1 C9083

16MX32-GDDR3-500MHZ

FBGA

CRITICALOMIT

K4J52324QC-BC20

G11

G2D12

D9

D4D1

B12

B9

T12T9

T4

T1P12

P9

P4P1

L11

L2

B4

B1

J12J1

V10

V3

L12L1

G12

G1A10

A3

H12

H1

E12E9

E4

E1C12

C9C4

V12

V1

C1

R12

R9

R4R1

N12N9

N4

N1J9

J4

A12A1

K12

K1

V11

V2M12

M1F12

F1

A11A2

U9050

0.1uF16V10%

402X5R2

1 C9076

FERR-220-OHM

0402

21

L9065

FERR-220-OHM

0402

21

L9060

16V10%

402X5R

0.1uF2

1 C905116V10%

402X5R

0.1uF2

1 C9052

0.1uF

X5R402

10%16V2

1 C9060

0.1uF

X5R402

10%16V2

1 C9053

0.1uF

X5R402

10%16V2

1 C9065

16V10%

402X5R

0.1uF2

1 C905420%

6.3VX5R805

22uF2

1C9000

20%6.3VX5R805

22uF2

1C9020

20%6.3VX5R805

22uF2

1C9050

22uF20%

6.3VX5R805

2

1C9070

X5R

0.1uF

402

10%16V2

1 C9031

051-6941


GDDR3 Frame Buffer BSYNC_DATE=(MASTER)

A

10490

FB_B_MA<4>

FB_B_CS_L<1>

FB_B_MA<9>


FB_B_DQ<24>

FB_B_DQ<13>FB_B_DQ<14>FB_B_DQ<12>FB_B_DQ<15>

FB_B_DQM_L<3>

FB_B_WDQS<1>


FB_DRAM_RST

FB_B0_ZQ

FB_B0_SEN

FB_B_DQ<23>

FB_B_CLK_N<1>

FB_B_CAS_L<1>FB_B_WE_L<1>

FB_B_RAS_L<1>FB_B1_ZQ

FB_B_DQ<61>

FB_B_DQ<46>

FB_B_CLK_P<1>

FB_B_MA<0>FB_B_MA<1>FB_B_MA<2>FB_B_MA<3>

FB_B_CKE<1>


=PP1V8_S0_FB_VDDQ

FB_B_MA<5>

FB_B_MA<7>

FB_B_BA<0>FB_B_BA<1>

FB_B_CKE<0>


FB_B_DQ<8>


FB_B_DQ<17>FB_B_DQ<19>FB_B_DQ<16>FB_B_DQ<20>FB_B_DQ<22>

FB_B_DQ<21>FB_B_DQ<29>FB_B_DQ<30>FB_B_DQ<28>FB_B_DQ<31>FB_B_DQ<27>


FB_B_DQ<6>FB_B_DQ<0>FB_B_DQ<5>FB_B_DQ<3>

FB_B_DQ<4>

FB_B_RDQS<1>

FB_B0_MF

FB_B_CAS_L<0>FB_B_WE_L<0>FB_B_CS_L<0>FB_B_CLK_N<0>

FB_B_MA<9>



FB_B_WDQS<3>FB_B_WDQS<2>

FB_B_WDQS<0>

FB_B_DQM_L<0>

FB_B_DQM_L<2>FB_B_DQM_L<1>

FB_B_MA<5>

FB_B_MA<11>

FB_B_MA<8>

FB_B_MA<10>




FB_B_DQ<50>



FB_B_DQ<43>FB_B_DQ<41>FB_B_DQ<42>FB_B_DQ<40>FB_B_DQ<37>FB_B_DQ<32>FB_B_DQ<39>FB_B_DQ<34>FB_B_DQ<36>FB_B_DQ<35>



FB_B_DQ<57>

FB_B_RDQS<7>FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B1_SENFB_DRAM_RST

FB_B1_MF

FB_B_MA<6>

FB_B_WDQS<4>FB_B_WDQS<5>FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_BA<0>FB_B_BA<1>

FB_B_DQM_L<7>FB_B_DQM_L<4>FB_B_DQM_L<5>FB_B_DQM_L<6>

FB_B_MA<11>

FB_B_MA<8>

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B1_VREF1




FB_B_RAS_L<0>

FB_B_BA<2> FB_B_BA<2>

FB_B_RDQS<5>

FB_B_MA<10>

FB_B_DQ<38>

=PP1V8_S0_FB_VDDQ

FB_B_MA<4>FB_B_MA<3>FB_B_MA<2>

FB_B_CLK_P<0>

PP1V8_S0_FB_B1_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V


=PP1V8_S0_FB_VDD



=PP1V8_S0_FB_VDD

71

71

71

71

71 71

71

71

70

71

71

71

71

70

71

71

71

71

71

71

71

71

71

71

71

71

71

70

71

71

71

71

71

71 71

71

70

71

71

71

70 70

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

63

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68

68 68

68

68

68

63

68

68

68

68

63 63

www.vinafix.vn

GPIO_0GPIO_1

TESTEN

GPIO_2

GPIO_27

PLLTEST

XTALOUTXTALIN

MPVSSMPVDD

PVSSPVDD

GPIO_16GPIO_17

GPIO_15GPIO_14GPIO_13GPIO_12GPIO_11GPIO_10GPIO_9GPIO_8

GPIO_7_BLONGPIO_6GPIO_5GPIO_4GPIO_3

VREFG

GPIO_33

GPIO_31GPIO_32

GPIO_25GPIO_26

GPIO_24

GPIO_21GPIO_20GPIO_19

DMINUSDPLUS

ROMCS*

GPIO_34

GPIO_29GPIO_30

NC_DVOVMODE_0NC_DVOVMODE_1

DVPCLK

DVPCNTL_0DVPCNTL_1DVPCNTL_2

DVPDATA_2DVPDATA_1DVPDATA_0

DVPDATA_4DVPDATA_3

DVPDATA_5

DVPDATA_7DVPDATA_6

DVPDATA_9DVPDATA_8

DVPDATA_10DVPDATA_11



DVPDATA_16


DVPDATA_19



GENERICAGENERICBGENERICCGENERICD

DIGONVARY_BL

NC0

GPIO_18

VDDPLL

GPIO_28

GPIO_22GPIO_23

GENERAL PURPOSE I/O

(1.2V)

(2.5V)

ROM

TEST

PLL & XTAL

VIP HOST / EXTERNAL TMDS

PANELCONTROL

VDDR3(3.3V)

(2.5V)VDD25

VDDR5

(1.8V/3.3V)

(1.8V/3.3V)

VDDR4

DIODETHERMAL

(2.5V)

(6 OF 7)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

20mA

70mA total for VDD25


- =I2C_GPU_TMDS_SCL - I2C clock line for

Page Notes

(PP1V0R1V2_S0_GPU_MPVDD)

NCNC

NC

NC


(GND_GPU_PVSS)

(GND_GPU_MPVSS)

(PP2V5_S0_GPU_PVDD_F)

- =I2C_GPU_TMDS_SDA - I2C data line for

- =PP3V3_GPU_GPIOS

- =PP1V8_GPU_LVDS_PLL

external TMDS transmitters

(NONE)

- =PP2V5_PVDD

external TMDS transmitters

20mA

Typically <50mA

Typically <50mA

Typically <50mA


100mA

10%16VX5R

0.1uF

4022

1 C91126.3VCERM

1uF

402

10%2

1 C9111

402

1uF6.3VCERM

10%2

1 C91166.3VCERM

1uF10%

4022

1 C9117

10%

X5R402

0.1uF16V2

1 C91376.3VCERM402

10%1uF

2

1 C9136

FERR-220-OHM

0402

21

L9135

6.3VCERM

1uF

402

10%2

1 C9141

FERR-220-OHM

0402

21

L9140

X5R16V

0.1uF10%

4022

1 C9142

5%1/16WMF-LF402

1K

2

1R9195

SM21

XW9140

1%4991/16WMF-LF4022

1R9191

1%499

402MF-LF1/16W

2

1R9190

SM21

XW9135

22uF

805X5R

6.3V20%

2

1C9100

20%6.3VX5R805

22uF2

1C9110

22uF

805X5R

6.3V20%

2

1C9115

20%6.3VX5R805

22uF2

1C9120

22uF

805X5R

6.3V20%

2

1C9125

10%

402

1uF6.3VCERM2

1 C913222uF

805X5R

6.3V20%

2

1C9130

805X5R

6.3V20%

22uF2

1C9135

22uF

805X5R

6.3V20%

2

1C9140

10%16VX5R402

0.1uF2

1C9191

OMIT

BGAM56P

AM26AL26

AC8

AE5AE4AE3AE2

AM5AL5AK5AJ5

AD20AD19AD18AC20AC19AB10AB9AA9

AC15

AC18AC16AC13AA10L10K22 AD12

AG22

AC7

AH14AJ14

AG14

AL4AK4

AB6

A5A6

AC5AC6AB2AC3AC2AC1

AG8AH7AG9AH8AJ8

AD3

AH9AG10AF10AH6AF8AF7AE9

AE10AG7AF9

AD1

AF13AE13

AB7AA8AB8AD5AB5AB4AB3AC4

AD2AD4

AD23AE23AF23AK22

AL2AK3AK1AK2AJ1AJ2AH3

AG6AE7AF6AH5

AH2

AG5AJ4AH4AJ3AG4AF5AF4AE6

AM3AL3

AG3AG2

AF3AF1AF2

AG1

AG12AH12

AE11

U8400

0.1uF

402X5R16V10%

2

1 C912710%

402

1uF

CERM6.3V2

1 C9126

10%16VX5R

0.1uF

4022

1 C91226.3VCERM

1uF10%

4022

1 C9121

FERR-220-OHM

0402

21

L9120

FERR-220-OHM

0402

21

L9125

200-OHM-EMI

0402

21

L9130

10%

402CERM6.3V

1uF2

1 C9131

10%

402

1uF

CERM6.3V2

1 C91016.3V

1uF10%

402CERM2

1 C91026.3VCERM

1uF

402

10%2

1 C9103


ATI M56 GPIO/DVO/Misc

91 104

A051-6941

GND_GPU_MPVSS


GND_GPU_PVSS


=PP3V3_S0_GPU_VDDR3

=PP2V5_S0_GPU_VDD25

=PP2V5_S0_GPU_VDDC_CT

GPU_GPIO_30GPU_GPIO_31

GPU_GPIO_8

ATI_DVPDATA<0>

ATI_DVPDATA<19>

ATI_DVPDATA<2>

ATI_TDIODE_P

GPU_GPIO_0GPU_GPIO_1GPU_GPIO_2

GPU_GPIO_27

GPU_XTALOUTGPU_XTALIN


GPU_GPIO_15GPU_GPIO_14GPU_GPIO_13GPU_GPIO_12GPU_GPIO_11GPU_GPIO_10GPU_GPIO_9


GPU_GPIO_3




ATI_TDIODE_N

TP_ATI_ROMCS_L

GPU_GPIO_34

GPU_GPIO_29

ATI_DVPCLK

ATI_DVPCNTL<0>ATI_DVPCNTL<1>ATI_DVPCNTL<2>

ATI_DVPDATA<1>

ATI_DVPDATA<4>ATI_DVPDATA<3>

ATI_DVPDATA<5>






ATI_DVPDATA<16>




GPU_GENERICAGPU_GENERICBGPU_GENERICCGPU_GENERICD

GPU_DIGONGPU_VARY_BL

GPU_GPIO_18

GPU_GPIO_28


ATI_TESTEN

=PP3V3_S0_GPU

ATI_VREFG

GPU_GPIO_24 GPU_GPIO_4


PP1V8R3V3_S0_GPU_VDDR4_F=PP1V8R3V3_S0_GPU_VDDR4


PP1V8R3V3_S0_GPU_VDDR5_F=PP1V8R3V3_S0_GPU_VDDR5


PP1V2_S0_GPU_VDDPLL=PP1V2_S0_GPU_VDDPLL


PP2V5_S0_GPU_PVDD_F=PP2V5_S0_GPU_PVDD


PPVCORE_S0_GPU_MPVDD=PPVCORE_S0_GPU

69

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63

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50

69

69

69

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69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

50

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

66

74

74

69

69

69

69

63

69 69

63

63

63

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DDC3DATADDC3CLK

DDC2DATADDC2CLK

DDC1DATADDC1CLK

TXOUT_L3NTXOUT_L3PTXOUT_L2NTXOUT_L2PTXOUT_L1NTXOUT_L1PTXOUT_L0NTXOUT_L0P

TXCLK_LPTXCLK_LN

TXOUT_U3N

TXOUT_U2NTXOUT_U3P

TXOUT_U2PTXOUT_U1NTXOUT_U1PTXOUT_U0NTXOUT_U0P

TXCLK_UNTXCLK_UP

COMP

CY

V2SYNCH2SYNC

B2G2R2

VSYNCHSYNC

BGR

TX2MTX2PTX1M

TX0MTX1P

TX0P

TXCM

HPD1

LPVSSLPVDD

R2SET

VDD2DIVSS2DI

A2VSSQNC_A2VDDQ

VSS1DI

RSET

AVSSQ

VDD1DI

TXCPTPVSSTPVDD

TX3PTX3MTX4PTX4MTX5PTX5M

A2VSS

A2VDD(2.5V)

AVSS

(2.5V)AVDD

TXVSSR

IDENTIFICATION

(5 OF 7)

LVDDR

LVSSR

DAC (CRT)

DAC2 (TV/CRT2)

LVDS

MONITOR

TXVDDR

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

INTEGRATED TMDS

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

20mA peak

20mA peak

20mA peak

130mA peak

- =PP1V8R2V5_S0_GPU_LVDDR- =PP2V5_S0_GPU

(NONE)

(NONE)


NC

150mA peak

65mA peak

200mA peak

Comp B Pb

C R PrY G Y

Composite/S-Video VGA Component

20mA peak



Sum of peak currents on this page: 605mA

Page Notes

BGAM56P

OMIT

AJ15

AJ22

AJ17

AL23

AJ16

AM23

AG15

AM7AL7AK8AK7AJ7AM6AL6AK6AJ6

AH21AG21

AG20AH20

AK20AJ20

AG18AH18

AJ18AK18

AM21AL21

AM20AL20

AL19AK19

AM9AL9

AJ21AK21

AM18AL18

AJ12AK12

AJ11AK11

AJ9AK9

AM12AL12

AM11AL11

AL10AK10

AL8AM8

AL22

AK14

AK15

AK24

AL14

AK17AJ19AH19AH17AG19AG17AF22AF21AF18AF17AF20AF19AE22AE21AE20AD22AD21AC22AC21

AE18AE19

AJ23

AF11

AF15

AM15

AM24

AE12AF12

AH13AG13

AH22AH23

AH15

AJ13

AL15

AL24AK23

AK25AJ24

AM25AL25

AK13

AM17AL17

AM16AL16

U8400

1/16W1%

402MF-LF

499

2

1R9350

0.1uF

X5R402

10%16V2

1 C93460.1uF

X5R402

10%16V2

1 C93426.3V402CERM

1uF10%

2

1 C9341

0402

FERR-220-OHM21

L9300

1uF

CERM10%6.3V402

2

1 C9301

1uF

CERM402

10%6.3V2

1 C93060402

FERR-220-OHM21

L9305

10%

402X5R

0.1uF16V2

1 C9307

0402

FERR-220-OHM21

L9330

6.3V10%

402CERM

1uF2

1 C9331

SM21

XW9345

SM21

XW9330

X5R402

10%0.1uF16V2

1 C93221uF

402

10%CERM6.3V2

1 C93210402

FERR-220-OHM21

L9320

SM21

XW9320

10%

402X5R

0.1uF16V2

1 C93126.3V10%CERM

1uF

4022

1 C93110402

FERR-220-OHM21

L9310

SM21

XW9310

SM21

XW9305

SM21

XW9300

SM21

XW9314

SM21

XW9324

16V10%X5R

0.1uF

4022

1 C9317

402CERM6.3V10%1uF

2

1 C9316

16V10%

402X5R

0.1uF2

1 C93276.3V402CERM10%1uF

2

1 C9326

0402

FERR-220-OHM21

L9325

0402

FERR-220-OHM21

L9315

0402

FERR-220-OHM21

L9345

0.1uF

X5R402

10%16V2

1 C934720%

6.3VX5R805

22uF2

1C934020%

6.3VX5R805

22uF2

1C9345

6.3V10%

402CERM

1uF2

1 C9332

1uF

CERM10%

4026.3V2

1 C93026.3VX5R805

22uF20%

2

1C9300

22uF

805X5R

6.3V20%

2

1C9305

20%6.3VX5R805

22uF2

1C9310

22uF

805X5R

6.3V20%

2

1C9315

20%

X5R

22uF

805

6.3V 2

1C9320

X5R6.3V20%

22uF

8052

1C9325

20%6.3V

805

22uF

X5R 2

1C9330

715

MF-LF402

1%1/16W

2

1R9351

93 104

A051-6941


ATI M56 Video Interfaces

GND_GPU_TXVSSR


GPU_TV_C

VOLTAGE=0V

GND_GPU_LPVSSMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

GPU_TV_COMP

GPU_TV_Y

GPU_VGA_RGPU_VGA_GGPU_VGA_B

GPU_R2GPU_G2GPU_B2

GPU_V2SYNC

VOLTAGE=0V

GND_GPU_AVSSNMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

ATI_R2SET

ATI_RSET

GPU_HPD

LVDS_U_DATA_N<3>LVDS_U_DATA_P<3>


LVDS_L_CLK_P

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<1>LVDS_L_DATA_N<0>

GPU_VGA_VSYNCGPU_VGA_HSYNC

LVDS_U_CLK_PLVDS_U_CLK_N

LVDS_U_DATA_P<0>LVDS_U_DATA_N<0>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

TMDS_DATA_N<5>

TMDS_DATA_N<4>

TMDS_DATA_N<3>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>LVDS_L_DATA_P<2>

LVDS_L_DATA_P<3>LVDS_L_DATA_N<3>

GPU_DDC_A_CLK

GPU_DDC_B_DATAGPU_DDC_B_CLK

GPU_DDC_A_DATA

ATI_RSETATI_R2SET


LVDS_L_CLK_N

GPU_DDC_C_CLKGPU_DDC_C_DATA

VOLTAGE=0V

GND_GPU_AVSSQMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

VOLTAGE=0V

GND_GPU_A2VSSNMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm

GPU_H2SYNC

VOLTAGE=0V

GND_GPU_A2VSSQMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm

TMDS_CLK_P

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

VOLTAGE=0V

GND_GPU_TPVSSMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

PP2V5_S0_GPU_TPVDDMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmVOLTAGE=2.5V

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.3 mmPP2V5_S0_GPU_TXVDDR

VOLTAGE=2.5V

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP2V5_S0_GPU_AVDD

VOLTAGE=2.5V

PP2V5_S0_GPU_VDD1DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmVOLTAGE=2.5V


PP2V5_S0_GPU_A2VDD

PP2V5_S0_GPU_VDD2DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmVOLTAGE=2.5V

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP2V5_S0_GPU_LPVDD

VOLTAGE=2.5V

=PP2V5_S0_GPU

GND_GPU_LVSSR



PP2V5_S0_GPU_LVDDR

79

79

79

79

79

79

79

79

79

79

79

79

79

79

75

75

75

77

77

77

77

77

77

77

77

77

77

75

75

75

75

75

75

75

77

77

77

77

77

77

75

75

75

75

75

75

75

69

69

69

69

69

69

74

74

74

75

73

73

75

69

69

74

74

74

74

74

74

69

69

74

74

74

74

74

74

74

74

74

74

74

74

74

74

69

69

75

69

69

75

73

73

74

74

74

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74

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G

D

S

N-CHN

S

D

G

P-CHN

G

DS

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SPACINGELECTRICAL_CONSTRAINT_SET PHYSICAL

INVERTER INTERFACE

NC

NC

NET_TYPE

100K pull-ups are for

Panel has 2K pull-upsNC

518S0293

518S0289

INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL

no-panel case (development)

LCD (LVDS) INTERFACE

100K

MF-LF402

5%1/16W

2

1R9450

0.001uF

CERM402

20%50V 2

1C9454

50V20%

402CERM

0.001uF2

1 C9452

CERM

0.001uF50V20%

4022

1 C9450

10UF

X5R603

20%6.3V 2

1C9451

SM

FERR-1K-OHM-EMI21

L9450

SM-1

400-OHM-EMI21

L9454

10V20%

402CERM

0.1uF

INVERTER_BUF

2

1C9453

SM-1

400-OHM-EMI21

L9452

0.001uF

CERM20%50V402

2

1C9420

1/16W5%

402MF-LF

100K

2

1R9410

402

0.001uF

CERM20%50V 2

1C9410

1/16W5%

402MF-LF

100K

2

1R9411

0.001uF

20%CERM40250V

2 1

C9421

MSC-RB30-5-FAF-RT-SM

CRITICAL

987654

30

3

29282726252423222120

2

19181716151413121110

1

34

33

J9400

SM60-OHM-EMI

2

1

L94550.001uF

402

20%50VCERM2

1 C9455

0.001uF

CERM20%50V402

2

1C9401SM

FERR-250-OHML940050V

CERM

0.0022uF

10%

402

21

C9400

100K

MF-LF402

1/16W5%

R9401MF-LF

402

5%1/16W

100K

2

1R9400

SI3443DVTSOP-LF

4

3 6521

Q9400

2N7002SOT23-LF

2

1

3

Q9401

5%1/16WMF-LF

402

10K

2

1R9489

100K

402MF-LF1/16W

5%

2

1R9494

INVERTER_UNBUF

5%1/16W

402

0

MF-LF

21

R9496

MC74VHC1G08SC70

INVERTER_BUF5

4

1

2

3

U9453

SM-2MT-LF

CRITICAL

4321

6

5

J9450

SC70-6FDG6332C_NL

1

2

6

Q9450

SC70-6FDG6332C_NL

4

5

3

Q9450


94 104

A051-6941

Internal Display Connectors

INVERTER_PWM

=GND_CHASSIS_LCD2

=PP5V_S0_INVERTER

PP5V_INVERTER_SW_FMIN_LINE_WIDTH=0.5 mmVOLTAGE=5VMIN_NECK_WIDTH=0.25 mm

GPU_BLON

FP_PWR_EN_L


PPBUS_S0_INVERTER

=GND_CHASSIS_LCD3

=GND_CHASSIS_LCD4

PP3V3_LCD_CONNMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V

=GND_CHASSIS_LCD1

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP3V3_LCD_SWLCD_PWREN_L_RC

GPU_DIGON

LCD_PWREN_L

=PP3V3_S0_LCD

=PPBUS_S0_INVERTER

=GND_CHASSIS_INVERTER

INVERTER_PWM_F

=PP3V3_S0_INVERTER

GPU_VARY_BL

GPU_DDC_C_CLK

=PP3V3_S0_DDC_LCD

LVDS_L_DATA_CONN_P<0>LVDS_L_DATA_CONN_N<0>

LVDS_U_DATA_CONN_N<0>

LVDS_L_CLK_CONN_NLVDS_L_CLK_CONN_P



LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<1>LVDS_U_DATA_CONN_P<1>

LVDS_U_DATA_CONN_N<2>LVDS_U_DATA_CONN_P<2>

LVDS_U_CLK_CONN_NLVDS_U_CLK_CONN_P

LVDSLVDS LVDS_U_CLK_CONN_PLVDS_U_CLK_CONN_NLVDS LVDSLVDS_U_DATA_CONN_P<2..0>LVDSLVDSLVDS_U_DATA_CONN_N<2..0>LVDSLVDS

LVDS_L_CLK_CONN_PLVDS LVDSLVDS_L_CLK_CONN_NLVDSLVDSLVDS_L_DATA_CONN_P<2..0>LVDSLVDSLVDS_L_DATA_CONN_N<2..0>LVDS LVDS

TMDS_CLK_PTMDS TMDSTMDS_CLK_NTMDS TMDS

TMDS_DATA_P<2..0>TMDS TMDSTMDS_DATA_N<2..0>TMDS TMDS

TMDS_DATA_N<5..3>TMDS TMDS

TMDS_DATA_P<5..3>TMDS TMDS

LVDS_L_CLK_PLVDSLVDSLVDS_L_CLK_NLVDS LVDSLVDS_L_DATA_P<2..0>LVDS LVDSLVDS_L_DATA_N<2..0>LVDSLVDS

LVDS_U_CLK_PLVDSLVDSLVDS_U_CLK_NLVDSLVDSLVDS_U_DATA_P<2..0>LVDS LVDSLVDS_U_DATA_N<2..0>LVDS LVDS

GPU_R2VGA VGAGPU_G2VGA VGAGPU_B2VGA VGA

GPU_DDC_C_DATA

PP5V_INVERTER_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

GND_INVERTERMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

79

79

79

79

79

79

77

77

77

77

77

77

77

77

77

77

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75

75

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69

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6

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72

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72

73

63

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G

SD

G

SD

G

SD

LCFILTER

LCFILTER

LCFILTERSYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

514-0278

PLACE NEAR 3, 11 & 19

PLACE NEAR C5A & C5B

(PP5V_S0_DDC)

Isolation required for DVI power switch

ELECTRICAL_CONSTRAINT_SET SPACINGNET_TYPE

PHYSICAL

(55mA requirement per DVI spec)

3V LEVEL SHIFTERS

DVI DDC CURRENT LIMITDVI INTERFACE

VGA SYNC BUFFERS

PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR

ANALOG FILTERINGPLACE CLOSE TO CONNECTOR

(DAC2 C)

(DAC2 Y)

(DAC2 Comp)

Place series R’s and common-mode filtering close to GPU, common mode chokes near connector.

TMDS Filtering

1/16W5%MF-LF

10K

4022

1R9721

1/16W5%

402MF-LF

10K

2

1R9720

SOT-3632N7002DW-X-F

1

2

6

Q9711

SOT-3632N7002DW-X-F

4

5

3

Q9711

1/16W5%

402MF-LF

100K

2

1R9722

50V5%

402CERM

100pF2

1 C9713

4.7K

MF-LF402

5%1/16W

2

1R97121/16W

5%

402MF-LF

4.7K

2

1R9710

100pF

CERM402

5%50V2

1 C9711

0.01uF

CERM603

20%50V 2

1C9710

400-OHM-EMI

SM-1

21

L9710

SOT-3632N7002DW-X-F

4

5

3

Q9714

CRITICAL

0.5AMP-13.2V

SM-LF

21

F9710

B0530WXF

SOD-12321

D9710

402

100pF

CERM5%50V2

1 C9714

MF-LF402

5%1/16W

100 21

R9711

MF-LF402

5%1/16W

100 21

R9713

MF-LF402

5%1/16W

100 21

R9714

0

MF-LF402

5%1/16W

2 1

R9730

0

MF-LF5%

1/16W402

2 1

R9731

3.3pF

CERM402

0.25%50V2

1 C9741

1/16W1%

402MF-LF

75

2

1R9742

1/16W1%

402MF-LF

75

2

1R9740

1/16W1%

402MF-LF

75

2

1R9741

3.3pF

CERM402

0.25%50V2

1 C9742

3.3pF

CERM402

0.25%50V2

1 C9740

CRITICAL

SM-220MHZ-LF

43

21

FL9740

SM-220MHZ-LF

CRITICAL

43

21

FL9741

CRITICAL

SM-220MHZ-LF

43

21

FL9742

CRITICAL

90-OHM-300mA2012H

4

32

1

L9702

CRITICAL

90-OHM-300mA2012H

4

32

1

L9701

33

5%1/16WMF-LF402

21

R9750

1/16W5%

402MF-LF

3321

R9751

90-OHM-300mA2012H

CRITICAL

4

32

1

L9703

90-OHM-300mA2012H

CRITICAL

4

32

1

L9704

CRITICAL

90-OHM-300mA2012H

4

32

1

L9705

90-OHM-300mA2012H

CRITICAL

4

32

1

L9700

QH11121-RIG02-4FF-RT-TH-DVI

CRITICAL

9

8

7

6

5

4

3

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

34

33

32

31

C5B C5A

C4

C3

C2

C1

J9700

5%1/16WMF-LF

402

20K

2

1R9715

1%1/16W

402MF-LF

182

2

1R9786

5%1/16WMF-LF

0

402

21

R9785

5%1/16WMF-LF

0

402

21

R9784

402MF-LF1/16W

1%182

2

1R9782

0

402MF-LF1/16W5%

21

R9780

5%1/16WMF-LF402

021

R9781

0

402MF-LF1/16W5%

21

R9777

5%1/16WMF-LF402

021

R9776

1%1/16WMF-LF

402

182

2

1R9778

402MF-LF1/16W

1%90.9

2

1R97751%1/16WMF-LF402

90.9

2

1R9774402

0

MF-LF1/16W5%

21

R9773

5%

402

0

MF-LF1/16W

21

R9772

10%50VCERM402

0.001uF21

C9774

1%1/16WMF-LF

402

182

2

1R9770

5%

MF-LF402

0

1/16W

21

R9769

5%

402

0

MF-LF1/16W

21

R9768

MF-LF1/16W

1%

402

182

2

1R9766

5%1/16WMF-LF

0

402

21

R9765

402

0

MF-LF1/16W5%

21

R9764

5%1/16WMF-LF402

021

R9761

0

402MF-LF1/16W5%

21

R9760

CRITICAL

SM370-OHM

4

32

1

L9706

402

0.1uF10V20%

CERM 2

1C9751

0.1uF

402CERM10V20%

2

1C9750

SC70MC74VHC1G085

4

1

2

3

U9750

SC70MC74VHC1G085

4

1

2

3

U9751

402

1/16WMF-LF

1821%

2

1R9762


External Display Connector

051-6941 A

10497

TMDS_DATA_R_N<0>

TMDS_CLK_P

TMDS_CLK_N

TMDS_DATA_R_P<5>

TMDS_DATA_R_N<5>

TMDS_DATA_R_P<4>

TMDS_DATA_R_N<4>

TMDS_DATA_R_P<3>

TMDS_DATA_R_N<3>

TMDS_DATA_P<5>

TMDS_DATA_N<5>

TMDS_DATA_P<4>

TMDS_DATA_N<4>

TMDS_DATA_P<3>

TMDS_DATA_N<3>

TMDS_DATA_R_P<2>

TMDS_DATA_R_N<2>

TMDS_DATA_R_P<1>

TMDS_DATA_R_N<1>

TMDS_DATA_R_P<0>

TMDS_DATA_P<2>

TMDS_DATA_N<2>

TMDS_DATA_P<1>

TMDS_DATA_N<1>

TMDS_DATA_P<0>

TMDS_DATA_N<0>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

GPU_HPD

GPU_DDC_A_DATA

GPU_DDC_A_CLK

GPU_R2

GPU_G2

GPU_B2

VGA_R

VGA_G

VGA_B

TMDS_CLK_F_NTMDSCONNTMDSCONN

TMDS_CLK_F_PTMDSCONNTMDSCONN

TMDS_DATA_F_P<5..0>TMDSCONN TMDSCONNTMDS_DATA_F_N<5..0>TMDSCONNTMDSCONN

TMDS TMDS TMDS_CLK_R_N

TMDSTMDS TMDS_DATA_R_P<5..0>

VGA_VSYNCVGA_VSYNC_R

VGA_HSYNCVGA_HSYNC_R

GPU_V2SYNC

GPU_H2SYNC

=PP3V3_S0_VGASYNC

=PP3V3_S0_VGASYNC

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<3>

TMDS_CLK_R_P

TMDS_CLK_R_N

TMDS_CLK_CMF

TMDS_CLK_F_N

TMDS_CLK_F_P

TMDS_DATA_F_N<2>

TMDS_DATA_F_P<2>

TMDS_DATA_F_N<1>

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<0>

=PP3V3_S0_DDC_DVI

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

VGA_HSYNC

VGA_B

TMDS_CLK_F_N

TMDS_CLK_F_P

DVI_DDC_DATA

DVI_DDC_CLK

DVI_HPD

PP5V_S0_DDC_FVOLTAGE=5VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

=GND_CHASSIS_DVI2

PP5V_S0_DDC_PULLUPSVOLTAGE=5VMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

=PP5V_S0_DVI_DDC

TMDS_CLK_R_PTMDS TMDS

TMDS TMDS TMDS_DATA_R_N<5..0>

DVI_HPD_R

=GND_CHASSIS_DVI4

VGA_R

VGA_G

TMDS_DATA_F_P<2>

TMDS_DATA_F_N<4>TMDS_DATA_F_N<3>TMDS_DATA_F_P<4>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<3>

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=5VPP5V_S0_DDC

VGA_VSYNC

DVI_DDC_DATA_R

DVI_DDC_CLK_R

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<1>TMDS_DATA_F_N<2>

TMDS_DATA_F_P<0>


=GND_CHASSIS_DVI1

79

79

79

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79

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79

79

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74

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79

79

79

79

79

79

79

79

79

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79

79

79

75

73

73

75

75

75

75

75

75

73

73

73

73

73

73

75

75

75

75

75

73

73

73

73

73

73

75

75

73

73

73

73

73

73

75

75

75

75

75

75

75

75

75

75

75

73

73

63

63

75

75

75

75

75

75

75

75

75

75

75

75

75

75

63

75

75

75

75

75

75

6

63

75

75

6

75

75

75

75

75

75

75

75

75

75

75

75

75

6

www.vinafix.vn

IO

IO

IN

OUT

SYM_VER-1

IN

INOUT

OUT

SYM_VER-1

IO

IO

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Left ALS Connector

516S0412

NC

NC

NOTE: _UF_ nets cross DDR2 signals and pickup significant noise. Common-mode chokesare to remove this noise from SATA signals.

518S0395

Bluetooth (M13P), IR & SATA HDD Flex Connector

FH19-4S-0.5SH-48

CRITICAL

F-RT-SM

4

3

2

1

6

5

J6430

CRITICALPLACEMENT_NOTE=Place FL4960 close to J4960

90-OHM-300mA2012H

4

32

1

FL4960

0.0047uF

10%

CERM25V

402

PLACEMENT_NOTE=Place C4960 close to southbridge

21

C496025VCERM

0.0047uF

402

10%

PLACEMENT_NOTE=Place C4961 next to C4960

21

C4961PLACEMENT_NOTE=Place FL4965 close to southbridgeCRITICAL

2012H90-OHM-300mA

4

32

1

FL4965

PLACEMENT_NOTE=Place C4965 close to J4960

402

25VCERM

0.0047uF

10%

12

C4965

PLACEMENT_NOTE=Place C4966 next to C4965

25VCERM

10%

402

0.0047uF12

C4966

CRITICAL

M-ST-SMQT500206-L020

9

87

65

43

20

2

19

1817

1615

1413

1211

10

1

J4960

M1 Specific Connectors

051-6941 A

10498


SATA_C_D2R_UF_N

=PP5V_S3_IR=PP3V3_S3_BT

=PP5V_S0_HDD

SATA_C_D2R_N

SATA_C_D2R_P SATA_C_D2R_UF_PSATA_C_D2R_C_PSATA_C_D2R_C_N

LTALS_OUTALS_GAIN

SYS_LED_ANODE

=USB_IR_P=USB_IR_N

=USB_BT_P=USB_BT_N

SATA_C_R2D_PSATA_C_R2D_N

SATA_C_R2D_UF_P SATA_C_R2D_C_P

SATA_C_R2D_UF_N SATA_C_R2D_C_N

=PP3V3_S3_LTALS

47 6

63

63

63

63

21

21

5

48

6

6

6

6

21

21

5

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

and long-term reliability issues. Pull-down resistors reduce

when they should be tri-stated to meet panel power sequence

LVDS Interface Pull-downsNOTE: These parts are to counter an invalid state caused by theM56 part. Bias voltage is present on LVDS interface pins even

requirements. Resulting pump-up in LCD panel can cause startup

the pump-up in the panel, though some voltage will still be seenon LVDS signals when they should be 0V.

SM-LF

LVDS_PD

5%1/16W

8.2K81

RP9900

SM-LF

LVDS_PD

1/16W5%

8.2K81

RP9902

SM-LF

LVDS_PD

1/16W5%

8.2K63

RP9902SM-LF

LVDS_PD

5%1/16W

8.2K54

RP9902

SM-LF

LVDS_PD

1/16W5%

8.2K72

RP9903

SM-LF

LVDS_PD

5%1/16W

8.2K81

RP9903

SM-LF

LVDS_PD

1/16W5%

8.2K63

RP9903SM-LF

LVDS_PD

5%1/16W

8.2K54

RP9903

SM-LF

LVDS_PD

1/16W5%

8.2K72

RP9900

SM-LF

LVDS_PD

5%1/16W

8.2K54

RP9900

SM-LF

LVDS_PD

1/16W5%

8.2K63

RP9900

SM-LF

LVDS_PD

1/16W5%

8.2K72

RP9901

SM-LF

LVDS_PD

5%1/16W

8.2K81

RP9901

SM-LF

LVDS_PD

1/16W5%

8.2K63

RP9901SM-LF

LVDS_PD

5%1/16W

8.2K54

RP9901

SM-LF

LVDS_PD

5%1/16W

8.2K72

RP9902

051-6941 A

10499


LVDS Interface Pull-downs

LVDS_U_CLK_NMAKE_BASE=TRUE

LVDS_U_CLK_CONN_N

LVDS_U_CLK_PMAKE_BASE=TRUE

LVDS_U_CLK_CONN_P

MAKE_BASE=TRUELVDS_U_DATA_N<2> LVDS_U_DATA_CONN_N<2>

MAKE_BASE=TRUELVDS_U_DATA_P<2> LVDS_U_DATA_CONN_P<2>

LVDS_U_DATA_N<1>MAKE_BASE=TRUE

LVDS_U_DATA_CONN_N<1>

LVDS_U_DATA_P<1>MAKE_BASE=TRUE

LVDS_U_DATA_CONN_P<1>

MAKE_BASE=TRUELVDS_U_DATA_N<0> LVDS_U_DATA_CONN_N<0>

MAKE_BASE=TRUELVDS_U_DATA_P<0> LVDS_U_DATA_CONN_P<0>

LVDS_L_CLK_NMAKE_BASE=TRUE

LVDS_L_CLK_CONN_N

LVDS_L_CLK_PMAKE_BASE=TRUE

LVDS_L_CLK_CONN_P

MAKE_BASE=TRUELVDS_L_DATA_N<2> LVDS_L_DATA_CONN_N<2>

MAKE_BASE=TRUELVDS_L_DATA_P<2> LVDS_L_DATA_CONN_P<2>

LVDS_L_DATA_N<1>MAKE_BASE=TRUE

LVDS_L_DATA_CONN_N<1>

LVDS_L_DATA_P<1>MAKE_BASE=TRUE

LVDS_L_DATA_CONN_P<1>

MAKE_BASE=TRUELVDS_L_DATA_N<0> LVDS_L_DATA_CONN_N<0>

MAKE_BASE=TRUELVDS_L_DATA_P<0> LVDS_L_DATA_CONN_P<0>

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

73 74

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

DMS Release #A000 (Production Release)(13.2.0)

(11.10.0) DMS Release #12000-13000 (DVT releases)

2006/01/06 - 4362451 - Changed BOM options for production SMC, BootROM.2006/01/06 - 4362451 - Added System Block Diagram, updated Power Diagram.2006/01/06 - 4402184 - Changed R7540 value for IMVP6 load-line improvement.

2006/01/05 - 4362451 - Removed power jumpers and 0-ohm resistor.2006/01/05 - 4362451 - Restructured BOM tables to eliminate LeMenu.

2005/12/07 - 4375840 - Synced 4 pages from mlb_dvt branch back to trunk.

2005/12/12 - 4362451 - Added MAKE_BASE=TRUE to SMC 32KHz SUSCLK net.

2005/10/08 - 4293072 - Various BOM / connection changes at IMVP6 (CPU VCore).2005/10/08 - 4214493 - Simplified FireWire port power circuit for BOM consolidation.

2005/10/07 - 4292633 - Changed IMVP6 10K NTC from 10% to 5% part.2005/10/07 - 4286888 - BOM restructuring per EVT build plan.

2005/10/04 - 4261313 - Deleted placeholder connector, grew HDD connector for IR.

2005/09/30 - 4274915 - C1001 stuffing change from Proto 2 MLB branch.

(11.8.0)

2006/01/03 - 4375840 - Synced 1 page from mlb_dvt branch back to trunk.

DMS Release #08000-11000 (EVT releases)

2005/08/29 - 4227336 - Changed Y5920 to 197S0169.2005/08/29 - 4227309 - Resolved sync issues with M38 (SB page 21).

2005/08/29 - 4227322 - Sync page 44 with M42 to fix FW power net S-states.

2005/12/02 - 4217524 - Updated part number for J6430.

2005/12/02 - 4256256 - Added BOMOPTION to R8801 to allow per-project control.

2005/10/12 - 4244539 - Retasked FET to control 3.3V S0 FET from GPU VCore PGOOD.

2005/10/13 - 4247941 - Spacing/Physical rule updates to match latest board database.

2005/10/21 - 4310267 - Synced 3 pages from mlb_evt branch back to trunk.

2005/11/15 - 4322537 - Updated thru-hole SO-DIMM connector part number.

2005/11/16 - 4235898 - Changed Yukon power rail neck widths per M9 request.

2005/11/16 - 4345921 - FUNC_TEST updates per test team request.2005/11/16 - 4227333 - Updated SMC net names per ERS v1.2.1.

2005/11/16 - 4235898 - Aliased connection to ALS_GAIN to support M9 request.

2005/09/08 - 4229560 - First implementation of Physical Security Guidelines.

2005/09/20 - 4214847 - Updated L1970 (old part no longer exists in library).

(11.9.0)

2005/10/09 - 4235898 - Part moves & refdes changes to support sync with M9.

2005/10/10 - 4247941 - Net property updates found via back-annotation.

2005/10/10 - 4229560 - Removed Physical Security circuitry.

2005/10/10 - 4248911 - Sync with M38 & M42.

2005/08/31 - 4227328 - Added ESD protection diode on right USB port.

2005/08/31 - 4237025 - Added R8824 and R8827 for GPU memory configuration straps.2005/08/31 - 4227315 - Changed BSA bus pull-ups from 2K to 10K.

DMS Checkin #11002

2005/11/22 - 4352020 - Changed 2.5V S3 supply inductor & compensation values.2005/11/28 - 4347845 - Added pull-down resistors on LVDS interface.2005/11/30 - 4227340 - Removed CPU VCore current sense input RC.

2005/10/10 - 4232826 - Swapped Vtt RPAK functions to optimize layout.

DMS Checkin #07007

2005/08/31 - 4227328 - Changed EMI caps from 50V to 16V to fid in ESD protection.

2005/09/03 - 4232534 - Added notes for power supplies and connectors.

DMS Checkin #040072005/09/06 - 4240486 - Removed NO_TEST property from GPU HSYNC and VSYNC.

2005/09/06 - 4232534 - Fixed label BOM tables to call out proper EEE #’s.

2005/09/08 - 4248911 - Sync with M38 & M42.

DMS Release #03000 (RFA #394758)

2005/08/12 - 4231030 - Changed pinout of J4960, added placement notes.

2005/08/27 - 4227325 - Removed S0 option for camera, now S3-only.

2005/10/10 - 4214493 - Cost reductions to GPU power supply circuitry.

2005/10/11 - 4261313 - Updated SATA connector pinout to match latest flex.

2005/10/12 - 4214494 - Implemented circuit to power down ethernet in S3 on battery.

2005/10/17 - 4304248 - Updated GPU VCore / BBP voltages for B13/B24 support.

2005/11/16 - 4346006 - Updated J5500 pinout to match updated LIO board pinout.

2005/11/19 - 4229560 - Changed FW chip back to REQ/GNT3.

(11.7.0)

2005/11/21 - 4351196 - Added 1K pull-down on IDE_RESET_L.(11.5.0) 2005/11/21 - 4343202 - Changed RC value and net name for USB OC.

2005/08/31 - 4240157 - Corrected pinout at SATA/BT conn (J4960) to match flex.2005/08/31 - 4240150 - Swapped PCIE Mini Card R2D/D2R connections at J5500.

(11.4.0)

2005/10/14 - 4247941 - Restored NO_TEST properties, added EXPOSED_VIA properties.


2005/11/16 - 4343202 - Changed USB overcurrent switch to TPS2051B, added OC* RC.

2005/11/16 - 4235898 - Sync with M38 & M42.

2005/11/18 - 4235898 - Changed R4210 package size per M9 request.

2005/11/19 - 4346184 - Fixed location of SATA R2D common-mode choke.

2005/11/19 - 4350840 - Simplified TMDS filtering to allow movement of filter.

2005/11/19 - 4292165 - Refreshed schematic symbol for U3750 (library update).

2005/08/29 - 4217524 - Changed R6430 from 4.5K to 3.5K.2005/08/29 - 4232826 - Changed MEM_ODT* from RPAKs to discrete Rs.2005/08/29 - 4235179 - Changed J8200 to proper 6-pin part.

2005/10/09 - 4272237 - Changed 2.5V S0 FET RC to 100K to slow down turn-on.

2005/08/29 - 4227335 - Changed U5900 to resolve ROHS issue.

2005/08/28 - 4232715 - Added FireWire ISense resistor, changed INA193 to INA194.

2005/08/27 - 4235208 - Changed value of R7707 to fix 2.5V S3 supply.

2005/08/30 - 4217535 - Removed BOM tables and OMITs for new 4-pin WTB connector.

2005/09/19 - 4235898 - Moved signal alias to improve schematic reuse.

DMS Checkin #04005

DMS Checkin #04006

DMS Checkin #04003

DMS Checkin #04001

DMS Checkin #04004

DMS Checkin #04002

2005/08/29 - 4237119 - Changed LIO 5V S3 to 5V S5.

2005/08/29 - 4227312 - Resolved sync issues with M38 (SB page 23).

2005/09/16 - 4229560 - Changed FW PCI REQ/GNT pair for Physical Security.2005/09/16 - 4256660 - Updated FUNC_TEST property for merged PBUS.

2005/09/21 - 4234952 - Replaced FDG6324L parts with FDG6332C for cost & supply.

2005/09/26 - 4274915 - Thermal sensor BOM updates from Proto 2 MLB branch.

Date - Radar # - Description

2005/09/26 - 4274915 - U6301 part number updated to M1 development BootROM.

2005/09/19 - 4247941 - GND line/neck/voltage properties updated per PCB request.

2005/09/21 - 4227306 - Changed CPU VCore caps to proper production part number.

2005/09/06 - 4246683 - Removed NO STUFF option from R8805 per ATI request.

2005/08/31 - 4232563 - Corrected net properties on R2/G2/B2 nets.

2005/08/27 - 4225433 - Changed PBUS voltage sense circuit.

2005/08/27 - 4230219 - Changed Y3301 to non-obsoleted part.

2005/08/28 - 4217524 - Added LEFT ALS connector (J6430).

DMS Release #05000-07000 (Proto 2 releases)

2005/08/28 - 4217535 - Added Left ALS FFC connector.

2005/08/28 - 4235203 - Changed BOM settings to stuff R2251.

2005/08/11 - 4214109 - Changed J4931 to proper 518S0342 part.

2005/10/11 - 4227308 - Deleted unnecessary MCH TVDAC filtering.

2005/10/07 - 4248911 - Sync with M38 & M42.

DMS Checkin #07004

DMS Checkin #07001

DMS Checkin #07002

2005/10/12 - 4298899 - Changed stuffing option to disable PLT_RST gating.

2005/10/12 - 4223808 - Power supply changes per vendor feedback.

DMS Checkin #07008

2005/08/28 - 4217535 - OMITs and tables to change 4-pin WTB connector parts.

2005/08/28 - 4225369 - OMITs and tables for staged LeMenu BOM approach.

DMS Checkin #07005

2005/10/12 - 4247941 - Added properties to resolve a PCB constraint issue.

2005/10/12 - 4298943 - Replaced last remaining non-RoHS compliant connector.

DMS Checkin #07009

2005/09/26 - 4239505 - Updated J4200 (old part no longer exists in library).

DMS Checkin #07003

2005/10/08 - 4286729 - Changed value of TPM Xtal caps.

2005/10/10 - 4295280 - Changed sleep LED connection per new SMC ERS.

2005/10/12 - 4248911 - Sync with M38 & M42.

2005/10/13 - 4247941 - Swapped pins at trackpad ESD protection diode.

2005/10/21 - 4235898 - Synced 2 pages from m9/mlb.

2005/08/28 - 4225369 - Changed ISL6269 PVCC aliases, added RC for 3.3V S5.2005/08/28 - 4225433 - Changed PBUS Voltage Sense circuit.

2005/08/28 - 4235217 - Added RC on Q3820 gate to slow down ODD FET turn-on.

2005/08/28 - 4227323 - Repinned Top-Case Flex connector.

2005/08/29 - 4225369 - Changed 3.3V S5 sequence to follow 5V S5 PGOOD.

2005/08/29 - 4227310 - Resolved sync issues with M38 (SB page 22).

2005/08/29 - 4227332 - Resolved sync issues with M38 (SMC page 58).

2005/08/30 - 4225433 - Fixed voltage divider values in PBUS VSense circuit.

2005/09/02 - 4244019 - Moved GPU-related power alias from PP3V3_S0 to PP3V3_S0_GPU.

2005/09/08 - 4214493 - Combined RTC coin cell diodes into dual-diode package.

2005/09/03 - 4232534 - Fixed documentation of battery address on I2C page.

2005/09/08 - 4247941 - Net property & name changes to support PCB/ICT requests.

2005/10/13 - 4247941 - Removed NO_TEST properties from CPU FSB strobe signals.

2005/10/13 - 4247941 - Unswapped pins at trackpad ESD protection diode.

2005/08/31 - 4240486 - Power line width & neck reductions at PCB request.2005/08/31 - 4240300 - Changed C6455 to a smaller part for cost & MCO.

2005/09/02 - 4241087 - Fixed pinout of USB D+/D- at camera connector to match FHB.

2005/10/08 - 4290735 - Swapped trackpad & PCIe Mini Card USB connections.

2005/10/10 - 4214847 - Changed 0-ohm resistor to solder jumper.

2005/10/12 - 4227320 - Updated SB pin name for GPIO 5 (ODD_PWR_EN_L).

2005/11/15 - 4298899 - Removed unused platform reset gate.

2005/11/16 - 4345498 - Updated Ethernet & FireWire crystal part numbers.

2005/08/31 - 4227306 - Swapped primary & alt part numbers for CPU VCore caps.

2005/08/31 - 4223808 - Various power supply R/C updates, plus some R/C adds.

2005/08/31 - 4214109 - Reversed pinout of J4931 to match updated PCB footprint.

2005/08/31 - 4240257 - Swapped some top & bottom EMC connections at DVI connector.

2005/09/02 - 4243269 - Inverted GPU VCore control, adjusted supply R values.

2005/09/03 - 4244539 - Added GPUVCORE_PGOOD to 1.2V, 1.8V, & 2.5V S0 sequence.

2005/11/16 - 4346184 - Inserted common-mode chokes on SATA R2D/D2R pairs.

(11.2.0)(11.1.0)

2005/11/19 - 4347717 - Changed SMS self-test pull-up to pull-down.

2005/11/16 - 4227333 - Fixed single-pin nets caused by SMC net name updates.

2005/11/18 - 4235898 - Changed C9710 GND connection per M9 request.

2005/11/16 - 4298899 - Fixed ethernet reset net name on page 26.

DMS Checkin #11001

2005/11/19 - 4350849 - Added option to connect SB_GPIO30 to ENET_LOM_DIS_L.2005/11/19 - 4340256 - Changed topcase flex trackpad power from 3.3V to 5V.

2005/09/30 - 4261313 - Added placeholder connector for IR FFC connector.


(11.3.0)


2005/10/06 - 4227330 - Added ESD protection on top-case USB port.


2005/10/12 - 4298905 - Changed ethernet VMAIN_AVLBL connection.2005/10/12 - 4214493 - Consolidated 0.22uF caps in design.

2005/10/12 - 4297684 - Split FW323 VSSA from VSS to reduce noise.

2005/10/11 - 4229560 - Changed SB GNT3#/GNT4# back to test points.

DMS Checkin #07006

2005/08/28 - 4235179 - Changed PBUS net names to merge PBUS A & PBUS B.2005/08/28 - 4235179 - OMIT and table to change 8-pin DC-In connector to 6-pin.2005/08/28 - 4227322 - Changed FW323 PCI_VIOS pin from 3.3V S0 to 3.3V S3.

2005/08/28 - 4221973 - Added pull-up for SB GPIO22 (REQ4#).

2005/08/28 - 4232563 - Changed analog video from Y/C/Comp to G2/R2/B2.

2005/08/27 - 4235401 - Moved a few pins at LIO BTB connector.

2005/09/03 - 4227315 - Changed SMBus pull-ups to 4.7K.

2005/09/03 - 4244484 - Changed P1V5S0_RUNSS circuit to work properly in G3Hot.

2005/09/02 - 4240486 - Adjusted line/neck widths, changed J4931 to 518S0371.

2005/10/17 - 4292633 - Changed remaining 10K NTCs to new 5% part.


(11.6.0)2005/09/29 - 4232826 - Swapped Vtt RPAK functions to free up unnecessary part.

2005/11/30 - 4331670 - Added CRITICAL flags to some more parts.

2005/11/22 - 4350840 - Swapped TMDS termination components for placement.

2005/09/28 - 4221965 - Added 2.2uF caps on SO-DIMM VREF pins.


2005/09/28 - 4278828 - Adjusted P5VS5_PGOOD R’s, added cap on PM_RSMRST_L.

2005/09/30 - 4282162 - Changed GPU BBN supply to MAX1673.

2005/09/30 - 4282349 - Added CRITICAL flags to parts identified in scrub.

2005/10/04 - 4256409 - Changed fan CTL series R’s to 2N7002 level-shifter.

2005/12/02 - 4363870 - Removed M1a support from BOM.

Changes from Proto Branch (DMS Release #04000):

2005/08/27 - 4235213 - Changed R8305, R8310, R8315 to slow down FET RCs.

2005/08/27 - 4227369 - Removed SMC options for display/backlight, now GPU-only.

2005/09/30 - 4248911 - Sync with M38 & M42.

2005/11/30 - 4351181 - Changed ITP connector BOM option.2005/11/30 - 4351196 - Changed IDE_RESET_L pull-down from 1K to 15K.2005/11/30 - 4358831 - Added pull-downs on two SB-to-SMC signals.

2005/12/01 - 4352020 - Changed 2.5V supply inductor to RoHS-compliant part.2005/10/04 - 4281394 - BOM option change to stuff right USB ESD protection part.

2005/11/30 - 4343864 - Added EMI/ESD parts at camera connector.

2005/12/01 - 4362404 - Changed TMDS diff term from 100-ohm to 180-ohm.

2005/12/01 - 4227340 - Changed supply for 1.8V S3 current sense amp.2005/12/01 - 4362566 - Restructured BOM for thick/thin PCB versions.2005/12/01 - 4347845 - RPAK pinswaps to LVDS pull-downs for PCB layout.

DMS Checkin #11003

2005/12/02 - 4363848 - Removed M56 GPU die rev B13 support from BOM.

2005/12/12 - 4235898 - Changes to LVDS net names to support mux option.2005/10/09 - 4214494 - Changed GPU VCore supply enable to use 1.2V/2.5V S3 PGOODs.

(13.1.0)2006/01/03 - 4362451 - Changed SCH/PCB/BOM part descriptions for Rev A.2006/01/03 - 4391436 - Swapped N/P signal names on one portion of SATA_R2D.2006/01/03 - 4347845 - Changed LVDS pull-downs from 10K to 8.2K.2006/01/03 - 4290282 - Removed BOM table, changed L9455 to 155S0002.

2006/01/05 - 4362566 - Removed 920- number for thin PCB option.2006/01/03 - 4362451 - Removed power jumpers and 0-ohm resistor.

2006/01/05 - 4394079 - Added BOMOPTION to SYS_ONEWIRE pull-up.

051-6941 A

104100

ASYNC_MASTER=N/A SYNC_DATE=N/A

www.vinafix.vn

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PHYSICALNET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

I70

I71

I72

I73

SYNC_DATE=(MASTER)

M1 Net Properties

051-6941 A

104104


ITPRESET_LCPU_ITPCPU_55S

CPU_VID<6..0>CPU_2TO1CPU_55SCPU_VID<6..0>CPU_2TO1CPU_55SCPU_VCCSENSE_PTHERM CPU_VCCSENSECPU_27P4S

SB_ACZ_BITCLKAUDIOAUDIO_55SACZ_BITCLKAUDIOAUDIO_55S

CLK_SLOW CLK_SLOW_55S

SPI SPI_55S

FSB_DPWR_LFSB_COMMONFSB_55S

FSB_REQ_L<4..0>FSB_ADDRFSB_55S

CPU_STPCLK_LCPU_55S

VGA VGA_75S

LVDS LVDS_100DTMDS TMDS_100D

PCIE PCIE_100D

TMDS_CLK_PTMDSTMDS

FSB_BNR_LFSB_COMMONFSB_55S

FSB_HITM_LFSB_COMMONFSB_55S

FSB_DEFER_LFSB_COMMONFSB_55S

SB_ACZ_SYNCAUDIOAUDIO_55S

TMDS_CLK_NTMDSTMDS

ACZ_SYNCAUDIOAUDIO_55S

ACZ_SDATAIN<0>AUDIOAUDIO_55SSB_ACZ_SDATAOUTAUDIOAUDIO_55SACZ_SDATAOUTAUDIOAUDIO_55S

ACZ_RST_LAUDIOAUDIO_55S

SB_ACZ_RST_LAUDIOAUDIO_55S

CLK_MED CLK_MED_55SCLK_PCIE CLK_PCIE_100D

IDE IDE_55S

FSB_HIT_LFSB_COMMONFSB_55S

CPU_THERMTRIP_LCPU_2TO1CPU_55S

FSB_IERR_LCPU_55S

DMI DMI_100D

FB_DATA FB_40S

FB_ADCTRL FB_35S_TO_55SFB_ADCTRL FB_55S

CPU_INIT_LCPU_55SCPU_SMI_LCPU_55S

MEM_DATA MEM_55S

MEM_CTRL MEM_45SMEM_CLK MEM_70D

MEM_CMD MEM_55S

FSB_ADS_LFSB_COMMONFSB_55S

FSB_BREQ0_LFSB_COMMONFSB_55S

XDP_BPM_L<5..0>CPU_ITPCPU_55SCPU_XDP_CLK_PCPU_ITPCLK_FSB_100D

CPU_COMP<0>CPU_COMPCPU_27P4S

IMVP6_VSEN_NCPU_VCCSENSECPU_27P4S

CPU_VCCSENSE_NTHERM CPU_VCCSENSECPU_27P4S

FSB_A_L<31..3>FSB_ADDRFSB_55S

FSB_FERR_LCPU_55S

IMVP_DPRSLPVRCPU_2TO1CPU_55S

CPU_PWRGDCPU_55S

CPU_NMICPU_55SCPU_A20M_LCPU_55SCPU_DPSLP_LCPU_55SCPU_IGNNE_LCPU_55S

PM_DPRSLPVRCPU_2TO1CPU_55S

CPU_GTLREFCPU_GTLREFCPU_55SCPU_COMP<3>CPU_COMPCPU_55SCPU_COMP<2>CPU_COMPCPU_27P4S

FSB_DSTBN_L<3..0>FSB_DSTBFSB_55S

FSB_DINV_L<3..0>FSB_DATAFSB_55SFSB_DSTBP_L<3..0>FSB_DSTBFSB_55S

FSB_DBSY_LFSB_COMMONFSB_55S

FSB_CPURST_LFSB_COMMONFSB_55S

FSB_TRDY_LFSB_COMMONFSB_55S

CLK_FSB CLK_FSB_100D

FW FW_110D

USB2 USB2_90D

FSB_RS_L<2..0>FSB_COMMONFSB_55S

FSB_DRDY_LFSB_COMMONFSB_55S

FSB_D_L<63..0>FSB_DATAFSB_55S

FSB_ADSTB_L<3..0>FSB_ADSTBFSB_55S

CPU_INTRCPU_55S

IMVP6_VSEN_PCPU_VCCSENSECPU_27P4S

CPU_XDP_CLK_NCPU_ITPCLK_FSB_100D

FSB_BPRI_LFSB_COMMONFSB_55S

SMB SMB_55S

CPU_COMP<1>CPU_COMPCPU_55S

ENET ENET_100D

SATA SATA_100D

FB_CLK FB_75D

MEM_DQS MEM_85D

FSB_LOCK_LFSB_COMMONFSB_55S

TMDS_CLK_F_NTMDSCONNTMDSCONN

TMDS_CLK_F_PTMDSCONNTMDSCONN

TMDS_DATA_P<5..3>TMDSTMDS

TMDS_DATA_P<2..0>TMDSTMDS

TMDS_DATA_N<5..3>TMDSTMDS

TMDS_DATA_N<2..0>TMDSTMDS

TMDS_DATA_F_P<5..3>TMDSCONNTMDSCONN

TMDS_DATA_F_P<2..0>TMDSCONNTMDSCONN

TMDS_DATA_F_N<5..3>TMDSCONNTMDSCONN

TMDS_DATA_F_N<2..0>TMDSCONNTMDSCONN

79

79

45

12

75

12

12

75

45

45

45

45

12

12

12

12

57

12

12

12

12

12

12

12

12

12

75

75

75

75

9

9

57

21

12

7

21

74

7

7

12

74

21

21

21

21

7

21

21

7

7

11

34

57

7

21

21

21

21

21

23

7

7

7

7

11

12

12

7

7

7

21

34

12

7

74

74

74

74

11

8

8

8

21

5

7

5

7

73

5

5

7

21

73

5

5

21

5

5

21

5

7

7

7

5

5

7

11

7

57

8

5

57

7

7

7

7

7

14

7

7

7

5

5

5

5

7

7

7

5

5

5

7

57

11

7

7

5

75

75

73

73

73

73

75

75

75

75

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