8085 interrupts

8085 Interrupts

• Maskable– INTR– RST vectored

• Non-Maskable– TRAP

• Vectored– RST5.5, RST6.5, RST7.5, TRAP

Interrupt process

• enable by writing EI.• mp checks INTR line at each instruction.• if INTR is high, mp completes the current instr, disables

Interrupt Flip-flop, sends INTA signal.• An RST instru is inserted by INTA through external

hardware.• Mp saves the memory address of the next instru into

stack. Program control is transferred to CALL location. The service routine starts at CALL location.

• At the end of the subroutine Int Flag is enabled again by EI instru.

• The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

RST instructions

• 8 RST instructionsMnemon

icsBinary code Hex Call

Location

D7 D6 D5

D4

D3D

2D

1D

0

RST0 1 1 0 0 0 1 1 1 C7 0000

RST1 1 1 0 0 1 1 1 1 CF 0008

RST2 1 1 0 1 0 1 1 1 D7 0010

RST3 1 1 0 1 1 1 1 1 DF 0018

RST4 1 1 1 0 0 1 1 1 E7 0020

RST5 1 1 1 0 1 1 1 1 EF 0028

RST6 1 1 1 1 0 1 1 1 F7 0030

RST7 1 1 1 1 1 1 1 1 FF 0038

+5v

Enable

1

1

1

1

1011 E

F to data bus

LXI SP, XX99H

EI

MVI A, 00H

NXTCNT: OUT PORT1

MVI C, 01H

CALL DELAY

INR A

JMP NXTCNT

XX70: SERV: PUSH BPUSH PSWMVI B, 0AHMVI A, 00H

FLASH: OUT PORT1MVI C, 01HCALL DELAYCMADCR BJNZ FLASHPOP PSWPOP BEIRET

Main programService routine

Interrupt instr: EFAt 0028H JMP xx70H

Write a program to count continuously in binary with one second delay between each Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with some appropriate delay between flash

Issues in implementing interrupts

• Is there a minimum pulse width required for the INTR signals?– MP checks INTR, one clk period before the

last-T state of an instruction cycle, therefore, the INTR pulse should be high at least for 17.5 T-states.

• How long can the INTR pulse stay high?• Can the MP be interrupted again before

the completion of the first interrupt service routine?