8086 interrupt

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Page 1 of 9 INTERRUPT The meaning of ‘interrupts’ is to break the sequence of operation. While the cpu is executing a program, on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main program. Purpose of Interrupts Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate. Interrupt Sources Hardware Interrupts (External Interrupts) ex: NMI, INTR Software Interrupts (Internal Interrupts and Instructions) ex: INT n (Software Instructions) 8086 Interrupt Response ISR procedure PUSH registers Mainline Program POP registers IRET 1. It decrements SP by 2 and pushes the flag register on the stack. 2. Disables INTR by clearing the IF. 3. It resets the TF in the flag Register. 5. It decrements SP by 2 and pushes CS on the stack. 6. It decrements SP by 2 and pushes IP on the stack. 6. Fetch the ISR address from the interrupt vector table. 1 PUSH Flags CLEAR IF , TF PUSH CS PUSH IP FETCH ISR ADDRESS POP IP POP CS POP FLAGS

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INTERRUPT The meaning of ‘interrupts’ is to break the sequence of operation. While the cpu is executing a program, on ‘interrupt’ breaks the normal sequence of executionof instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back againto the main program.Purpose of Interrupts Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.Interrupt Sources

Hardware Interrupts (External Interrupts) ex: NMI, INTR

Software Interrupts (Internal Interrupts and Instructions) ex: INT n (Software Instructions) 8086 Interrupt Response ISR procedure PUSH registersMainline Program

POP registers IRET

1. It decrements SP by 2 and pushes the flag register on the stack.

2. Disables INTR by clearing the IF.3. It resets the TF in the flag Register.5. It decrements SP by 2 and pushes CS on the stack.6. It decrements SP by 2 and pushes IP on the stack.6. Fetch the ISR address from the interrupt vector table. Interrupt Vector Table –The first 1Kbyte of memory of 8086 (00000 to 003FF) is set aside as a table for storing the starting addresses of Interrupt Service Procedures (ISP).–Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. –The starting address of an ISP is often called the Interrupt Vectoror Interrupt Pointer. Therefore the table is referred as Interrupt Vector Table. –In this table, IP value is put in as low word of the vector & CS is put in high vector.

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PUSH Flags CLEAR IF , TF PUSH CS PUSH IP FETCH ISR ADDRESS

POP IP POP CS POP FLAGS

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Sprcified interrupts:- Type 0 POINTER(DIVIDE ERROR) Type 1 POINTER(SINGLE STEP) Type 2 POINTER (NON-MASKABLE) Type 3 POINTER (BREAK POINT) Type 4 POINTER (OVERFLOW) Functions associated with INT00 to INT04 (Exceptions) INT 00 (divide error) - INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero -ISR is responsible for displaying the message “Divide Error” on the screen Ex1: Mov AL,82H ;AL= 82 SUB CL,CL ;CL=00 DIV CL ;82/0 = undefined result INT 01

- For single stepping the trap flag must be 1 After execution of each instruction, 8086 automatically jumps to00004H to fetch 4 bytes for CS: IP of the ISR -The job of ISR is to dump the registers on to the screen Resetting TF (TF = 0)

First method: PUSH F POP AX AND AX, 1111 1110 1111 1111 B PUSH AX POP F Second method: PUSH F MOV BP,SP AND 0(BP), OFE FFH POP F

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Setting TF (TF = 1) Use OR instruction in place of AND instruction. PUSH F POP AX OR AX, 0000 0001 0000 0000 B PUSH AX POP F INT 02 (Non maskable Interrupt) 8086 NMI 5v When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to physical memory location00008 to fetch CS:IP of the ISR assocaiated with NMI INT 03 (break point) -A break point is used to examine the cpu and memory after the execution of a group of Instructions. -It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte instructions. INT 04 ( Signed number overflow) -There is an instruction associated with this INT 0 (interrupt on overflow). -If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1. -In case where 0F = 0 , the INT 0 is not executed but is bypassed and acts as a NOP. Example Mov AL , 64 Mov BL , 64 ADD AL , BL INT 0 ; 0F = 1 0100 0000 0100 0000 1000 0000 +64 +64 +128

Interrupt priority structure Interrupt Priority Divide Error, INT(n),INTO Highest NMI INTR Single Step Lowest

Interrupt Sequence in an 8086 system 1. One or more IR lines are raised high that set corresponding IRR bits.2. 8259A resolves priority and sends an INT signal to CPU.3. The CPU acknowledges with INTA pulse.4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive data bus

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during this period. 5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on to data bus from where it is read by the CPU. 6. This completes the interrupt cycle. The ISR bit is reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine.

FUNCTIONAL BLOCK DIAGRAM OF 8259:1. Control logic2. Read Write logic3. Data bus buffer4. Interrupt Request Register (IRR)5. In-Service Register (ISR)6. Interrupt Mask Register (IMR)7. Priority Resolver (PR)8. Cascade buffer.

1. Interrupt Request Register (IRR):- –The interrupts at IRQ input lines are handled by IRR internally. IRR stores all the interrupts in it, in order to serve them one by one on the priority basis. 2.In-Service Register (ISR):- This register stores all the interrupt requests those are being

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served, i.e ISR keeps a track of the requests being served. 3.Priority Resolver:- This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected & stored into the corresponding bit during INTA pulse. IR0 - highest priority IR7 -lowest priority ; in fixed priority. 4.Interrupt Mask Register (IMR):- This register stores the bits required to mask the interrupts inputs. IMR operates on IRR at the direction of the Priority Resolver. 5. Interrupt Control logic:- –This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the 8 interrupt requests. –This also accepts the interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus. 6. Data Bus Buffer:- –This Tri-state bidirectional buffer interfaces internal 8259A bus the microprocessor data bus. –Control words, status & vector information pass through data buffer during read or write operations. 7. Read/Write Control logic:- –This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus.8. Cascade Buffer/Comparator:- –This block stores & compares the IDs of all the 8259As used in the system. –The 3 I/O pins CAS0 – CAS2 are outputs when the 8259A is used as a master. –The same pins used as inputs when it is in the slave mode. –8259A in master mode, sends the ID of the interrupting slave device on these lines. In slave, will send its pre-programmed vector address on the data bus during the next INTA pulse.CS base address IP offset Interrupt Vector Table INT Number Physical Address INT00 00000 INT 01 00004 INT 02 00008 : :

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: : INT FF 003FC Example Find the physical address in the interrupt vector table associated with b) INT 12H b) INT 8H Solution: a) 12H * 4 = 48H Physical Address: 00048H ( 48 through 4BH are set aside for CS & IP)b) 8 * 4 = 20HMemory Address : 00020HDifference between INT and CALL instructions Externally activated hardware interrupt can come at any time Used by the programmer in the sequence of instructions in the program Goes to fixed memory location in the interrupt vector table to get address of ISR Can Jump to any location with in 1MB address range1. INT CALL IRET to pops of F, CS:IP RET is the last instruction 2. In addition to CS:IP, Flags can be saved Automatically saves CS: IP of next instruction3. INTR can be masked Cannot be masked (disabled) 4. INT CALL

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