8086 pin functions_a

7/31/2019 8086 Pin Functions_A

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Data Bus (AD0 AD15):

These 16 pins are used as Address and data bus.

During T1 state this lines provides address anddata lines are valid only during T2 to T4.


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Address bus (AD0 AD 15, A16/S3 A19/S6):

This 20 lines are correspond to the CPUs 20-bit address.

These lines are valid only during T1 state.

S6 : always remain a logic 0

S5 : indicate condition of IF flag bits


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ALE (Address Latch Enable): Signal output on this pin can be used to

Demultiplex the address , data bus and statuslines. ALE pulse is high during T1 state.

M/IO :

The 8086 does not output separate memory andI/O signals. Instead , the M/IO signal output duringearly in T1 state. So if M/IO = 1 then it is memoryoperation or M/IO = 0 then IO operation.


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Read (RD): This active low output signal indicates that the

direction of data flow from memory or IO to CPU. It

can be combined with M/IO to generate MEMR andIOR signals.

Write(WR): This active low output signal indicates that the

direction of data flow from CPU to memory or IO. Itcan be combined with M/IO to generate MEMW andIOW signals.


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Clock (CLK):

All events in the microprocessor are synchronizes to

the system clock applied to CLK pin.

BHE / S7:

This signal is multiplexed with the S7 status indicator.

It is output only during the T1 state. BHE and A0 aretypically used to select even or odd memory banks.


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BHE A0 Action

0 0 Access 16-bit word

0 1 Access odd byte to D8- D15

1 0 Access even byte to D0-D7

1 1 No action


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Ready: READY : this signal is samples during rising edge of the T2

clock pulse. If this line found low an extra T3 state isinserted by the processor. This is the acknowledgement

from the slow device or memory that they havecompleted the data transfer.

TEST : This input is examined by a WAIT instruction. If the TEST

pin goes low, execution will continue, else the processorremains in an idle state. WAIT is then prefix to those 8086instructions that reference data operated on by the 8087 .Driven by Numeric coprocessor 8087.


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INTR-Interrupt Request : This is a triggered input. This is sampled during

the last clock cycles of each instruction todetermine the availability of the request. If anyinterrupt request is pending, the processor entersthe interrupt acknowledge cycle.

This can be internally masked by resetting theinterrupt enable flag. This signal is active high andinternally synchronized.


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INTA Interrupt Acknowledge : This signal is used as a read strobe for interrupt

acknowledge cycles. i.e. when it goes low, the

processor has accepted the interrupt.

DT/R Data Transmit/Receive:

This output is used to decide the direction of dataflow through the transreceivers (bidirectional buffers).When the processor sends out data, this signal is highand when the processor is receiving data, this signalis low.


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DEN Data Enable :

This signal indicates the availability of valid data

over the address/data lines. It is used to enablethe transreceivers ( bidirectional buffers ) toseparate the data from the multiplexed

address/data signal. It is active from the middle of

T2 until the middle ofT4.


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HOLD, HLDA-Acknowledge :

When the HOLD line goes high, it indicates to the

processor that another master is requesting thebus access. The processor, after receiving theHOLD request, issues the hold acknowledge

signal on HLDA pin, in the middle of the next

clock cycle after completing the current bus cycle.


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NMI : non-maskable interrupt

similar to INTR except that no check IF flag bit

if NMI is activated : use interrupt vector 2

RESET :

: reset if RESET held high for a minimum of four clock

cycle

VCC(power supply) : +5.0V, 10%


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GND(Ground) : GND MN/MX : select either minimum or maximum mode

Minimum mode Pins M/IO WR INTA

HOLD HLDA DEN ALE


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MN/MX = 0(ground)

S2,S1,S0:indicate function of current bus cycle

these signal : normally decoded by 8288 bus controller


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Request / Grant (RQ0/GT0 , RQ1/GT1) : these two pins are

bidirectional, allowing a coprocessor to request control of the

system buses ( similar to HOLD and HLDA in minimum

mode). The 8086 respond by disconnecting itself from thesystem buses and pulsating the RQ/GT line in

acknowledgement.


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LOCK(lock output): lock is an output signal intended for usein a bus arbitration scheme with another processor. Arbitration

refers to the process of determining which processor shouldhave the control of the system buses at any given time. The

LOCK signal is output low during the execution of any

instruction with LOCK prefix.


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QS1, QS0(queue status) :

show status of internal instruction queue

provided for access by the numeric coprocessor(8087)

They allow the coprocessor to track the progress of aninstruction through the queue.


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clock generation, RESET synchronization, READY

synchronization, and TTL-level peripheral clock signal


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AEN(address enable) input : cause to enable memory

control signals

CEN(control enable) input: enable the command output

IOB(I/O bus mode) input : select either system bus or I/Obus mode mode operation

AIOWC(advanced I/O write command) output : provide

I/O with its advanced I/O write control signal

IOWC(I/O write) : provide I/O with its main write signal

IORC, AMWC, MWTC, MRDC

INTA(interrupt acknowledge) output :

8086 pin functions_a

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