8259-INTERRUPT CONTROLLER AIM: Generate an Interrupt using 8259 Interrupt Controller

a) To display the pulse counter. b) To derive the frequency counter.

APPARATUS: 1. ESA 86/88-2 Microprocessor kit. 2. Function generator. 3. Connecting wires.

THEORY: The Processor 8085 had five hardware interrupt pins. Out of these five interrupt pins, four pins were allotted fixed vector addresses but the pin INTR was not allotted any vector address, rather an external device was supposed to hand over the type of the interrupt to the microprocessor. The microprocessor then gets this type and derives the interrupt vector address from that. Consider an application where a number of I/O devices connected with CPU desire to transfer data using interrupt driven data transfer mode. In this type of applications more number of interrupts are required than available in typical microprocessor. Moreover ,in this multiple interrupts systems the processor will have to take the care of priorities for the interrupts, simultaneously occurring at the interrupt request pins to overcome all this difficulties, we require a Programmable interrupt controller which is able to handle a number of interrupts at a time.8259A was operated with 8-bit as well as 16-bit processors. PORT ADDRESSES OF 8279 Control word register = FFF4 Data Port Address = FFF6 8259INTERFACING

Architecture of 8279:

PROGRAM: PULSE COUNTER Main program:

Memory address

Op codes labels

Mnemonics

Operands

Comments

2000 2006 200C 2012 2015 2017 2018 201B 201D 201E 2020 2021 2023 2024 2025

C7,06,00,30,00,00 C7,06,20,01,50,20 C7,06,22,01,00,00 BA,F4,FF B0,13 EE BA,F6,FF B0,48 EE B0,03 EE B0,FE EE FB EB,FE

L1:

MOV MOV MOV MOV MOV OUT MOV MOV OUT MOV OUT MOV OUT STI JMP

[3000],0000H [0120],2050H [0122],0000H DX,FFF4H AL,13H DX,AL DX,FFF6H AL,48H DX,AL AL,03H DX,AL AL,FEH DX,AL L1

;Initial cnt.0 ; ISR addr .in INT vector location. ;Initialize 8259 in edge triggered interrupt ,8086 processor, automatic end of interrupt , interrupt no. 0 ;Keep monitoring the interrupt

Delay subroutine:

Memory address

Op codes labels Mnemonics

Operands

Comments

2050 2053 2055 2056 2059 205E

A1,00,30 04,01 27 A3,00,30 9A,0A,0B,00,FF CF

MOV ADD DAA MOV CALL IRET

AX,[3000] AL,01H [3000],AX FF00:0B0A

; Increment the counter by 1. ;Display count ;Back to main.

Output: FREQUENCY COUNTER Main program:

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2006 200C 2012 2015 2017 2018 201B 201D 201E 2020 2021 2023 2024 2025 2028 202B 202C 202D 202F 2030 2032 2037

C7,06,00,30,00,00 C7,06,20,01,50,20 C7,06,22,01,00,00 BA,F4,FF B0,13 EE BA,F6,FF B0,48 EE B0,03 EE B0,FE EE FB BB,0C,00 B9,02,63 90 49 75,FC 4B 75,F6 9A,0A,0B,00,FF EB,FE

L2: L1: L3:

MOV MOV MOV MOV MOV OUT MOV MOV OUT MOV OUT MOV OUT STI MOV MOV NOP DEC JNZ DEC JNZ CALL JMP

[3000],0000H [0120],2050H [0122],0000H DX,FFF4H AL,13H DX,AL DX,FFF6H AL,48H DX,AL AL,03H DX,AL AL,FEH DX,AL BX,000CH CX,6302H CX L1 BX L2 FF00:0B0A L3

;Initial cnt.0 ; ISR adder .in INT vector location. ;Initialize 8259 in edge triggered interrupt ,8086 processor, automatic end of interrupt , interrupt no. 0 ;Activate interrupt ; Initialize counters for 1 sec delay. ; Wait for 1sec. ;Display the frequency value.

Interrupt service subroutine:

Memory address

Op codes labels Mnemonics

Operands

Comments

2050 2053 2055 2056 2059

A1,00,30 04,01 27 A3,00,30 CF

MOV ADD DAA MOV IRET

AX,[3000] AL,01H [3000],AX

;Count the pulses ; Back to main.

Input: Output: RESULT: The count of the pulses is displayed on the microprocessor data field and the frequency is measured and displayed.

8279-KEYBOARD DISPLAY AIM: WRITE A PROGRAM TO DISPLAY

1) A Single Characters. 2) String of characters. 3) Read the character and display

APPARATUS: ESA 86/88-2 Microprocessor kit. THEORY: Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives the display of a system and interfaces a key board with the CPU, leaving it free for its routine task .The keyboard display interface scans the keyboard to identify if any key has been pressed and sense the code of the pressed key to Performed by the controller in repetitive fashion with out involving the Cup-Tie keyboard is interfaced either in interrupt mode or polled mode. In the interrupt mode the processor is requested service only if any key is pressed otherwise the CPU can proceed with its main task. In the polled mode the CPU periodically reads an internal flag of 8279 to check for a key pressure. The keyboard section can interface an array of a maximum of 64 keys with the CPU. The keyboard entries are debounced and stored in 8-byte FIFO RAM that is further accessed by the CPU to read the key codes. If more than 8-characters are entered in the FIFO. Before any FIFO read operation the overrun status is set. The 8279 is normally provides maximum of sixteen 7 segment Display interface with CPU. PORT ADDRESSES OF 8279 Control word register = FFEB Data Port Address = FFE9 8279A Interfacing:

8279 INTERNAL ARCHITECTURE

8086

8279

7-seg

display

PROGRAM: To display string of characters

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2008 2009 200B 200C 200F 2012 2015 2017 2018 2019 201A 201C

BA,EB,FF B0,00 EE B0,38 EE B0,90 EE BE,00,30 B9,LENGTH BA,E9,FF 8A,04 EE 46 49 75,F9 EB,FE

L1: L2:

MOV MOV OUT MOV OUT MOV OUT MOV MOV MOV MOV OUT INC DEC JNZ JMP

DX,FFEBH AL,00H DX,AL AL,38H DX,AL AL,90H DX,AL SI,3000H CX,LENGTH DX,FFE9H AL,[SI] DX,AL SI CX L1 L2

; Initialize 8279 in encoded scan keypad 2key lock out,8char display left entry. ;Select display position 0 ;Display the string of characters

Input: Output: PROGRAM: To display single character

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2008 2009 200B 200C 200F 2011 2012

BA,EB,FF B0,00 EE B0,38 EE B0,90 EE BA,E9,FF B0,CHAR EE EB,FE

L1:

MOV MOV OUT MOV OUT MOV OUT MOV MOV OUT JMP

DX,FFEBH AL,00H DX,AL AL,38H DX,AL AL,90H DX,AL DX,FFE9H AL,CHAR DX,AL L1

; Initialize 8279 in encoded scan keypad 2key lock out, 8char display left entry. ;Select display position 0 ;Display the character

Input: Output:

To read the character and display

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2008 2009 200C 200D 200F 2011 2013 2014 2017 2018 201B 201D 201F 2022 2024 2025 2028 202A 202B

BA,EB,FF B0,00 EE B0,38 EE BA,EB,FF EC 24,07 74,F8 B0,40 EE BA,E9,FF EC BE,00,40 B4,00 0B,F0 BA,EB,FF B0,90 EE BA,E9,FF 8A,04 EE EB,DC

L1:

MOV MOV OUT MOV OUT MOV IN AND JZ MOV OUT MOV IN MOV MOV OR MOV MOV OUT MOV MOV OUT JMP

DX,FFEBH AL,00H DX,AL AL,38H DX,AL DX,FFEBH AL,DX AL,07 L1 AL,40H DX,AL DX,FFE9H EC SI,4000H AH,00H SI,AX DX,FFEBH AL,90H DX,AL DX,FFE9H AL,[SI] DX,AL L1

;Initialize 8279 in encoded scan keypad 2key lock out,8char display left entry. ; scan the key board for key press.

;read the character

; get the address of the character code. ;Select display position 0 ;Display the key no. pressed; wait for next key.

Input: Output: RESULT: A character is displayed at 0 position of the display. A string characters is displayed on left entry basis. A character is read from the keyboard and displayed the key no on the display using look-up table method.

8251- UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

AIM: To transfer a block of data and to receive a block of data. APPARATUS: ESA 86/88-2 Microprocessor kits—2n0s. R S 232 Cable. THEORY:

Intel’s 8251A is a Universal Asynchronous receiver and transmitter compatible with Intel’s processors. This may be programmed to operate in any of the serial communication modes built in to it.

This chip converts the parallel data in to serial stream of bits suitable for serial transmission. It is able to receive a serial stream of bits and convert in to parallel data bytes to be read by a microprocessor.

The data transmission between two points involves unidirectional or bidirectional transmission of meaningful digital data through a media. There are basically three modes of data transmission.

a) Simplex

b) Duplex

c) Half-duplex

In simplex mode data is transmitted only in one direction over a Single communication channel. In Duplex mode data may be transferred between two transceivers. In both directions simultaneously. In half-duplex mode data transmission may take place in either direction, but at a time data may be transmitted only in one direction. PORT ADDRESSES OF 8279 Control word register = FFF2

Data Port Address = FFF0

8251A Interfacing

FUNCTIONAL BLOCK DIAGRAM OF 8251 USART

PROGRAM: Transmitter

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2009 200B 200C 200F 2011 2012 2015 2017 2019 201A 201D 201F

BA,F2,FF B0,00 EE B9,02,00 E2,FE EE B9,02,00 E2,FE EE B9,02,00 E2,FE B0,40 EE B9,02,00 E2,FE B0,CE

L1: L2: L3: L4:

MOV MOV OUT MOV LOOP OUT MOV LOOP OUT MOV LOOP MOV OUT MOV LOOP MOV

DX,FFF2H AL,00H DX,AL CX,0002H L1 DX,AL CX,0002H L2 DX,AL CX,0002H L3 AL,40H DX,AL CX,0002H L4 AL,CEH

; Soft ware reset 8251. ;activate both Txer and Rxer with communication parameters b.r.f

I

N

T

E

R

N

A

L

B

U

S

RECEIVER

BUFFER

(S—P)

TRANSMIT

CONTROL

TRANSMIT

BUFFER

(P—S)

RECEIVE

CONTROL

DATA BUS

BUFFER

TxD

TxRdy

TxEMPT

TxC

RxD

RxRdy

___

RxC

SYNDET/

BRKDET

READ/

WRITE

CONTROL

LOGIC

MODEM

CONTROL

D7-D0

RESET

CLK

C/D

__

RD

__

WR

__

CS

___

DSR

__

DTR

__

CTS

__

RTS

2021 2022 2025 2027 2029 202A 202D 2030 2033 2034 2036 2028 203A 203D 203F 2040 2041 2042 2044

EE B9,02,00 E2,FE B0,37 EE B9,0A,00 BE,00,30 BA,F2,FF EC 24,81 3C,81 75,F9 BA,F0,FF 8A,04 EE 46 49 75,EC CC

L5: L7: L6:

OUT MOV LOOP MOV OUT MOV MOV MOV IN AND CMP JNZ MOV MOV OUT INC DEC JNZ INT

DX,AL CX,0002H L5 AL,37H EE CX,000AH SI,3000H DX,FFF2H AL,DX AL,81H AL,81H L6 DX,FFF0H AL,[SI] DX,AL SI CX L7 03

16,char length 8,no stop bits,2 start bits, no parity. ;transmitting block length 10, start addr.3000 ;wait for Txer ready ;transmit the total block on polling basis

Receiver

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2009 200B 200C 200F 2011 2012 2015 2017 2019 201A 201D 201F 2021 2022 2025 2027 2029 202A 202D 2030

BA,F2,FF B0,00 EE B9,02,00 E2,FE EE B9,02,00 E2,FE EE B9,02,00 E2,FE B0,40 EE B9,02,00 E2,FE B0,CE EE B9,02,00 E2,FE B0,37 EE B9,0A,00 BE,00,30 BA,F2,FF

L1: L2: L3: L4: L5: L7:

MOV MOV OUT MOV LOOP OUT MOV LOOP OUT MOV LOOP MOV OUT MOV LOOP MOV OUT MOV LOOP MOV OUT MOV MOV MOV

DX,FFF2H AL,00H DX,AL CX,0002H L1 DX,AL CX,0002H L2 DX,AL CX,0002H L3 AL,40H DX,AL CX,0002H L4 AL,CEH DX,AL CX,0002H L5 AL,37H EE CX,000AH SI,3000H DX,FFF2H

;software reset 8251. ; activate both Txer and Rxer with communication parameters b.r.f 16, char length 8, no stop bits, 2 start bits, no parity. ;receiving block length 10, start addr.3000

2033 2034 2036 2038 203B 203D 203F 2040 2041 2042

EC 24,81 75,FB BA,F0,FF 8A,04 EE 46 49 75,EE CC

L6:

IN AND JNZ MOV MOV OUT INC DEC JNZ INT

AL,DX AL,02H L6 DX,FFF0H AL,[SI] DX,AL SI CX L7 03

;wait for Rear ready ;receive the total block on polling basis

Input: Output: RESULT: A block of 10 bytes is transmitted from the location 3000. A block of 10 bytes is received and stored at location 3000.

8255- PROGRAMMABLE PERIPHERAL INTERFACE (PPI) AIM: To generate square wave. To control the speed & direction of stepper motor. APPARATUS: ESA 86/88-2 Microprocessor kit. C.R.O. Stepper motor interface module with stepper motor. F R C Cable. Power supply- +15v. THEORY: The parallel input-output port chip 8255 is also called as Programmable peripheral input-output Port. The Intel’s 8255 are designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in 2-groups of 12 lines each, or 3 groups of 8 lines .The two groups of I/O pins are named as GROUP A and GROUP B. Each of these two groups contain a sub group of 8 I/O lines called as 8-bit Port and other sub group of 4 I/O lines are a 4-bit port. Thus GROUP A Contains an 8-bit port A along with a 4-bit port, C upper. Port lines are identified by symbols PAO-PA7, While the port C lines are identified as PC4-PC7 .Similarly group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0-PC3 .The port C upper and port C lower can be used in recombination as an 8-bit port-C .Both the port Cs are assigned the same address. Thus one may have either Three 8-bit I/O ports are two 8-bit and two 4-bit I/O ports from 8255.All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as Control word register (CWR). PORT ADDRESSES OF 8255 Control word register = FFE7 Port A = FFE1 Port B = FFE3 Port AC = FFE5 Block diagram of 8255 Interfacing

Stepper motor

inter face

8255

PPI

Micro

processor

8086

Block diagram of 8255 programmable peripheral interface:

SQUARE WAVE GENERATION PROGRAM: Main program:

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2009

BA,E7,FF B0,80 EE BA,E1,FF B0,FF

MOV MOV OUT MOV MOV

DX,FFE7H AL,80H DX,AL DX,FFE1H AL,FFH

;Initialize 8255 all ports o/p ;Make port a high

Group

A

control

Group

B

control

Group

A

Port A

(8)

Group A

Port

C upper (4)

Group

B

Port C lower

(4)

Group

B

Port B

(8)

DATA

BUS

BUFFER

Read/

write

Control

logic

8 bit internal bus

I/O

PA7-PA0

I/O

PC7-PC4

I/O

PC3-PC0

I/O

PB7-PB0

BIDIRECTIOAL DATA BUS

BUFFER

D7--D0

POWER

SUPPLIES

+5V

GND

__ RD

__

WR

A1

A0

RESET

__

CS

200B 200C 200F 2011

EE E8,11,00 F6,D0 EB,F8

L1: OUT CALL NOT JMP

DX,AL DELAY AL L1

;Wait for on/off Compliment port A continuously

Delay subroutine:

Memory address

Op codes labels Mnemonics

Operands

Comments

2020 2023 2026 2027 2028 202A 202B 202D

BB,01,00 B9,99,00 90 49 75,FC 4B 75,F6 C3

L3: L2:

MOV MOV NOP DEC JNZ DEC JNZ RET

BX,0001H CX,0099H CX L2 BX L3

;Initialize the counters for delay ;Wait for 0.5 ms.

Output

STEPPER MOTOR PROGRAM: Main program:

Memory address

Op codes labels Mnemonics

Operands

Comments

2000 2003 2005 2006 2009 200B 200C 200F 2011

BA,E7,FF B0,80 EE BA,E1,FF B0,FF EE E8,11,00 D0,C8/C0 EB,F8

L1:

MOV MOV OUT MOV MOV OUT CALL ROR/ROL JMP

DX,FFE7H AL,80H DX,AL DX,FFE1H AL,88H DX,AL DELAY AL L1

;Initialize 8255 all ports o/p ; Start stepper motor in half step mode. ;Wait for step time ;Rotate the stepper motor continuously

Delay subroutine:

Memory address

Op codes labels Mnemonics

Operands

Comments

2020 2023

BB,0A,00 B9,02,5D

L3:

MOV MOV

BX,000AH CX,5D02H

;Initialize the counters for

2026 2027 2028 202A 202B 202D

90 49 75,FC 4B 75,F6 C3

L2: NOP DEC JNZ DEC JNZ RET

CX L2 BX L3

delay ;Wait for 1 sec.

Output:

RESULT: 1. Amplitude and time period of the square wave are measured. 2. Stepper motor is rotated in both clockwise and anti-clockwise directions.

INTRODUCTION TO 8051 MICROCONTROLLER: Feature of 8051 Microcontroller:

1. ESA 51e operates on single +5v power supply either in stand alone mode using PC keyboard and LCD or with host PC through its RS-232C interface in serial mode implemented using the On-chip serial port of Microcontroller.

2. Stand alone and serial monitor programs support the entry of user programs editing and debugging facilities like single stepping and full speed execution of user programs.

3. Total On-board memory is 128Kbytes of which 88K bytes RAM has back-up provision.

4. I/O lines and four programmable interval timers. 5. INTERRUPTS:

EXTERNAL: INT is used for implementing single stepping and user’s break switching is available to user.

INTERNAL: Internal timer and serial interrupts are used by the system monitor. COMMANDS: A- Assembler: ESA 5E provides the powerful, PROM resident one-line assembler to enhance development work. This assembler supports the entire standard mnemonics and addressing modes of Intel /5 microcontrollers.

Function: The assembler generates the actual machine and stores them in the memory locations defined by the program. Also, the system will display the codes generated as well as the source statements. Any error detected is also displayed on the screen. C- Compare a block of memory with destination block Function: Compare command can be used to compare the contents of one memory block with the content of another memory block. F-Fill memory: Fill a block of memory with a constant or search a string of data in program memory, external data memory and internal data memory. Function: This command is used to fill a block of memory with specified constant. G- Go command: Transfer the processor control from the monitor to user program. Function: The GO command is used to transfer the control of the system from monitor to the users Program. H- Help command: List all the commands supported by serial monitor. Function: The help command is used to list all the commands supported by the monitor. J-Jump to address: Function: The J command is used to change the program counter value to the desired address before executing a program by either GO command or SINGLE STEP command. M-Modify/Display/Move memory: Modify/Display/Move memory contents in program memory, external data memory and internal data memory with all combinations Function: The M Modify memory command is used to examine the contents of specified memory locations. Further if location are in RAM their contents can be altered if desired and block move contents of memory from program, data or internal memory to program or data or internal memory for all combinations.

The M Display memory command is used to display the contents of the program memory, external or internal data memory. The M Move memory command is used to move a block of data from one area of the memory to another area. P- Programmer:

S-Single step command: The command is used to execute a program one instruction at a time. With each instruction executed, control is returned to the monitor. Thus this command is an extremely useful debugging tool. Provision has been made for single stepping with disassembly. S-Single step command with disassembly: Function: This command is used to single step a program with disassembly. The register content will not be displayed. Z-Disassemble: Disassembly is an extremely useful feature, often employed during debugging. Function: A disassemble converts machine language codes in to assembly language mnemonics, making it easy for user to understand the/verify the program.

ARITHMATIC OPERATIONS AIM: By using 8051 microcontroller

a) To perform addition of two numbers b) To perform subtraction of two numbers c) To perform multiplication of two numbers d) To perform division of two numbers

APPARATUS: 1. ESA-51 microcontroller kit 2. Power supply 3. Key board THEORY: The 8051 is an 8-bit Microcontroller designed by Intel. It was optimized for 8-bit mathematics and single bit Boolean operations. Microcontroller consists of Cutworm kinds of memory sections I/O ports, special function registers and control logic needed foe a variety of peripheral functions. These elements communicate through an 8-bit data bus which runs through out the chip referred to as internal data bus. This bus if buffered to the outside world through an I/O port when memory or I/O expansion is desired. ADDITION

Memory address

Op codes labels Mnemonics

Operands

Comments

8000 8003 8004 8006 8007 8008 800A 800B 800C

90,90,00 E0 E5,0B A3 A0 25,0B A3 F0 02,00,00

MOV MOVX MOV INC MOVX ADD INC MOVX LJMP

DPTR,#9000H A,@DPTR B,A DPTR A,@DPTR A,B DPTR @DPTR,A 0

Keep data in 9000h and 9001h;data memory Perform addition operation Store the result in 9002h and 9003h of data memory.

INPUT: 9000- OUTPUT: 9002- 9001- SUBTRACTION

Memory address

Op codes labels Mnemonics

Operands

Comments

8000 8003 8004 8006 8007 8008 800A 800B 800C

90,90,00 E0 E5,0B A3 A0 95,0B A3 F0 02,00,00

MOV MOVX MOV INC MOVX SUBB INC MOVX LJMP

DPTR,#9000H A,@DPTR B,A DPTR A,@DPTR A,B DPTR @DPTR,A 0

Keep data in 9000h and 9001h;data memory Perform subtraction operation Store the result in 9002h and 9003h of data memory.

INPUT: 9000- OUT PUT: 9001-

MULTIPLICATION Memory address

Op codes labels Mnemonics

Operands

Comments

8000 8003 8004 8006 8009 800A 800B 800E 800F 8010 8012 8013

90,90,01 E0 F5,F0 90,90,00 E0 A4 90,90,02 F0 A3 E6,F0 F0 02,00,00

MOV MOVX MOV MOV MOVX MUL MOV MOVX INC MOV MOVX LJMP

DPTR,#90001H A,@DPTR 0F0H,A DPTR,#9000H A,@DPTR AB DPTR,#9002H @DPTR,A DPTR A,OFOH @DPTR,A 0

Keep data in 9000h and 9001h;data memory Perform multiplication operation Store the result in 9002h and 9003h of data memory.

INPUT: 9000- OUTPUT: 9002- 9001- DIVISION

Memory address

Op codes labels Mnemonics

Operands

Comments

8000 8003 8004 8006 8008 8009 800A 800D 800E 800F 8011 8012

90,90,01 E0 F5,F0 16,82 E0 84 90,90,02 F0 A3 E6,F0 F0 02,00,00

MOV . MOVX MOV DEC MOVX DIV MOV MOVX INC MOV MOVX LJMP

DPTR,#90001H A,@DPTR 0F0H,A 82H A,@DPTR AB DPTR,#9002H @DPTR,A DPTR A,OFOH @DPTR,A 0

Keep data in 9000h and 9001h;data memory Perform division operation Store the result in 9002h and 9003h of data memory.

INPUT: 9000- OUTPUT: 9002- 9001- RESULT: Hence arithmetic operations like addition, subtraction, multiplication and

division are performed on 8051 Microcontroller.

TIMER IN DIFFERENT MODES AIM: To generate a square wave with frequency using Timer 0 and Interrupts APPARATUS:

1. Microcontroller kit 2. Cathode ray oscilloscope 3. Keyboard 4. CRO probes

THEORY: 8051 has two 8-bit register A and B, which can be used to store operands, as allowed by the instruction set. 8051 has a family of special function registers called a special function registers including A and B registers. There is total number of 21-bit addressable 8-bit registers. The registers TH0-TL0 from 16-bit counter or timer registers, with H indicating the upper byte and L indicating the lower byte of 16-bit timer registers. TMOD is ca be used for programming the modes of Times/Counters .TCON is called Timer/Counter control register. Some of the bits of this registers are used to turn the Timers on or off. This registers are also contains interrupt control flags for external interrupts INT1 or INT0. MAIN PROGRAM:

Memory address

Op codes

labels Mnemonics

Operands

Comments

8000 8003 8004 8006 8007 8008

75,89,01 75,8C,F0 75,8A,FF 11,20 80,FE 53,41,20

MOV MOV MOV ACALL CPL SJMP

TMOD 89,#01 TL1 8A,#0F0 TH1 8C,#0FF 8020 95 8003

Initialize timer 0 In mode 1,16-bit count reg.mode Introduce delay Keep complimenting port 1,5-bit To get square wave

DELAY PROGRAM: Memory address

Op codes labels Mnemonics

Operands

Comments

8020 800 8004 8006 8007

D2,8C C2,8C C2, 8D 22

SETB JNB CLR CLR RET

8C 8D,8022 8C 8D

Start the timer Wait for delay time Reset timer Reset timer over flow flag

MAIN PROGRAM:

Memory address

Op codes labels Mnemonics

Operands

Comments

8000 800 8004 8006 8007

75,89,02 75,A8,82 75,8C,F0 D2,8C 80,0B

MOV MOV MOV SETB SJMP

89,#02 0A8,#82 8C,#0F0 8C 800B

Initialize timer 0 in mode 2, Declare TF 0 as an interrupt Load timer count reg.TL1 Start the timer Keep monitoring the interrupt

INTERRUPT SERVICE ROUTINE:

Memory address

Op codes labels Mnemonics

Operands

Comments

FFF1 FFF2

B2,95 32

CPL RETI

95 Generate a square wave on interrupt basis

OBSERVATIONS: Time period calculations for Timer0 mode1 16-bit counter =FOFFH Number of clock cycles = FFFF – FOFF=F00H Clock period =11.095 µSec/12=0.925µSec Delay= Clock period* Number of clock cycles=0.925µSec* F00H=3.78msec. Therefore ON time=3.78msec OFF time=3.78msec Time period=ON time OFF time= 7.56msec Frequency=1/Time period=1/7.56msec=132Hz Time period calculations for Timer0 mode2 16-bit counter =FFH Number of clock cycles = FF – FO=0FH Clock period =11.095 µSec/12=0.925µSec Delay= Clock period* Number of clock cycles=0.925µSec* 0F=13.875µSec. Therefore ON time=13.875µSec. OFF time=13.875µSec. Time period=ON time OFF time= 27.75 µSec Frequency=1/Time period=1/27.75 µSec =36.04 KHz. RESULT: Hence square wave in Timer0 mode1 with a frequency 132Hz and in timer0 mode2 with a frequency 36.04 KHz was generated.