838 ieee transactions on components, … · 838 ieee transactions on components, packaging and...

838 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 6, JUNE 2017

Embedded Trench Redistribution Layers at 2–5 µmWidth and Space by Excimer Laser Ablation and

Surface Planer Processes for 20–40 µmI/O Pitch Interposers

Yuya Suzuki, Habib Hichri, Frank Wei, Venky Sundaram, and Rao Tummala, Fellow, IEEE

Abstract— This paper reports on one of the first demonstra-tions of the formation and metallization of 2–5-µm lines andspaces by an embedded trench method in two dry-film polymerdielectrics, Ajinomoto build-up film and preimidized polyimide,without using chemical mechanical planarization. The trenchesand vias in 8–15-µm-thick dry-film dielectrics were formed by308-nm excimer laser ablation, followed by the metallization ofthe trenches and vias by copper electrodeposition. A low-costplanarization process was used to remove the copper overburdenwith a surface planer tool. Using an optimized set of materialsand processes, multilayer redistribution layers with 2–5 µmtrenches and vias were successfully demonstrated. Althoughthin film processes on silicon wafers have been able to achieve40-µm I/O pitch for interposers, the materials and processesintegrated in this paper are scalable to large panel fabrication atmuch higher throughput, for interposers and high-density fan-out packaging at lower cost and higher performance than siliconinterposers.

Index Terms— Embedded trench, excimer laser, fan-out,interposer, microvia, panel scalable, polymer dielectric,redistribution layer (RDL), surface planar.

I. INTRODUCTION

INCREASING component and I/O density in electronicsystems have driven the need for higher functional-

ity and integration density at the package level. As thedemand for high-density packages has increased, redistributionlayer (RDL) wiring technologies have evolved from subtractiveetching processes to semiadditive processes (SAP). Organicsubstrates with SAP RDL have been demonstrated down to5-µm line and space recently [1]–[3]. However, SAP methodsface challenges in scaling below 5 µm, primarily limited by theside etching of the copper lines during seed layer removal, andpoor adhesion of ultrafine lines on smooth dielectric surfaces.Demonstration of ultrasmall line formation down to 2 µm withSAP has been reported by several research groups [4], [5].However, these processes utilized liquid dielectrics and

Manuscript received December 1, 2016; revised February 14, 2017; acceptedFebruary 24, 2017. Date of publication March 21, 2017; date of currentversion May 31, 2017. Recommended for publication by Associate EditorJ. J. Pan upon evaluation of reviewers’ comments.

Y. Suzuki, V. Sundaram, and R. Tummala are with the 3-D PackagingResearch Center, Georgia Institute of Technology, Atlanta, GA 30332 USA(e-mail: [email protected]; [email protected]).

H. Hichri is with Suss Microtec, Corona, CA 92880 USA.F. Wei is with Disco Corporation, Tokyo 143-8580, Japan.Color versions of one or more of the figures in this paper are available

online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCPMT.2017.2676023

chemical mechanical planarization (CMP) processes, whichlimits their application to panel-scale fabrication. As an alter-native wiring process, embedded trench technology has beenintensively researched and developed. One of the early exam-ples is Via2 technology developed by Amkor, Atotech, andUnimicron [6], [7]. It emulates the dual-damascene processschemes used in wafer back end of line (BEOL) and replacesSiO2 dielectrics and reactive ion etching etching with polymerdielectrics and excimer laser ablation patterning. The advan-tages of such laser embedded trench approaches compared toSAP are: 1) higher aspect ratio line capability; 2) eliminationof the seed layer removal process; 3) ability to pattern lines andmicrovias at the same time; 4) reduced number of process stepsby eliminating photograph lithography processes; and 5) viapattern integrity. One of the main challenges of the embeddedtrench approach is the removal of the copper overburden afterthe copper filling of trenches and vias by electrolytic plating.In prior work on Via2 technology, CMP processes adoptedfrom wafer BEOL were used to remove the copper overburden,which limits the process application for panels and increasesthe process cost. Furthermore, the resolution of the trenchwidth by the excimer laser has been limited in the traditionaldielectric polymers. A recent study by Unimicron reported thesuccessful trench formation down to 3-µm lines and spaces ina build-up dielectric material with small-sized filler [8]. Thepresence of large filler particles in the dielectric polymer haslimited the formation of small trenches or microvias by laserprocesses [9]–[11].

In this paper, 2–5-µm copper embedded trenches in polymerdielectric layers were demonstrated by combining new mate-rials and optimized processes that are scalable to large panelsand have the potential for higher throughput and reducedmanufacturing costs. Epoxy-based dry-film Ajinomoto build-up film (ABF) by Ajinomoto and preimidized polyimide basedry film by Fujifilm were selected as the primary dielectrics inthis paper because of their superior chemical and mechanicalstability as well as processability. The effect of the filler size onthe trench profile was investigated by analyzing the excimerlaser trench formation process in ABF films with differentfiller sizes and a polyimide material without fillers. Afterdown-selecting the suitable materials, 2-µm small trenches and20-µm pitch microvias were successfully formed by excimerlaser ablation. After the laser process, metallization was con-ducted with seed-layer deposition and copper electroplating

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SUZUKI et al.: EMBEDDED TRENCH RDL 839

Fig. 1. Process schematic of the laser embedded trench approach.

processes to fill the trenches and vias simultaneously. Theexcess copper overburden was removed by a surface planariza-tion tool (DISCO Japan) as a higher throughput alternative toCMP [12]. Fig. 1 summarizes the process schematic of theembedded trench approach in this paper:

1) lamination of polymer dry film on the core substrate;2) formation of trenches and vias by excimer laser ablation;3) seed deposition by Cu electroless (Eless) plating or

Ti-Cu sputter processes;4) electrolytic Cu plating to fill trenches and vias;5) planarization to remove copper overburden on the

surface.

This paper is organized as follows. Section II describes thedry-film polymer materials selections for this paper. Section IIIdiscusses the formation of trenches and vias structured withexcimer laser processes and the effect of filler size in thedielectric polymer. Section IV explains the metallizationprocesses of the trench and via structures, including platingand surface planarization processes. Section V describes theinitial demonstration of the multi-RDL layer stack-up withreliability under thermal shock testing.

II. DRY-FILM POLYMER DIELECTRICS

Selection of proper materials is critical for achieving ultra-small embedded wiring structures. Three different dry-filmmaterials, ABF GX92, ABF GY50, and preimidized polyimidewere examined in this research.

ABF is a compound material of epoxy polymer matrixesand inorganic fillers, being widely used in the packagingindustry [13]. The chemical and electrical properties of epoxypolymer can be easily tailored by changing the chemicalcomponents. For better mechanical and thermo-mechanicalproperties, inorganic fillers (such as silica) are mixed withan epoxy matrix to make compounds. In this research, a tra-ditional epoxy polymer composite material ABF GX92 and anew type of material ABF GY50 with smaller sized silica filler

particles were studied to see the impact of different filler sizeon small trench formation. Although the two materials havedifferent sized filler particles, their mechanical and thermo-mechanical properties are comparable.

Polyimide has been also used for variety of packagingapplications such as wafer-level packaging and flexible sub-strates [14], [15]. Polyimide has strong absorption of UV lightespecially from 200 to 450 nm, which makes it superior in UVlaser processing [16]. Additionally, due to lower coefficient ofthermal expansion of polyimide compared to other polymers,the material can be used without filler particles, which hasa large advantage in making small feature by excimer laserprocessing [17]. Polyimide is well known for its outstand-ing chemical, mechanical, and thermomechanical propertiesbecause of the strong imide bonding and molecular packing.On the other hand, due to this strong molecular interaction,typical polyimide materials have very high melting point andare nonsoluble in most solvents, which makes it challengingto process the materials. Therefore, for the industrial useof polyimide materials, precursor polymers are molded orlaminated first, then exposed to a thermal baking process tocomplete polyimide formation. For a dry film application,the thermal baking step has disadvantages such as requirementof high temperature (>300 °C) and large shrinkage during thebaking. To address this issue, a new preimidized polyimidematerial by Fujifilm was recently developed. This material canbe manufactured as dry film type, processed by laminationstep, and then cured at 200 °C–250 °C [18]. In this research,dry-film-type preimidized polyimide material was used for adielectric layer.

ABF and polyimide dry film materials were laminatedon FR-4 or glass core materials. ABF films (15-µm-thickGX92 and GY50) were laminated with vacuum laminatorat 120 °C, then oven cured at 180 °C. Polyimide film(8 µm thick) was laminated and cured with hot press at 250 °C.These materials showed high material flow during the lamina-tion process to achieve flat surface.

III. TRENCH AND VIA FORMATION BY EXCIMER LASER

For making trenches and vias in polymer dielectric layers,an excimer laser system was used. One of the advantages ofexcimer lasers is the efficient ablation of polymer materials.Photon energy of excimer lasers is typically more than 4 eV,which is at the same level as the molecular bonding energy inpolymer materials (C-H, C-C, C-O etc.). Additionally, polymerdielectrics have strong absorption of ultraviolet light, operatingwavelengths of the excimer lasers, which induces efficientphoton penetration into the polymer materials. As a result,the absorbed photons of the excimer laser initiate photograph-induced decomposition of the polymers from solid phase togas phase directly [19]. The energy discharged during thetransition converts to the velocity of the decomposed frag-ments, which leads to the explosive ejection of the fragments,called ablation [20]. The efficient ablation leads to the cleanetching of polymer without heat damage. Another advantageof the excimer laser is the capability of mask projection laserprocessing due to large beam size [21], [22], which enablesthe formation of ultrasmall features such as trenches and


Fig. 2. Example of beam delivery system schematic for an excimer laserablation tool.

vias, defined by mask opening size. Since the location oftrenches and vias are defined by the mask, high-positionalaccuracy is guaranteed, enabling pad-less microvia formationand accurate layer-to-layer registration. Furthermore, capabil-ity of mask projection results in high throughput processingby step-and-repeat platform and scalability to large panelproduction [23]. Excimer lasers are available in different laserwavelengths based on the type of active gases in the tools;157 nm (F2), 193 nm (ArF), 248 nm (KrF), 308 nm (XeCl),and 351 nm (XeF). UV light below 250-nm wavelength hasstrong absorption by glass materials, therefore F2, ArF, andKrF excimer lasers are useful for glass processing [24]. How-ever, these lasers cause inherent damages to the optical systemmade of glass materials after long time usage. Additionally,strong attenuation of laser occurs in the air due to absorptionby oxygen at the ultrashort wavelength, therefore optical pathsshould be purged with nitrogen or argon, or vacuumed, whichmakes the system more complicated and expensive. In thisresearch, a 308-nm XeCl laser was selected because of theinertness in the air and much less damage to the opticswhile having high-processing capability of polymer materi-als. Fig. 2 shows the experimental scheme of excimer laserablation of the samples with mask projection. The excimerlaser system used in this paper was ELP300 Gen2, equippedwith Coherent LPXPro 305 (XeCl) and projection lens of 0.1NA.

Using the mask projection laser process, trenches wereformed in the samples. The depth of the ablated trench canbe controlled by changing the number of laser pulses. Depthsof trenches were measured for the various numbers of laserpulses (5, 7, 8, 9 shots) at 800 mJ/cm2 and plotted in Fig. 3.It was confirmed that the ablation depth and number of laserpulses had a linear relationship.

To investigate the effect of filler size in polymer dielectricson trench size and profile, samples with different ABF films,GX92 and GY50, were prepared. GY50 has smaller fillerparticles compared to GX92. A sample with polyimide, whichdoes not include filler particles, was also prepared. Trencheswith 3–4 µm depth were formed in these dielectrics byexcimer laser under the same process conditions (six pulsesof laser ablation at 800 mJ/cm2) using a mask with 2–4-µm

Fig. 3. Ablated depth of trench with different number of laser pulses.

line and space structures. After titanium or copper thinlayer (<0.1 µm) deposition with sputtering to minimize thefilm transparency, the profiles of the trenches were measuredwith a laser confocal microscope. Top views and profiles ofthe trenches are shown in Fig. 4. Profiles of the trenches weremeasured at the red broken line in the top view pictures.Trench profile in GX92 was much rougher than that inGY50 or polyimide. Additionally, trench walls in GX92 werecollapsed due to the side erosion. Line and space trenchstructures down to 3 µm in GY50 and down to 2 µm inpolyimide were successfully formed.

For more detailed analysis, SEM micrographs (5000×)of the 4-µm trenches in the same samples were preparedas shown in Fig. 5. As seen in the SEM images, mostfiller particles with diameter of around 1–2 µm were foundin GX92, whereas filler particles in GY50 were much smaller,less than 1/10 of the particle size of fillers in GX92. The trenchside wall roughness was much higher in GX92, and this canbe explained on the basis of the ejection of large filler particlesfrom the side walls since the magnitude of the roughness inthe trench side walls was approximately equal to the size offiller particles. The trench side wall roughness in GY50 wassignificantly lower, due to the smaller size filler particles, andthe side wall roughness was roughly equivalent to the fillerparticle size. The trench side walls in the polyimide materialhad the lowest surface roughness, which is consistent withthe fact that the polyimide dielectric did not include any fillerparticles.

Due to the rough surface in GX92 samples, large sideerosion of the trench was observed and trench width wasextended by more than 2 µm on each side. As a result,trenches below 5-µm line and space could not be yieldedin GX92. In contrast, side erosion of trenches in GY50 wasmuch smaller, below 0.5 µm on each side, which resultedin successful formation of trenches down to 3-µm line andspace (6-µm pitch). In the case of polyimide, 2-µm lineand space structures were successfully demonstrated due tominimized side erosion.

After the formation of trenches, microvias were drilled alsoby excimer laser. First, trenches with 20-µm width and 5-µmdepth were created in 15-µm-thick GY50 with nine pulsesof mask projection excimer laser ablation. Thereafter, usinga different mask, 10-µm-deep microvia with 8 µm diameterwere formed by 20 pulses of laser ablation. Top view and


Fig. 4. Top view (top) and line profile (bottom) of 2–4-µm line and spacetrenches in (a) GX92, (b) GY50, and (c) polyimide. Red broken lines indicatethe traces of profile scanning for each sample.

profile of the structure are shown in Fig. 6. No damage inthe bottom copper pad was observed. Side wall angle of amicrovia were measured as 75°.

IV. METALLIZATION OF TRENCH AND VIA

Before the metallization step, cleaning processes wereapplied to the samples to remove residual debris sitting on thesurface during the laser process. Chemical desmear process

Fig. 5. SEM images of 4-µm line and space trenches in (a) GX92,(b) GY50, and (c) polyimide.

was used for ABF samples, and acid cleaning process wasused for polyimide samples. Chemical desmear processesincluded immersion of samples in three different chemicalssequentially: 1) swelling at 60 °C for 10 min; 2) permanganateetching at 77 °C for 10 min; and 3) neutralization at 50 °Cfor 5 min. Metallization fill processes of the trenches andvias were carried out with metal seed deposition, followed byelectrolytic plating. For seed layer deposition, Eless Cu platingwas used for ABF samples to form 0.2 µm thick Cu seedlayer. For polyimide samples, Ti-Cu sputtering seed (0.03 µmTi and 0.1 µm Cu) was deposited. After the seed depositionprocesses, trenches and vias were filled with copper by elec-trolytic plating. To achieve effective filling in the trenches andvias, right selection of plating chemistry and electrolyte flowis very critical, and two different configurations of platingprocesses were examined in this research. One configurationused Cupracid TP by Atotech and nozzles facing parallel to thesamples (process tank A), while the other configuration usedInpro THF by Atotech and nozzles facing perpendicular to


Fig. 6. Top view and profile of the ablated trench and microvia in GY50.The profile was measured at the red line in the top view.

Fig. 7. Trench filling by different electrolytic plating processes. (I) Beforeplating. (A) After 40 min plating at 10 A with tank A. (B) After 40 minplating at 10 A with tank B.

the samples (process tank B). Nozzles with parallel directioncreate a laminar flow on the surface, whereas one withperpendicular direction creates turbulence. The samples hadtrenches with 20-µm width, 60-µm length, and 5-µm depth.After 40 min of electrolytic copper plating at 10 A in eachprocess, profiles of the plated trenches were observed with anoptical profiler (Fig. 7), and thickness of copper on the samplesurface was measured with an electrical thickness gauge. Fromtank A, plated copper thickness on the surface was 5 µm, andthe depth of the dimple was 3.2 µm. From tank B, copperthickness on the surface was 6 µm, and the depth of the dimple

Fig. 8. Illustration of Cu overburden removal by a surface planarizationprocess.

was 0.2 µm. This result indicates the process with tank A wascloser to conformal plating, whereas tank B process was moretrench filling plating. Plating with tank B has an advantagein effective copper filling in trenches without depositing thickcopper on top of the surface.

After filling of the trenches and vias, copper overburdenon the surface needs to be removed for process completion.Copper etching is the simplest method, however, control ofthe etching thickness is extremely challenging. Given the as-plated complex surface profiles, wet etching process posesa high-risk of over-etching in the trench. In this research,DISCO’s surface planer process equipment was used for theplanarization overburden removal step because of lower CoOand scalability to panel-base manufacturing due to its simplic-ities in the equipment kinematics. The surface planer processcan effectively remove ductile materials such as metals and/orpolymers from the surfaces of substrates. The process pointconsists of a single bit made of diamond, which is mounted ona spindle rotating at high speed at a fixed height. The substrateis fixed on a flat chuck table that is creep-fed under the rotatingbit that is barely contacting the surface (Fig. 8). The surface ofthe chuck table is in precise parallelism with the plane definedby the rotation of the processing bit. As the tool shaves thesubstrate, the unevenness of the ductile material on the surfaceis carved off, leaving an extremely flat surface with excellenttotal thickness variation (TTV) control across the substrate.In case of this paper, the copper overburden was removed inthis fashion.

Thickness variations under the top layers inside the samplescan affect the precise cutting of the plated surfaces. To illus-trate the impact of TTV on planarization, two samples withdifferent core substrates were prepared. First, 15-µm-thickABF GX92 films were laminated on both 6-in square FR-4(700 µm thick) and glass (500 µm thick) panels.TTV of 6” square FR-4 panel was 4 µm, while that ofglass panel was 1 µm. In the laminated ABF layers, trencheswith 3-µm depth were formed by excimer laser ablation.Subsequently, trenches were filled with copper by Eless platingand electrolytic plating processes. The surface planer tool wasused to remove overburden copper from the samples, and theinspection results were compared in Fig. 9. In the sample withFR-4 core, residual copper can still be observed in the centerdevice area, while adjacent die areas were already showing


Fig. 9. Top view of the 46-in panels with FR-4 core (left), and glasscore (right) after trench planarization. Circles with dashed line show residualcopper, and circles with solid line show overcut areas.

Fig. 10. Magnified images of the four corner coupons in the glass coresample.

signs of over-cutting. This is because of the unevenness ofthe FR-4 core. In contrast, uniform cutting was observedin the sample with glass core, which has even TTV. Someresidual copper was seen at the edge of the glass sample,which is due to the edge setups from the plating process.Magnified images of the four corner coupons in the glasscore sample are displayed in Fig. 10. This result indicateslow TTV core, or coplanar-base layer treatment, is critical forfine-line RDL formations.

To demonstrate small trench structures, samples with poly-mer dielectrics on glass panels were prepared, and embeddedtrench processes were applied. Fig. 11 shows the top view ofthe small trenches made by the processes. Trench structureswith 5-µm width on GX92, 3 µm on GY50, and 2 µm onpolyimide materials were successfully achieved.

Fig. 11. Fine pitch trenches formed in GX92 (top), GY50 (middle), andpolyimide (bottom).

Fig. 12. Top view (left) and cross-sectional view (right) of the daisy-chainstructure with 20 µm via pitch by embedded trace processes.

V. MULTILAYER RDL DEMONSTRATION

A sample with a multilayer RDL structure was also fab-ricated by repeating the process steps. Initial demonstrationwas conducted using GX92 polymer dielectric, excimer laser,and surface planarization processes. After the first embeddedcopper layer formation on GX92, second metal layer wasfabricated from lamination of 15-µm-thick GX92 film on topof the first layer. Thereafter, both trenches and vias were


Fig. 13. Cross-sectional view of the multilayer RDL of different locationsin one sample.

Fig. 14. Daisy-chain resistance (100 vias) of different via pitches underliquid-to-liquid thermal shock test (1 min at −55 °C, 1 min at 125 °C).

formed in the top dielectric layer by two steps of laser ablation.Then, Eless copper plating and electrolytic copper platingwere used for filling in the trenches and vias, followed bysurface planarization to complete multilayer fabrication. Topview and cross-sectional view of the fabricated daisy-chainstructure with 20-µm pitch microvias are shown in Fig. 12.Cross-sectional pictures from different locations in a sam-ple with lower magnification are shown in Fig. 13. Highlyplanarized metal structures at large scale can be confirmedfrom the pictures. Via diameter was 8 µm, and pad widthwas 15 µm. Demonstration of multilayer RDL structurewith smaller design rule using GY50 is currently underdevelopment.

Daisy-chain coupons at three different via pitches(20, 30, and 40 µm) were fabricated, and an initial reliabilitytest was performed. Resistances of the daisy-chain couponswith 100 of microvias were measured before the test and after

100, 500, and 1000 cycles of liquid-to-liquid thermal shocktest between −55 °C and 125 °C. The resistance of the couponwith 20-µm pitch was higher than those of 30- and 40-µmpitch because the wiring widths in 20-µm pitch design werenarrower; 15 µm wide for 20-µm pitch design and 20 µmwide for 30- and 40-µm pitch design. No failure (failurecriteria: 10% increase in resistance) was observed for all ofthe coupons (Fig. 14) up to 1000 cycles.

VI. CONCLUSION

High-density RDL with 2–5-µm trenches was demonstratedusing advanced dry-film dielectrics with excimer laser-basedembedded trench approach. The approach comprises excimerlaser ablation, copper seed layer formation and electrodeposi-tion, and surface planarization process steps. The effect offiller particles in the polymer dielectric materials on fine-pitch trench formation was investigated. It was concluded thatdielectrics with smaller fillers have an advantage in fine-pitchtrench formation. By down-selecting the suitable materials,small RDL copper transmission lines down to 2 µm weresuccessfully demonstrated. The embedded trench approachalso integrates small microvia formation for layer-to-layerinterconnection, and multilayer RDL structures with 20 µmvia pitch was successfully fabricated. The materials andRDL formation processes discussed in this paper can be scaledto large panels, providing a path for high-volume manufactur-ing of high-density interposers and fan-out packages at lowercost than wafer-based silicon interposers.

ACKNOWLEDGMENT

The authors would like to thank Ajinomoto, Fujifilm, andAtotech for providing ABF materials, polyimide materials, andplating process setup, respectively. They would also like tothank K. S. Lee for his support in SEM pictures.

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Yuya Suzuki received the B.S. and M.S. degreesin applied chemistry from the University of Tokyo,Tokyo, Japan, in 2005 and 2007, respectively. He iscurrently pursuing the Ph.D. degree with the Mate-rials Science and Engineering Department, GeorgiaInstitute of Technology, Atlanta, GA, USA.

In 2007, he joined Zeon Corporation, Tokyo, as aResearcher. He is currently a Research Engineer withthe 3-D Packaging Research Center, Georgia Insti-tute of Technology. His current research interestsinclude thin dielectric materials and processing of

small microvia, polymer synthesis, polymer processing, and organic-inorganichybrid materials.

Habib Hichri received the B.S. degree from theNational School of Engineering of Gabes, Gabes,Tunisia, the M.B.A. degree from the State Universityof New York at Buffalo, Buffalo, NY, USA, and themaster’s and Ph.D. degrees in chemical engineeringfrom Claude Bernard University at Lyon, Lyon,France.

He spent about 12 years with the IBM Semi-conductors Research and Development Center, EastFishkill, NY, USA, where he was a Lead ProcessIntegration Engineer for microprocessor, games, and

communications chips. He was later promoted to a management position atIBM on process development in lithography and dry reactive ion etch in thefront-end-of-line area for microprocessor fabrication. In 2013, he joined SUSSMicroTec, Corona, CA, USA, as an Engineering Applications Director. Hehas authored over 25 publications and presentations, and holds over 40 U.S.patents.

Dr. Hichri is a Full Member of the IEEE CMPT Society.

Frank Wei received the B.S. degree in chemi-cal engineering from the University of California,Berkeley, CA, USA, and the Ph.D. degree in materi-als science and engineering from the MassachusettesInstitute of Technology, Cambridge, MA, USA.

He spent five years with the Research andDevelopment Department, Philips Lumileds Light-ing Company, San Jose, CA, USA, where he focusedon developing chip-scale package processes forhigh-brightness LED manufacturing. He is currentlythe Research and Development Manager of DISCO

Hi-Tec America, Inc., Santa Clara, CA, USA. He is on overseas assign-ment with the Operation-V Department, DISCO Corporation’s headquarterResearch and Development Center, Tokyo, Japan. He has authored morethan 20 publications, is actively involved with various professional societiesin the packaging field, and holds numerous processing-related patents. Hiscurrent research interests include customer-centric process development andintegration in the areas of die singulation, thinning, and polishing for advancedpackaging.

Venky Sundaram received the B.S. degree from IITBombay, Mumbai, India, and the M.S. and Ph.D.degrees in materials science and engineering fromthe Georgia Institute of Technology (Georgia Tech),Atlanta, GA, USA.

He is currently the Director of Research andIndustry Relations with the 3-D Systems PackagingResearch Center, Georgia Tech, the Program Direc-tor for the Low-Cost Glass Interposer industry con-sortium with more than 25 active global industrymembers, a globally recognized expert in packaging

technology, and a Co-Founder of Jacket Micro Devices, an RF/wireless startupacquired by AVX. He has authored more than 100 publications and holds morethan 15 patents. His current research interests include system-on-packagetechnology, 3-D packaging and integration, ultrahigh-density interposers,embedded components, and systems integration research.

Dr. Sundaram was a recipient of several best paper awards. He is theCo-Chairman of the IEEE CPMT Technical Committee on high-densitysubstrates and is on the Executive Council of IMAPS as the Director ofEducation Programs.

Rao Tummala (M’88–SM’90–F’93–LF’16)received the B.S. degree from the Indian Institute ofScience, Mumbai, India, and the Ph.D. degree fromthe University of Illinois at Urbana–Champaign,Champaign, IL, USA.

He is currently a Distinguished and EndowedChair Professor and the Founding Directorof NSF ERC with the Georgia Institute ofTechnology (Georgia Tech), Atlanta, GA, USA,pioneering Moore’s Law for System Integration. Hehas authored about 500 technical papers, the first

modern Microelectronics Packaging Handbook, the first undergraduatetextbook Fundamentals of Microsystems Packaging, the first bookintroducing the system-on-package technology, and holds 74 patents andinventions.

Prof. Tummala was an IBM Fellow, pioneering the first plasma displayand multichip electronics for mainframes and servers. He is currently amember of the National Academy of Engineering, Washington, DC, USA.He was the President of the IEEE-CPMT and the IMAPS Societies. In 2011,he received the Technovisionary Award from the Indian SemiconductorAssociation and the IEEE Field Award for contributions in electronicssystems integration, and cross-disciplinary education. He is a recipientof many industry, academic, and professional society awards, includingIndustry Week’s Award for improving U.S. competitiveness, the IEEE’sDavid Sarnoff, the IMAPS’ Dan Hughes, the Engineering Materials fromASM, and the Total Excellence in Manufacturing from SME, and is also arecipient of Distinguished Alumni Awards from the University of Illinois atUrbana–Champaign, the Indian Institute of Science, and Georgia Tech.

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