Pin description

COURSE CODE

: BECCEC502

COURSE NAME

: MICROPROCESSORS

LECTURE PERIODS PER WEEK : 05

TOTAL PERIODS PER WEEK

: 05

CREDITS

: 05UNIT -I : Architecture of Intel 8085

15 Periods

Architecture of 8085 Pin description and functions Instruction and Data flow Machine cycle -Timing diagram for opcode fetch cycle, memory, I/O Read and write cycles - Interrupt structure and its operation.

UNIT -II : Assembly programming with 8085

18 Periods

8085 addressing modes instruction set classification and format stack and subroutine assembly language programming.

UNIT - III : Intel 8086 Architecture and Programming

20 Periods

Intel 8086 architecture Pin description and function overview minimal & maximum mode- bus activities during read / write operation Interrupts structure and its operation. Instruction set addressing modes ALP comparative study of 286, 386,486 & Pentium processors - Memory Protection and Virtual Memory Concepts.

UNIT - IV : Peripheral interface ICs & Serial communication.

22 Periods

Address space partitioning memory and I/O interfacing PPI 8255- UART -8251- 8253 Timer 8259 A interrupt controller- 8237 programmable DMA 8279 keyboard and display interface controller, 8087 numeric processor.

Buses: I2C, USB, field Bus, CAN, Profi Bus, IEEE 488.

Text Books :

1. Krishna kant Microprocessor and microcontrollers, PHI, 2007.

2. Barry B. Brey The Intel Microprocessors: Architecture, Programming and Interfacing 4th ed., PHI, 2005.

3. Douglas V. Hall Microprocessors and Interfacing Programming and Hardware - 2/e - Tata McGraw Hill, 2003.

Suggested Readings:

1. Ramesh S. Gaonkar Microprocessor Architecture, Programming and Applications with the 8085 Penram International, 5th Ed, 2006.

2. A.P. Mathur Introduction to Microprocessors TMH, (3/e), 2006.

3. Walter A.Triebel, Avtar Singh, The 8088 & 8086 Microprocessor Programming, Interfacing, software, Hardware and applications,4th ed., Pearson, 2004.

1. Pin description 8085 A

AD0 - AD7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)

appear on the bus during the first clock cycle of a machine state. It then becomes the

data bus during the second and third clock cycles. 3 stated during Hold and Halt

modes.

A15 A8 (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0

address,3 stated during Hold and Halt modes.

ALE (Output)

Address Latch Enable: It goes high during the first clock cycle of every machine cycle to latch the lower order address from multiplexed address/Data bus. ALE is never 3stated.

SO, S1 (Output)

Data Bus Status. Encoded status of the bus cycle:

S1 S0Function

O O HALT

0 1 WRITE

1 0READ

1 1 FETCH

__

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

___

RD (Output 3state)

READ; indicates the selected memory or I/O device is to be read and that the Data

Bus is available for the data transfer.

___

WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory

or I/O location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt

modes.

CLK (Output)

Clock Output can be used as a clock i/p for other systems.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator. X1 can also be

an external clock input instead of a crystal. The input frequency is divided by 2 to

give the internal operating frequency.

________

RESET IN (Input)

Reset sets the Program Counter to zero and buses are tri stated and CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPU is being reset. It can be used to RESET other system.HOLD (Input) - DMAHOLD; indicates that another Master is requesting the use of the Address and Data

Buses.

HLDA (Output) - DMAHOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and

It is willing to serve the request.INTERRUPT PINS:

INTR (Input), TRAP (Input), RST 5.5 (Input), RST 6.5 (Input), RST 7.5 (Input)

INTA (Output).Vcc - +5 volt supply.

Vss - Ground.

2. Architecture Description:

Registers

The 8085 has six general-purpose registers to store 8-bit data; these are identified as

B,C,D,E,H, and L. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This

register is used to store 8-bit data and to perform arithmetic and logical operations.

The result of an operation is stored in the accumulator. The accumulator is also

identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according

to data conditions of the result in the accumulator and other registers. They are called

Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The microprocessor uses these flags to test data conditions.

D7D6D5D4D3D2D1D0

SZ-AC-P-CY

Stack Pointer (SP)

The stack pointer is also a 16-bit register. It points to a memory location in R/W memory, called the stack(TOP OF STACK). The beginning of the stack is defined by loading 16-bit address in the stack pointer.Internal Architecture

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location.Instruction Register (IR):It holds the opcode of the instruction which is being decoded & executed.

Temporary Register:

It is an 8-bit register associated with ALU. It holds the data during an arithmetic/logical operation. It is used by the MPU & not accessible to the programmer.

Program Status Word (PSW):

It is a combination of Flag register & Acc.

T-State:

One T-state or state is referred to as one clock cycle of system clock. It is also a part of operation performed in one clock cycle.

Machine cycle (MC):

The necessary steps carried out to perform a fetch, read or write operation constitute a machine cycle. A MC consists of several T-states.

Instruction Cycle:

An instruction is a command given to the computer to perform a specified operation on the given data. Program is a sequence of instructions to perform a task. Program & data are stored in memory. The CPU fetches one instruction at a time from memory & executes it.The necessary steps that a CPU carries out to fetch an instruction and necessary data from memory, and to execute it constitute an instruction cycle. An instruction cycle consists of a Fetch & Execute cycle. Fetch cycle (FC):

In fetch cycle, the CPU fetches the opcode from the memory. In the begining of fetch cycle the content of PC which is the address of memory location where the opcode is available, is sent to memory. The memory places the opcode on the data bus so as to transfer it to the CPU.

Execute cycle (EC):

The steps carried out to get data, if any, from the memory and to perform the operation specified by the instruction constitute execution cycle. The opcode fetched from memory goes to the data/address buffer and then to IR. From IR it goes to decoder circuitary which decodes the instruction. After the decoding the execution begins.

Time required for FC is a fixed slot of time but the time for EC depends on type of instruction to be executed. IC = FC + EC. An IC consists of several MC.Instruction flow:

The word length of a computer or processor is the number of bits it handles at a time. For a 8-bit processor it is of one byte. Two kinds of words, namely instruction word (opcode) and data word are processed during an instruction cycle. In the beginning of a fetch cycle the content of PC is transferred to a special register called Memory Address Register, MAR (Address buffer). The content of MAR is transferred to the memory through the address bus. Using some control signal MPU tells that it wants to read the content of memory. Then the memory sends the opcode to the MPU through the data bus. The opcode first comes in the Memory Data Register, MDR (Data buffer). The opcode is then placed in the Instruction register & decoded by the instruction decoder and it is executed. Finally, the content of PC is incremented.

Flow of Opcode

Data flow:For the execution of most instruction, data flow is required. The data word received from the memory or input device, flows to the processor through the data bus and is placed in the Acc or any general purpose register depending upon the instruction. After the execution the result is placed in memory or sent to an output device through data bus. When a data word is written into memory, it is also held in MDR (Data buffer) until the write operation is complete.

3. Addressing Modes:It is the way by which the operand is specified in the instruction.i. Immediate The operand is specified as a part of instruction itself.

ii. Direct The address location containing the operand is specified in the instruction

itself.

iii. Register Direct The register at which the operand is present is specified in the

(or) Register instruction.

iv. Register Indirect The address of the operand is specified by a register pair. In other words, register pair, whose contents is the address location of the

operand is specified in the instruction.

v. Implicit The operand is implicitly specified in the instruction itself (default operand).

Instruction set classificationi. Data Transfer (Copy) Operations

This group of instructions copy data from a location called a source to another

location called a destination, without modifying the contents of the source.

MOV Rd,Rs LDAX B/D LHLD Addr16LDA AddR16 LXI Rp/SPMOV R,8-bit STAX B/D SHLD Addr16STA Addr16 XCHG

ii. Arithmetic Operations : These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement.

Addition/ Subtraction - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator or subtracted from accumulator and the sum/difference is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of the register C). The instruction DAD is an exception; it adds 16-bit data directly in register pairs.

ADD R/M

ADC R/M

SUB R/M

SBB R/MADI 8-bit

ACI 8-bit

SUI 8-bit

SBI 8-bitDAD Rp/SP

DAAIncrement/Decrement - The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such

as BC) can be incremented or decrement by 1.

INR R/MDCR R/M

INX RpDCX Rp

iii. Logical Operations : These instructions perform various logical operations. Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator.

ANA R/MORA R/MXRA R/M

STC

ANI 8-bitORI 8-bit XRI 8-bit

CMCRotate- Each bit in the accumulator can be shifted either left or right to the next

Position. RLC(without carry)RAL (through carry bit)

RRC

RAR

Complement - The contents of the accumulator can be complemented. All 0s are

replaced by 1s and all 1s are replaced by 0s. CMA

Compare- Any 8-bit number, or the contents of a register, or a memory location can

be compared for equality, greater than, or less than, with the contents of the accumulator.

CMP R/M

CPI 8-bitiii. Branching Operations: This group of instructions alters the sequence of program execution either conditionally or unconditionally.

Jump - Conditional jumps are an important aspect of the decision-making process in

the programming. These instructions test for a certain conditions (e.g., Zero or Carry

flag) and alter the program sequence when the condition is met. In addition, the

instruction set includes an instruction called unconditional jump.

JNZ

JNC

JP

JPO

PCHL

JZ

JC

JM

JPE

JMP Addr16

Call, Return, and Restart - These instructions change the sequence of a program

either by calling a subroutine or returning from a subroutine. The conditional Call and

Return instructions also can test condition flags.

CNZ

CNC

CP

CPO

CALL Addr16

CZ

CC

CM

CPE

RNZ

RNC

RP

RPO

RET Addr16

RZ

RC

RM

RPE

iv. Machine Control & I/O Operations

These instructions control machine functions such as Stack, Halt, Interrupt, or do nothing.

IN Addr8

PUSH Rp/PSWXTHL

NOPOUT Addr8

POP Rp/PSWSPHL

HLTDIRIMRST n

RST 5.5TRAPEISIMRST 6.5RST 7.5Note: Addr16 16 bit memory location

Addr8 8 bit Port address

R A, B, C, D, E, F, H, L

Rp B, D, H

PSW ACC (MSB) & FLAGS (LSB)n 0 TO 7

M Memory pointed by HL pair.4. Stack:The stack in 8085 microprocessor can be described as a set of memory locations in R/W memory, specified by the programmer in the main program. These memory locations are used to store data bytes temporarily during the execution of the program. The beginning of stack can be defined in the program using the instruction LXI SP,16bit address which loads the SP with the 16-bit address specified in the instruction. The stack in 8085 microprocessor is a down growing stack which means, once the stack location is defined, storing of data bytes begins at the memory location one less than the address in SP register and it can grow till the lowest possible address location (0000H). The programmer can store & retrieve the contents of a register pair using PUSH & POP instructions.Subroutine:

A subroutine is a group of instructions written separately from the main program to perform a function that occurs repeatedly in the main program. the 8085 microprocessor has two instructions to implement subroutines: CALL (call a subroutine), and RET (return from subroutine). When a CALL instruction is executed, the microprocessor automatically stores the 16-bit address of the instruction next to CALL on the stack. Upon the execution of RET instruction, the contents of the top two locations of the stack are transferred to PC. In other words, CALL & RET instruction uses implicit PUSH & POP operations. 5. 8085 Interrupt Structure and Operation

8085 supports two types of interrupts: Hardware & Software.Hardware Interrupts: interrupt signals generated by peripheral device through some pins to interrupt the main program. 8085 has five hardware interrupts namely TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP highest priority, RST 7.5, RST 6.5, RST 5.5, INTR lowest priority. The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. The TRAP input is both edge and level sensitive.Software Interrupts: interrupt signals generated by the execution of an instruction.The RST n instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number n (0-7). These can be used as software instructions in a program to transfer program execution to one of the eight locations (nx8).Vectored Interrupts: when interrupt is active, the internal control circuit produces a CALL to a predetermined memory location.

INTR receives the address from external deviceMaskable interrupt: these interrupts can be enabled / disabled under program control. All interrupts except TARP are maskable.SIM : Masks the interrupts + sends serial data

RIM: copies status of interrupts into A + read serial data

Interrupt Structure of 8085InterruptPriorityMaskableVectoredTriggerVector Address

TRAP1(Highest)NOYESLevel & +VeEdge0x24

RST 7.52YESYES+VeEdge0x3C

RST 6.53YESYESHigh Level0x034

RST 5.54YESYESHigh Level0x02C

INTR5(Lowest)YESNOHigh Level-

INTR sequence of events:

8085 checks INTR during execution of each instruction.

If INTR, then 8085 completes current instruction and sends INTA if the interrupt is enabled. External logic places an instruction OPCODE on the data bus. In case of multi-byte instruction, additional INTA cycles are generated. 8085 saves PC and executes received instruction.If received instruction is RST:

8085 pushes PC into stack. Branches the program control to the vector address.

If received instruction is CALL:

8085 generates 2 additional interrupt acknowledge cycles. After receiving 16-bit address, 8085 pushes PC and branches to the received address.InstructionNo.of T-statesExecution countTotal T-state

LXI D10110

L1:DCX D6N6N

MOV A,D4N4N

ORA E4N4N

JNZ L110 or 7N-1 with 10

1 time with 710N-10

7

RET1010

CALCULATION OF DELAY & WRITING DELAY ROUTINE USING 8085

JNZ instruction will take 10T when it makes jump and 7T when condition fails.

Time = 24N-17 T-states.

Example:

Required time delay = 10ms.

With clk of 3MHZ, time for 1 T-state is 1/3x106 = 0.33s.

T-states required to get 10ms delay = 10ms / 0.33s

= 10x10-3 / 0.33x10-6

= 30303 = 765Fh.

From above equation,

30303 = 24N-17

24N = 30303 17

N = 30286 / 24

N = 1261.91 = 1262.

N = 04ED h.

Note: N is the Count to be loaded in DE-reg pair of above program to get the delay of

10ms..

Memory Adress Bus

Memory Data Bus

MAR

MDR

Program

Counter

Instruction Decoder

Control

Instruction Register

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