8616 over 30” of legacy backplane

PLX PCI Express over 30” of Legacy Backplane White Paper

Version 1.0

July 2008

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Copyright © 2008 by PLX Technology, Inc. All Rights Reserved – Version 1.0 July 23, 2008

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Summary This paper demonstrates the ability of PLX Gen2 switches to link and operate with over 30 inches of a legacy Communication space (Tyco) backplane at both 2.5 and 5Gbps. In the communications space, the ability to drive distance and the ability to operate without a common clock reference are important factors for these systems. Both these conditions are set up and demonstrated. Link operation was established with approximately 40 total inches of PCB, multiple Hm-Zd and SMA connectors including approximately 2 feet of coax.

Introduction Very often the question comes up, “how far can a PCI-Express operate along a backplane?” As to be expected, the answer to that question is - “It depends”. Still, as an indication of what is possible - enclosed is an example utilizing the Tyco HM-Zd Legacy backplane, familiar in many Telco design labs. Over the years, it has become a common test benchmark in telecommunications and gives a common reference point for discussion. As we have seen, PCI Express is gaining foothold as the control plane protocol of choice, even in Ethernet applications. As such, we demonstrate operation over this test standard. Note however, this backplane, is based on Nelco material, not FR4, and as such, is typically less lossy than a standard FR4 link.

Setup As shown below, the initial setup consists of two PLX 8616 RDKs, PCIe to SMA connector adaptor, two sets of coax cables going into and out of the backplane, and a pair of SMA to Hm-Zd connector cards to convert to connection from SMA to Hm-Zd. The link is operated asynchronously – no common reference - with separate, constant frequency time bases for each transceiver.

The Tyco backplane has populated slots at distances of 16 and 30 inches. Each Hm-Zd connector card has a trace distance of 3 inches. Distance from chip to RDK connector edge is ~ 5inches. Total PCB trace distance is 27 and 41 inches respectively. The length of each section of coax is ~ 18 inches.

Tyco PCB specification and Adapter card specifications are as follows;

• 200 mil thick, 14 layers, Nelco 4000

• Signal layers, 100 ohm differential impedance, 8 mil wide, ½ ounce copper

• Stripline construction with GND plane above and below

• Adapter cards, 93 mils thick, 100 ohms differential, 14 layer, Nelco 4000

• PCIe compliant based board (rev 1.1), 100 ohms differential, FR4

• PLX PEX 8616RDK, ~ 85 ohms differential, FR4

Note that the RDK configuration also employs two PCIe connectors which is atypical to this application. The additional discontinuities introduced by this connector can be significant.

PLX PCIe Gen 2 Signal over Legacy Backplane White Paper, Version 1.0 © 2008 PLX Technology, Inc. All rights reserved. 2

1 PCI Express Gen 1 Results

1.1 16 Inch Testing Using the native support features of PCI Express to automatically create a compliance test pattern, Gen1 testing was done using channel 0 of the RDK and of the backplane. PCISig software was used to verify electrical compliance for direct system interconnect.

Figure 1. Setup

With the backplane set at 16 inches, the PEX 8616 produced clean passing Gen 1 compliance pattern.

Figure 2. 16 inches Tyco – Non-Transition Eye


Figure 3. 16 Inches Tyco – Transition Eye

As can be seen from the above plots, and recorded from the PCI-SIG software logfile, Overall Systems Pass.

1.1.1 PCI-SIG Test

• Overall Sigtest Result: Pass!

• Max Peak to Peak Jitter: 60.891944 ps Max Peak to Peak Jitter Passes Sigtest Limits!

• Minimum Non Transition Eye Voltage: -0.2996 volts Minimum Non Transition Eye Voltage Passes Sigtest Limits!

• Maximum Non Transition Eye Voltage: 0.28 volts Maximum Non Transition Eye Voltage Passes Sigtest Limits!

• Data Rate (Gb/s): 2.50005

• Per Edge RMS Jitter (ps): 10.80234

• .…

For this ‘short link’, the quality of the transmitted signal stands out. With the low random jitter of the transmitter, what can be observed is the channel induced, channel dependent deterministic jitter caused by the link.


1.2 30 Inch Testing Below, plots from 30 inches of Tyco backplane are observed.

Figure 4. 30 inches Tyco – Non Transition Eye (Gen 1)

Note the increase in channel induced deterministic jitter.

Figure 5. 30 inches Tyco – Transition Eye (Gen1)

At 30 inches, the default specified PCIe emphasis setting of 3.5 dB is not enough to clear the receive eye mask. This is a reasonable expectation because the transition eye holds the highest frequency components of the signal. If the bandwidth of the channel were to be examined in the frequency domain, it would be seen that the extra distance equates to a lower overall channel bandwidth and higher frequency dependent losses. To counteract the channel, more signal de-emphasis can be employed to balance the disparity between high frequency and low frequency losses. Below is the re-measured eye diagram with the PEX8616 channel reset to 7dB de-emphasis.


Figure 6. 30 inches with 7dB de-emphasis (Gen 1)

Figure 7. 30 inches with 7dB de-emphasis (Gen 1)


2 Impact of Trace Length on the Signal As mentioned above, as trace distance increases, so too does signal loss, but just as critically, the line bandwidth decreases and signal rise times increase. As estimated in Table 1 below, changing from 16 to 30 inches, the channel bandwidth is reduced by ~ 30%. Below, two eye plots using the PCIe base reference clock as the scope trigger. The first plot is “16” inches of backplane. The second is “30” inches.

Figure 8. 16 Inch Eye Plot Gen 1 Tyco – (less final PCIe Connector)

Figure 9. 30 Inch Eye Plot Gen 1 Tyco – (less final PCIe Connector)

Not that the above plots do not include the effects of the final PCIe connector and as such, will add appreciably to the distortion shown above. Never the less, as can be gleaned from the above plots, the 30 inch trace induces a significant increase in signal rise time and inner eye opening. It is rise time degradation along with trace discontinuities (also creating ISI) that typically impair a long channel well


before losses reach minimum thresholds. In our final series of tests, we will actually slightly reduce the TX amplitude for additional linearity and testing of Gen2 link capabilities.

Using approximations to calculate line bandwidth, loss, and rise time, enclosed below are the values for the backplane (PCB material, no connectors) and measured losses on the system.

Table 1. Estimated vs. Measured Losses

As shown in Table 1 above, the decrease in channel bandwidth (increased rise time) grows with channel distance. When operating at Gen1 rates, data bit interval is 400ps. However, operating at Gen2 speed, one bit interval is 200ps. As such, increased rise time can extend beyond a single bit interval, further decreasing the ability to link.

Additionally, even with one PCIe connectors removed (so as to create the scope connection), the capacitive effects of the various discontinuities begin to emerge. Luckily, in most comms application, the usage of a PCIe connecter (and its lesser integrity) does not come in to play.

Below is a calculated comparison of FR4 with Nelco.

Table 2. Loss comparison FR4 and Tyco

As the trend in the above tables shows, the loss delta between materials is not so great at lower frequency, but the disparity grows as the frequency increases. Given the same design parameters, the Nelco material for which the Tyco is made has a higher channel bandwidth.


2.1 PCIe Gen 2 Rates Gen2 data rate halves the bit interval of operation. This offers a significant challenges to legacy backplanes. Below is an overlay of several eye plots at both distances using a higher speed Agilent Scope.

Figure 10. 16 Inch Ele Plot Gen 2 Tyco – (Less final PCIe Connector)

For the above plot, the estimated channel bandwidth is estimated to be ~ 3.6Ghz and as such, above the fundamental frequency of PCI Express Gen2 (2.5Ghz).

Figure 11. 30 Inch Eye Plot Gen 2 Tyco – (Less final PCIe Connector)


As can be seen from this eye plot, it is clear that the fundamental frequency of PCIe Gen 2 (2.5Ghz) has extended beyond the 30 inch channel bandwidth (estimated at ~ 1.9Ghz). The end result is noticeable frequency dependent attenuation of the signal. (In addition, as noted earlier, there is added reflectionary issues and loss induced by the final PCIe connector that is not accounted for in the above plots) It is the role of the passive equalizer within the chip to balance the amplitude differences between these frequency components, and as such minimize the voltage-to-phase jitter translation that occurs in the receiver.

2.2 But does it Link? Still, the fundamental question is, ‘can the system link?’ Using the above PLX VPK and

connected to the Tyco backplane, link operation was achieved at Gen1 at both 16 and 30 inches without Serdes adjustment. As can be seen in Figure1 no clocking is shared between devices. This actually increases system jitter due to the lack of noise correlation, but is typical of a comms application. Data recovery is based off the constant frequency clock of each subsystem (PC spread Spectrum Clocking turned off). No adjustment of the transmit level or emphasis was made. The 30 inch configuration was run for 12 hours then checked for system errors without fail.

At Gen2 speeds, linkup and error free operation was established at 16 inches of Tyco, ~6 inches of paddle card, two Hz-Md connectors, 4 SMA connectors, two PCIe connectors, 5 inches of FR4 and ~22inches of coax cable. To gain link and clean operation, it was necessary to actually reposition the transmitters on both sides of the line to a lower amplitude with higher pre-emphasis. This attests to the need for linearity and the hidden dangers of link discontinuities.

At 30 inches, the losses combined with connector discontinuities proved overly cumbersome for channel link up. An alternate PLX card was designed with direct SMA connectivity. PCIe Gen2 link-up was shown. Total signal path was 30inches Tyco, 2 Hm-Zd connectors, 4 SMA connectors, ~ 6 inches of paddle card and a total of ~ 5 inches of test card PCB (FR4).

Below is a picture of the SMA riser card and of the set up.

Figure 12. PLX Signal Integrity Riser Card


Figure 13. PLX PEX 8648 SI Riser Card with Tyco Backplane

Below is a scope capture of the signal launched into the channel. The signal was set for an additional 4 dB of de-emphasis above the Gen2 specification to compensate for the additional frequency dependent losses of the channel.


Figure 14. Signal Launched from SMA Riser

After the signal traverses the channel, below is what the compensated output looks like.

Figure 15. Eye Plot after 30 inches of Tyco

Comparing the signal before and after the channel, the loss is ~ -11.6dB (20Log(0.213/0.813). The SerDes was able to link and run error free.



3 Conclusion As can be demonstrated, the PLX 8600 series of switches are capable of Gen 2 link operation across an old telecom ‘standard’. can be seen from this demonstration, with reasonable design considerations PCI Express can be extended 30+ inches and beyond.

For test cards, layout files, design considerations, etc for which this demonstration was developed, contact your local PLX FAE representative at www.plxtech.com.

http://www.plxtech.com/

8616 over 30” of legacy backplane

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