Lecture 8

PipeliningTechnique in which multiple instructions are overlapped in execution

Non-pipelined Vs Pipelined performanceMIPS instruction execution involves the following stepsFetch instruction from memory Read registers while decoding the instructionExecute the operation or calculate an addressAccess an operand in data memoryWrite the result into a register

Non-pipelined Vs Pipelined performanceConsider the following

Non-pipelined Vs Pipelined PerformanceFor the non-pipelined operation

Non-pipelined Vs Pipelined PerformanceFor the pipelined operation

Pipeline HazardsSituations in pipelining when the next instruction cannot execute in the following clock cycle

Three types

Structural hazard

Data hazard (Pipe-line data hazard)

Control hazard (Branch hazard)

Structural HazardsA planned instruction cannot execute in the proper clock cycle because the hardware cant support the combination of instructions that are set to execute in the given clock cycle

Data HazardsA planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available

To solve this we use forwarding or bypassing technique

Forwarding - Retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory

Data Hazards

Data HazardsLoad-use data hazard A data hazard in which the data requested by a load instruction has not yet become available when it is requested

We need a pipeline stall to resolve this

Pipeline stall (Bubble) - A stall initiated to resolve a hazard

Data Hazards

Control HazardsA planned instruction cannot execute in the proper clock cycle because the instruction that was fetched is not the one that is needed; i.e., the flow of instruction addresses is not what the pipeline expected

Arises from the need to make a decision based on the results of one instruction while others are executing

Control HazardsWhen the branch is not taken

Control HazardsWhen the branch is to be taken

Control HazardsBranch prediction - A method of resolving a branch hazard by assuming a given outcome for the branch and proceeding from that assumption rather than waiting to ascertain the actual outcome

Dynamic branch prediction works by keeping a history for each branch as taken or untaken, and then using the recent past behavior to predict the future

Control HazardsDelayed branch is another solution

MIPS software will place an instruction immediately after the delayed branch instruction that is not affected by the branch

Pipelined datapath

Pipelined datapath

Pipelined datapath with pipeline registers

Stages of lw instruction

Stages of lw instruction

Stages of lw instruction

Stages of lw instruction

Stages of lw instruction

Stages of sw instruction

Stages of sw instruction

Stages of sw instruction

Stages of sw instruction

Stages of sw instruction

Corrected datapath for lw instruction

Pipelined Control

Data hazards & forwarding

Two pairs of hazard conditions

1a. EX/MEM.RegisterRd = ID/ EX.RegisterRs1b. EX/MEM.RegisterRd = ID/EX.RegisterRt2a. MEM/WB.RegisterRd = ID/EX.RegisterRs2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

Data hazards & forwarding

ALU and pipeline registers before adding forwarding

ALU and pipeline registers with forwarding

The control values for the forwarding multiplexors

Conditions for detecting hazards with control signalsEX hazard:

if (EX/MEM.RegWriteand (EX/MEM.RegisterRd 0)and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10

if (EX/MEM.RegWriteand (EX/MEM.RegisterRd 0)and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10

Conditions for detecting hazards with control signals.MEM hazard:

if (MEM/WB.RegWriteand (MEM/WB.RegisterRd 0)and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01

if (MEM/WB.RegWriteand (MEM/WB.RegisterRd 0)and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Data hazards & stalls

if (ID/EX.MemRead and((ID/EX.RegisterRt = IF/ID.RegisterRs) or(ID/EX.RegisterRt = IF/ID.RegisterRt)))stall the pipeline

Data hazards & stalls

Pipeline with Forwarding and Hazard Detection Unit

Branch hazards

Branch hazardsWhen a branch is taken we will discard or flush the instruction in IF, ID & EX stages by setting the control signals to 0Calculate the branch target address and make the branch decision at ID stage of the pipeline.Dynamic branch predictionDelayed branch

36 sub $10, $4, $840 beq $1, $3, 7 # PC-relative branch to 40 + 4 + 7 * 4 = 7244 and $12, $2, $548 or $13, $2, $652 add $14, $4, $256 slt $15, $6, $7. . .72 lw $4, 50($7)

Exceptions

40hex sub $11, $2, $444hex and $12, $2, $548hex or $13, $2, $64Chex add $1, $2, $150hex slt $15, $6, $754hex lw $16, 50($7)assume the instructions to be invoked on an exception begin like this:40000040hex sw $25, 1000($0)40000044hex sw $26, 1004($0)

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