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Code: 9D06106b

M.Tech - I Semester Regular and Supplementary Examinations, April/May 2012 DSP PROCESSORS AND ARCHITECTURE

Time: 3 hours Max Marks: 60 Answer any FIVE questions

All questions carry equal marks *****

*****

1 (a) Briefly explain different methods of the design of FIR filter with suitable example. How MATLAB is used in the design?

(b) The sequence [0 2 4 6 8] is interpolated using the interpolation filter sequence bk

=[0.5 1 0.5] and the interpolation factor is 2. Determine interpolated sequence.

2 (a) Briefly discuss about the floating point and block floating point formats. (b) Explain with suitable D/A errors in DSP implementation. 3 (a) How the shifters are useful in DSP? Explain the functionality of barrel shifter? (b) Explain in detail the different addressing modes required for the FFT algorithm

implementation. 4 (a) Briefly discuss about different interrupts available in DSP processor. (b) Explain the concept of pipelining with an example and discuss appropriate timing

diagram. 5 (a) Briefly discuss about the memory-mapped register and stack addressing modes of

TMS320C54XX processor. (b) Explain the pipeline operation in TMS 320C54XX processor with suitable example. 6 (a) Describe the implementation of basic FIR filter in IC54XX processor. Modify the

implementation for minimum number of multipliers. (b) Briefly describe about the implementation of PID controller algorithm in IC54XX

processor. 7 (a) Explain how bit-reversed index is generated in DSP processor for 8-point FFT

implementation. (b) Explain 8-point DIT-FFT with butterfly implementation having scaling factor =1/4. 8 (a) Explain the memory space organization of TMS 320C54XX processor. (b) Explain in detail the synchronous serial interface of IC54XX processor with CODEC

device.

(Common to DSCE, DECS and ECE)

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