a 100 mhz two-phase four-segment dc-dc converter with light load efficiency enhancement in...

$: A 100 MHz Two-Phase Four-Segment DC-DC Converter With Light Load Efficiency Enhancement in $0.18~\mu{\rm m}$ CMOS$
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 8, AUGUST 2013 2213

A 100 MHz Two-Phase Four-SegmentDC-DC Converter With Light Load Efficiency

Enhancement in CMOSHan Peng, Student Member, IEEE, David I. Anderson, and Mona Mostafa Hella, Member, IEEE

Abstract—This paper describes a high switching frequencyCMOS DC-DC converter employing phase shedding/segmenta-tion and resonant gate drivers to improve light load efficiency. Anovel output inductor network with positively coupled inductorsbetween segments and negatively coupled inductors betweenphases is adopted in two-phase four-segment interleaved topologyto improve effective inductance and reduce inductor currentripple. To limit the contribution of the gate driver to the totalconverter loss under light and medium loads, a new combinedhigh-side and low-side resonant type gate driver with partiallyshared inductor is presented. The DC-DC converter is imple-mented in six-metal CMOS technology with 5 V powerdevices and occupies a total area of 2.55 mm 3.0 mm. It converts4 V input to 1 to 3 V output with peak 1.78 A current under100 MHz switching frequency. The measured peak efficiency is77.4% at 5.95 W output power and the tracking mode bandwidthcan reach up to 8 MHz. With resonant gate drivers, 5% efficiencyimprovement can be reached at 1 V output. Furthermore, theconverter is able to maintain peak efficiency as the output currentvaries from 0.1 A to 1.86 A.

Index Terms—Coupled inductors, DC-DC converters, duty ratiocorrector, high switching frequency, hysteresis controller, multi-phase power converters, resonant gate drivers.

I. INTRODUCTION

T HE recent advances in the development of multifunctionSystem-On-Chip (SOC) designs for portable devices,

have increased the need for improved battery capacities andlifetimes while maintaining small footprints and sizes. Forexample, a typical mobile terminal as shown in Fig. 1, includesa display, an audio interface, digital and analog/RF circuitsas well as an RF power amplifier (PA). Each circuit block isoptimized and designed for maximum performance at differentsupply voltages varying from 3.6 V to 0.8 V, while typicalLithium ion battery voltage in a mobile terminal is 4.2–4.5 V

Manuscript received June 04, 2012; revised September 23, 2012; acceptedDecember 02, 2012. Date of publication February 01, 2013; date of current ver-sion July 24, 2013. This work was supported in part by the National Semicon-ductor for chip fabrication and packaging and in part by the NSF under GrantsEEC-0812056, CNS-0721612 and NYSTAR contract C090145. This paper wasrecommended by Associate Editor T.-J. Liang.H. Peng is with the GE Global Research, Niskayuna, NY 12309 USA (e-mail:

[email protected]).D. I. Anderson is with the Texas Instruments, Santa Clara, CA 95051 USA

(e-mail: [email protected]).M. M. Hella is with the Rensselaer Polytechnic Institute, Troy, NY 12180

USA (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2013.2239157

Fig. 1. Block diagram of a cellular handset with various required supplyvoltages.

[1]. Power supply modules are required to interface betweenthe battery and the different functional blocks. To reduce thesize of power supplies and improve the cost effectivenessfactor, a single high efficiency supply regulator has becomeincreasingly attractive. Such a regulator would operate over alarge output power/voltage range instead of having multiplesupply regulators optimized at different output settings.Fig. 2 shows the output power limits expected from discrete

power supply modules and the projected monolithic realizationsin different forms and technologies [2]. As can be seen, oper-ating at high switching speeds to reduce the size of the powersupply module through monolithic integration typically resultsin lower output power. Achieving higher levels of output powerand efficiency within a small form factor is currently a chal-lenging research and development task pursued by the scientificcommunity [3]–[5].Switch mode power supplies are good candidates for integra-

tion given their high efficiency compared to linear and hybridregulators [5]–[7]. Operating switch mode regulators at highswitching speed can reduce their passive network size and theoverall module footprint. On the other side, high switching fre-quency would also increase the switching loss in the power de-vices [8]. Furthermore, power efficiency typically reaches itspeak value at maximum output power and drops significantlyduring light load operation, i.e., when the duty ratio is low. Tomaintain high efficiency over a wide output power range, lightload efficiency improvement techniques have been widely in-vestigated. Some of these techniques include phase sheddingand switch segmentation inmulti-phase converters [9], [10], andthe use of variable switching frequencies [11], [12].In multiphase converters, phase shedding and phase seg-

mentation are realized by turning off unneeded phases as therequired current reduces. Thus, the overall efficiency curve

1549-8328/$31.00 © 2013 IEEE

2214 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 8, AUGUST 2013

Fig. 2. Output power versus switching frequency for discrete power supplymodules and projected monolithic implementations [2].

follows the peak efficiency for each phase setting. A similarapproach is called “phase segmentation”, which divides eachpower switch and gate driver into several segments and dis-connects some of them during light load operation [10]. Thistechnique does not require synchronization between phases,and thus reduces the complexity of the control circuitry. Whileboth approaches can improve the average efficiency of theconverter, at light load, the DC-DC converter for both phaseshedding and phase segmentation can fall into DiscontinuousConduction Mode (DCM) due to the smaller load inductorvalue and low current level [9], increasing the output voltageripple.In this paper, a fully integrated DC-DC converter is presented

with switching frequency and output power exceeding the pro-jected monolithic limit shown in Fig. 2. A novel output inductornetwork with positively coupled inductors between segmentsand negatively coupled inductors between phases is proposedin a two-phase four-segment interleaved topology to improvethe effective inductance and reduce inductor current ripple, thusminimizing the potential of falling into DCM. To further im-prove the efficiency at low output power levels, for the singlesegment buck converter, a type II symmetrical resonant gatedriver topology with a partially shared resonant inductor is used,which increases the efficiency at low duty ratios by as much as5%. An analog hysteresis controller is employed for the feed-back control system. The paper is based on our prior publication[13], and includes a complete analysis of the effect of couplingfactors on the ripple reduction and efficiency of the proposedDC-DC converter as well as a detailed explanation of the op-eration and design equations for the resonant gate driver andhysteresis controller with automatic delay corrector.The organization of the paper is as follows. Section II pro-

vides the steady state analysis of the output inductor networkwith positively and negatively coupled inductors. The completecircuit design including power stage, resonant gate driver andclosed loop is discussed in Section III while Section IV presentsthe measurements results. Finally, conclusions are drawn inSection V.

II. MULTI-PHASE DC-DC CONVERTERSWITH DUAL POLARITYCOUPLED INDUCTORS

Conventional multi-phase interleaved DC-DC converters,shown in Fig. 3(a), are widely used to reduce the size of in-

ductors per phase [3], [4], [14]–[18]. However, considering theinductor current per phase and the operational mode, inductorsize in multi-phase topologies can not be easily derived as

, where is the required inductance for thesingle phase operation under the same specifications and Nis the number of phases. Although smaller inductance valuesare used compared to the single phase operation, multi-phaseDC-DC converters require an increased number of inductorswhich can increase the size of the overall module. Anotherissue that affects the performance of multi-phase converters isthe drop in efficiency under medium and light load conditions,as each phase operates far from the optimal design conditions.Phase shedding and/or phase segmentation can be used toeliminate unneeded phases of the power switch and gate driversegments during light load operation [9], [10]. The outcomein this case is an efficiency curve that would ideally followthe peak of the efficiency curves of each phase/segment atdifferent output currents as shown in Fig. 3(b). However, atlight load, the DC-DC converter for both phase shedding andphase segmentation can fall into Discontinuous ConductionMode (DCM) due to the smaller load inductance value andthe low current level [9], increasing the output voltage ripple.Higher load inductance and capacitance or a variable switchingfrequency is necessary to avoid this effect.To increase the effective inductance and current ripple can-

cellation, coupling between the different phases and segmentscan be introduced as proposed in Fig. 3(c) for the case of atwo-phase four-segment output network. In general, a positivecoupling factor increases the effective inductance value betweensegments and a negative coupling factor reduces inductor cur-rent ripple between phases [14], [16]. Thus, the efficiency inFig. 3(b) tends to increase (solid line) when employing phaseshedding and/or phase segmentation. For a one-phase one-seg-ment operation, the efficiency will be the same as the conven-tional topology shown in Fig. 3(a). However, for a two-phasetwo-segment and two-phase four-segment mode, the proposedarchitecture is expected to deliver higher efficiency due to theripple reduction introduced by the multi-polarity coupled induc-tors scheme analyzed below. It also decreases the phase delaycomplexity in the control loop design compared to conventionalfour phase interleaved structures as will be shown in the fol-lowing analysis.The proposed architecture, shown in Fig. 3(c), is based on a

two-phase interleaving structure. Each phase is divided into twoequal segments that consist of the power switches and the gatedrivers. There are three operational schemes: (1) two-phasefour-segment at full load, (2) two-phase two-segment atmedium load, and (3) one-phase one-segment at light load. Toprevent the converter from operating in a DCM, four additionalinductors are added and a positive coupling coefficient isintroduced between segment inductors ( and ) toimprove the effective inductance value. Furthermore, negativecoupling between phases ( and ) is employed to reducethe inductor current ripple and improve efficiency.To quantify the effect of the coupling coefficients and

in the proposed topology, we assume and can be eitherpositive or negative and all the inductors have the same value.

PENG et al.: 100 MHZ TWO-PHASE FOUR-SEGMENT DC-DC CONVERTER 2215

Fig. 3. (a) Conventional four phase buck converter, (b) efficiency versus loadcurrent for multi-phase converters employing phase shedding/segmentations,(c) proposed two-phase, four-segment buck converter with coupled inductornetwork.

Based on the current charge balance equation [19], the inductorcurrent per segment can be derived as

(1)

The inductor current at and is the sum of ( and ) and( and ). In a two-phase, four-segment operation, as shown in

Fig. 4. Steady state waveforms of the proposed output stage with coupledinductors.

Fig. 3(b), is equal to and is equal to such thatcan be given by

(2)Using the steady state switching node voltage and inductor

current waveforms shown in Fig. 4, for a duty ratio larger than0.5, there are four different operational states. During both stateI and state III, , , in stateII, , , , and in state IV, wewill have , , . By adding upthe current ripple expressions over the entire period, the steadystate ripple per phase for is as follows:

(3)

Similarly, for duty ratios , the current ripple can begiven by

(4)For comparison the current ripple per segment for the uncou-

pled condition is defined as in (5) such that

(5)

The current ripple reduction factor can bederived as:

for

for

(6)


Fig. 5. Effect of on current ripple reduction when .

The effect of can be easily shown by examining the twosegments in one phase and assuming in (3) and (4),where the current ripple is given as

(7)

Thus, for , the ripple reduction factor is

(8)

It is obvious that the larger , the smaller current the rippleper segment with a maximum ripple reduction of 25% comparedto the non-coupled condition at as shown in Fig. 5.However, given practical limitations for coupling coefficients,the highest coupling factor achieved for is about 0.8 and theripple reduction factor is 0.79.Fig. 6 shows the effect of at different duty ratios for. Current ripple reduction factor changes significantly with

different combinations of and duty ratio. For example, atD=0.5, varies from 0.55 to 1.4 when is swept from to0.9 and the optimal is . For D=0.4/0.6, the optimumis with 31% improvement in current ripple. For D=0.1/0.9with of , we can get 20% ripple reduction. As can beseen from the figure, the proposed structure expands the rangewhere the ripple reduction region is achieved to positive cou-pling factor range although the optimum point still exists fornegative coupled . It also reduces the sensitivity of to dutyratio variations compared to traditional two phase interleavedtopology with negative coupled inductors.To demonstrate the performance of the proposed two-phase

four-segment output network with positively-and-negativelycoupled inductors, the output stage of the DC-DC converter issimulated using CMOS process parameters with 5 Vdevices. Operating at 5 V/2.5 V conversion ratio with 100 MHzswitching frequency, Table I compares the simulated currentripple per segment and the converter’s output stage efficiencyfor three different coupling conditions. For small duty ratios,the effect of negatively coupled inductors is not significant.However, for 50% duty ratios, the ripple reduction percentageis 45% for compared to 21% for case.The efficiency improvement is mostly related to the positivecoupled inductors , with a maximum efficiency improvement

Fig. 6. The variation of the current ripple with coupling factor for differentduty ratios at .

TABLE IRIPPLE REDUCTION AND EFFICIENCY COMPARISON FOR

DIFFERENT OPTIMUM AND

around 1.2% at 50% duty ratio for the case of tight positivelycoupled inductors at .

III. CIRCUIT IMPLEMENTATION OF 100 MHZ TWO-PHASEFOUR-SEGMENT CMOS DC-DC CONVERTER

The complete two-phase, four-segment DC-DC converter,shown in Fig. 7 is designed in CMOS technology with5 V transistors used in the power stage and 1.8 V transistorsin the control loop. It targets 5 V input, 1–4 V output and 2 Atotal current. One significant source of power loss at light loadconditions is the gate driver loss which does not scale with theoutput current, particularly at high switching speeds [16], [20].One possible solution to reduce the gate driver loss is to addanother energy storage component between the output of thegate driver and the power switch gate terminal to change theenergy distribution. Such driver is known as the resonant gatedriver. Resonant gate drivers are introduced in Section III-A,and a new combined high-side and low-side CMOS resonantgate driver circuit is presented with partially shared resonantinductance. The remaining building blocks, including powerswitches, coupled inductors, hysteresis comparator, and delaycells with duty ratio auto-correction circuits are discussed inSections III-B–III-D respectively.

A. Resonant Gate Driver

Conventional gate drivers suffer from high loss at reducedoutput power settings. This loss is even more pronouncedat high switching frequencies. Resonant type gate drivers


Fig. 7. Full schematic of hysteretic controlled two-phase four-segment CMOS DC-DC converter.

Fig. 8. Equivalent circuit for a resonant gate driver, (a) charging period,(b) discharging period.

have been proposed to reduce the power loss and realizesoft-switching transitions by adding another energy storagecomponent [21]–[25]. For such resonant drivers, as shown inFig. 8, and form a resonant circuit with a characteristicimpedance equal to . Thus the gate resistancein this case , which is much smaller than , becomes theonly damping factor in the equivalent circuit, reducing the totalenergy loss.Fig. 9(a) shows the resonant gate driver used in this design.

Switches sw1 and sw2 are the main power switch and syn-chronous rectifier respectively. The high side and low side drivecircuits (HS and LS) have half-bridge topology which consist ofswitches , and , . With deliberately designed asym-metrical control as shown in Fig. 9(b) [23], [26], all the driveswitches can achieve zero-voltage switching (ZVS). Since in aPMOS-NMOS DC-DC converter, same phase driving signalsare used for and , drive LS can be considered as du-plication of Drive HS. is the resonant inductor for drive HSand is the resonant inductor for drive LS. This isdue to the fact that in a PMOS-NMOS DC-DC converter de-sign, a high-side PMOS switch is usually 2–3 times larger thana low-side NMOS synchronous rectifier. In order to equalizerise and fall times for sw1 and sw2, larger resonant inductorsare used for the LS driver. is the blocking capacitor which

removes the DC component of the voltage across the resonantinductors. According to the charge balance over the resonant in-ductors, the steady-state voltage across is , whereis the duty ratio of the power switches. At 100 MHz switchingfrequency, a of 2 nF is selected to block the DC voltageacross .From Fig. 9(b), the resonant inductor current remains at its

peak value during turn-on and turn-off transitions. Based on thecharge balance equation, the peak inductor current can be ap-proximately expressed as

(9)

Here, we assume that the size of the PMOS is wider than theNMOS, and . Thus the totalpeak resonant current can be given as

(10)

, where is the gate-source ca-pacitors of sw1. Thus, the turn-on and turn-off times ofcan be derived as

(11)

Since the resonant inductor affects the turn-on/off tran-sition of the main power switch and determines the peak in-ductor current, there is always a tradeoff between the resonantgate driver loss and the switching loss. The switching loss of thepower switch (eg. sw1 in Fig. 9(a)) can be expressed by

(12)


Fig. 9. (a) Circuit topology and (b) voltage and current waveforms of the proposed CMOS resonant gate driver.

Assuming the rising period equals to the falling period, andaccording to (11)

(13)

Hence, the switching loss of the power switch is proportionalto . Meanwhile, according to (10), the peak current in the res-onant gate driver is inversely proportional to the resonant induc-tance. The power loss in the resonant gate driver has the relationof: . Fig. 10 shows the trend of the two lossschemes. The minimum loss point is the point where the res-onant gate drive loss equals the switching loss. In this design,the output power switches are optimized at 5 V-to-2.5 V con-version at 100 MHz switching frequency with high side switchPMOS of 40 mm and low side switch NMOS of 15 mm. Thus,and ( and ) are selected as 7.5 mm and 2.5 mm (3

mm and 1 mm) respectively using 5:1 ratio compared to powerswitches. Fixed dead time circuits are used to provide non-over-lapping signals for resonant gate drivers, which are composedof clock tree logic gates as shown in Fig. 7. The time ischosen as . According to (11), is selected as 10 nHand is 2 nF. The improvement in efficiency using the reso-nant gate driver can be seen in Fig. 11. The figure compares theefficiency using conventional gate drivers, resonant gate driverswith the case of a power stage without gate driver losses for asingle phase buck converter at load resistance. An im-provement of 8% can be achieved based on simulation results,at a low duty cycle and 1% improvement at peak output power.Since the gate driver loss is the dominant loss component underlight load conditions, resonant gate drivers can greatly improvethe overall efficiency variation.

B. Switching Stage Design

The output stage utilizes a PMOS transistor as a high sideswitch and an NMOS transistor as a low side switch. The powerswitches are optimized at 5 V input to 2.5 V output. Powerswitches have both conduction losses and switching losses. Theconduction loss is proportional to the switch on resistance and

Fig. 10. Switching loss and resonant gate driver loss versus resonant inductor.

Fig. 11. Efficiency versus output voltage for different gate driver topologies at100 MHz switching frequency, and .

inversely proportional to . Switching loss is directly relatedto the gate parasitic capacitances and and is propor-tional to the gate driving charges which determines the turn-onand turn-off transition periods. This means that smaller devicesrequire less driving capability and reduce the gate driver lossand the overall switching loss. The optimum condition is whenthe switching loss equals the conduction loss. Another impor-tant issue for multi-phase DC-DC converters with phase shed-ding/segmentation is to determine the optimum current valueper phase. Fig. 12 plots the output efficiency of the power stage


Fig. 12. Optimum current per phase for 5 V to 2.5 V conversion.

Fig. 13. Coupled inductors layout, (a) positive coupled inductors, (b) negativecoupled inductors.

and gate drivers at different load currents for 5 V input and 2.5V output. The peak current occurs at 1 A load current.

C. Coupled Inductor Design

To implement the coupled inductor network discussed inSection II, copper layers on the PCB are utilized for planarinductors. The thickness of PCB copper layer is with 1oz copper. This is much thicker than most of the metal layersin a typical CMOS process process [27]–[29] and can providehigher quality factors at hundreds of MHz. Furthermore, thespacing between different layers can be selected as low as 2.7mil with Micro Via technology, which can significantly improvethe coupling coefficient between inductors for multi-phase in-terleaved DC-DC converters. Fig. 13 shows the layouts ofdesigned positive and negative coupled inductors. The min-imum size of the inductor is determined by ,when the converter is operating at the boundary of CCM and

TABLE IIPCB INDUCTOR PARAMETERS

DCM [19] and is the average current per segment. Basedon (3) and (4), the minimum inductance can be found as

(14)where is selected as 0.8 between L1 and L2 and isbetween L5 and L6 as shown in Fig. 3(b). For ,

, and , the minimum induc-tance value can be calculated as 3.9 nH. However, for smallerinductor ripple and to consider the inductor area limitation ofPCB laminate, 6 nH inductance is selected for this design.To achieve the highest coupling factor, the positive-coupled

inductors are built on the top and second PCB layers withspacing between layers. The negative-coupled in-

ductors are designed on the top copper layer and the spacingbetween windings are adjusted to achieve the specific couplingfactor of 0.4. Electromagnetic simulation results for the twocoupled inductors are given in Table II.

D. Hysteresis Controller Design

Given the high switching frequency of the presented DC-DCconverter, hysteresis mode control is selected to achieve a fasttransient response [3], [15], [16], [30], [31]. To synchronize thetwo-phase operation, an open loop delay chain with duty ratiocorrector circuit is used to balance the currents in each phaseand avoid current sharing problems. In the presented design, anautomatic duty ratio correction circuit is employed. The func-tion of phase delay is realized by using series connected voltagecontrolled delay cells.For the hysteresis comparator design, the circuit shown in

Fig. 14 is used. It employs a two-stage differential structure witha bias current of . The comparator uses short channel

devices to reduce propagation delay and achieve highAC bandwidth. The simulated small signal bandwidth equals278 MHz at 55 mW power consumption. A level shifter circuitis added after the comparator stage to increase the high level ofthe signal swing from 1.8 V to 5 V to interface with the outputstage.The two-phase interleaved DC-DC converter requires 0 and

180 degrees phase delayed input signals with balanced dutyratio. To generate delayed signal for the second phaseoperation at variable duty ratio inputs, a cascaded analog delay-cell chain is used. However, as demonstrated in Fig. 15, the dutyratio of the delayed signal is reduced by the finite slew rate ofdelay cells. Therefore, another duty ratio corrector loop is intro-duced and conventional voltage controlled delay cells are used


Fig. 14. Hysteresis comparator circuit schematic.

Fig. 15. Circuit schematic of the delay cell and the block diagram of duty ratiocorrector circuits.

to generate the required delay. controls the delay timeby adjusting the effective load resistance of through thebiasing current. The larger leads to a smaller delay time.The maximum delay of a single cell is 1 ns at 1 V. In this design,eight cascaded delay cells are used for a total 5 ns delay witheach cell contributing about 0.625 ns delay at .Since the delay is achieved by adjusting the turn on/off tran-

sitions of each delay cell, the duty ratio of the output signal issmaller than the input signal. At the end of the delay chain, thevariation of duty ratio compared to can be as high as25% causing severe current sharing and distribution problems.Hence, the duty ratio information at the output of the delay chainis adjusted using the duty ratio corrector shown in Fig. 15, whichcompares the average voltage of both and sig-nals and adjusts the duty ratio of accordingly. The cir-cuit is composed of the following blocks; (1) an average valuedetector, (2) Op-amp and (3) duty ratio corrector. The schematicof the average value detector is shown in Fig. 16(a) which is

Fig. 16. Circuit schematic of (a) the average value detector, (b) duty ratio cor-rector, and (c) op-amp circuit.

simply a charge pump circuit. The average output voltage isgiven as:

(15)

where is the off time of the input signal . As seen in(15), the larger the duty ratio, the smaller the output voltage

. In this design, is chosen as and implementedusing on chip metal resistance while is selected as 300 pFand implemented using poly capacitors.TheOp-amp circuit is used to compare the two average values

from the input clock signal and the delayed signal and generatefor the duty ratio corrector. The schematic of the three-stage

differential op-amp is shown in Fig. 16(c). The DC bias of thetwo inputs is 2 V. The output of the Op-amp is sent to the dutyratio corrector circuit as depicted in Fig. 16(b). The voltageis connected to the gate of the load PMOS device to adjust the


Fig. 17. Die photo of the CMOS DC-DC converter with C4 solder bumps forflip chip packaging.

load resistance of the inverter. By changing the value of , theduty ratio of signal can be modified.

IV. MEASUREMENTS RESULTS

The circuit schematic shown in Fig. 7 is implemented inCMOS technology. High voltage 5 V devices are

used for the power switches, gate drivers, and delay chains,while 1.8 V devices are used for the hysteresis comparator toensure minimal propagation delay. The die photo of the chip isshown in Fig. 17, which contains two segments of the converterpower switches and gate drivers, and all the control blocks. Thepositively and negatively coupled inductors are implementedon the PCB laminate with 1oz copper of thickness togenerate the required 6 nH inductance. The output capacitoris 47 nF and is built using discrete 0402 components. Theconverter operates at a peak 4 V supply with 1 V–3.2 V and 0.1A–1.86 A output. The die area is with 30C4 solder bumps for flip chip packaging. The die size is mostlylimited by the solder bumps. The converter die is mounted ona four-layer PCB laminate using Micro Via design rules. Inputdecoupling capacitor of and are mounted closeto the supply pads.The output of the hysteresis comparator is monitored in

Fig. 18(a) using an external reference signal running at 100MHz. The lower and upper limit of the hysteresis window isset at 0.5 V and 2.2 V respectively, estimated using circuitsimulations. The propagation delay at turn-on transitions isabout 0.5 ns and 0.7 ns at turn-off transitions. The two-phasefour-segment interleaved DC-DC converter is tested for closedloop operation and the output is measured using HP Infinium1.5 GHz Oscilloscope. and in the feedback networkare selected as and 2.7 pF respectively for 100 MHzswitching frequency. Fig. 18(b) shows the measured outputsteady state response at and with anoutput ripple of 50 mV. Fig. 18(c) demonstrates the trackingmode output response when the input reference signal is run-ning at 200 KHz, where it can be seen that there is no phasedelay at this reference frequency.Fig. 19(a) compares the efficiency of the resonant gate driver

to a conventional gate driver at 4 V supply and resistor.For conventional gate drivers at a two-phase two-segment op-eration, the efficiency is about 73.8% at 3 V output and drops

Fig. 18. Time domain measurement results: (a) output of the hysteresis com-parator; (b) converter output steady state response and ripple; and (c) closedloop circuit tracking mode performance with reference at 200 KHz.

to 46.4% at 1 V output with 27.8% overall reduction. The ef-fect of the resonant gate driver topology is demonstrated byadding the resonant inductor and the DC blocking capac-itor on the evaluation board. The calculated and simulatedoptimum is about 10 nH. However, considering the PCBtrace inductance, which is about 1 nH/mm, the external discreteimplemented using Coilcraft inductors, is selected as 2 nH

while is equal to 2.7 nF. With resonant gate drivers, 51%efficiency is achieved with 5% improvement at .At 3 V output, the converter gets 75.2% efficiency and 1.4%improvement compared to conventional gate drivers. Fig. 19(b)also plots the conventional gate driver and resonant gate driverloss contribution in terms of different output voltages. By usingresonant gate drivers, the total driver loss reduces from 33.3%to 27.32% at of 0.7 V. However, there is still a significant


Fig. 19. (a) Efficiency versus output voltage at two-phase two-segment oper-ation with conventional gate drivers and resonant gate drivers, (b) gate driverpower loss contribution at different output voltages.

Fig. 20. Output efficiency of the two-phase four-segment operation at differentoutput power.

loss contribution from other driver stages preceding the reso-nant stage. Also since the control signals for the resonant gatedrivers are generated from fixed clock tree circuits, the powerloss of the designed resonant gate driver may still be higher thanits minimum theoretical loss.The output efficiency at different output power levels under

two-phase four-segment operation is plotted in Fig. 20 withload resistor and compared with a typical linear regulator

efficiency at same power range. The peak efficiency reaches77.4% at 5.94 W output. However, the efficiency drops to 72%at 2.8W output and 50.4% at 0.7W output. At full power around6 W, 2% efficiency improvement can be achieved. When theoutput power is around 1.2 W, 25% efficiency improvement isachieved. Efficiency is also measured at different input voltageswhile keeping the output voltage constant. In Fig. 21, the input

Fig. 21. Output efficiency of the two-phase four-segment operation versusinput voltage at .

Fig. 22. Efficiency versus output current at and .

TABLE IIISUMMARY OF MEASURED PERFORMANCE

voltage varies from 1.5 V to 4 V and the output is maintained at1 V. Under two-phase four-segment operation, when the supplyvoltage equals 1.5 V, the efficiency reaches 74.5%. At 4 V inputand 1 V output, the output efficiency is 51%.The phase shedding and segmentation operation is demon-

strated by changing output current at 4 V to 2 V conversion ratioas shown in Fig. 22. The variation of the measured output cur-rent is from 0.1 A to 1.86 A. At Vout = 2 V, the optimum currentfor the single phase one segment operation is 0.75 A and 1.35A for the two-phase two-segment operation. Due to the unavail-ability of lower load resistances, the highest measured currentis about 1.86 A. It is estimated that for the two-phase four-seg-ment operation, the peak efficiency is at .Through reducing phases and segmentations, the converter op-erates at peak efficiency as the load current changes.The large signal tracking mode frequency response is mea-

sured by feeding the reference node with sinusoidal signals atdifferent frequencies and monitoring the time domain reference


TABLE IVEXAMPLES OF STATE-OF-THE-ART INTEGRATED DC-DC CONVERTERS IN SILICON-BASED TECHNOLOGIES

Fig. 23. Tracking mode frequency response: (a) gain, (b) phase.

and output signals. Fourier transformation is applied to bothsignals to generate the required frequency domain response.Fig. 23 shows both the gain and phase responses of the hys-teresis controlled two phase converter. The 3 dB bandwidth isabout 8 MHz. Table III summarizes the measurement resultsof the proposed two-phase four-segment interleaved DC-DCconverter with positively and negatively coupled inductors in

CMOS technology. The comparison between this workand prior art at switching frequencies above 100 MHz is givenin Table IV. At hundreds of MHz switching speed, most of theexisting works have relatively low output powers . Theproposed 100 MHz CMOS DC-DC converter achieves com-petitive efficiency at almost 6 W, which exceeds the expectedlimits projected in Fig. 2 in terms of switching frequency andpeak output power levels. The design is also the first to uti-lize the copper layer on the PCB to build the output coupledinductors. It is also worth noting that higher efficiencies can beachieved by tighter control of the value of the resonant induc-tance. Our simulations show that 8% efficiency improvement

compared to the achieved 5% can be realized using fully inte-grated on-chip resonant inductors at the expense of higher areaon chip. Advanced control techniques for the gate driver signalsand a more compact PCB design would also lead to further ef-ficiency improvements.

V. CONCLUSION

A two-phase four-segment DC-DC converter with combinedresonant gate drivers and positively and negatively coupled in-ductors is demonstrated in 180-nm CMOS technology. The pro-posed coupled inductor network has the advantages of currentripple reduction and potentially smaller die area. Furthermore,with such topology, the operational flexibility improves signifi-cantly using phase shedding as the peak efficiency can be main-tained at different current settings. It is worth noting that the ef-ficiency improvement over conventional multi-phase convertercan be more pronounced for design conditions where the induc-tors are the main power loss contributors. A novel combinedhigh side and low side resonant gate driver improves light loadefficiency by as much as 5%. The designed converter achievespeak efficiency of 77.4% at 4 V-to-3 V conversion operating at100 MHz switching frequency with peak output power of 6 W.The overall efficiency can also be maintained at peak value asthe output current changes from 0.1 A to 1.86 A.

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Han Peng (S’06) received the B.S. degree fromSoutheast University, Nanjing, China, in 2006 andthe Ph.D. degree in electrical engineering at Rensse-laer Polytechnic Institute, Troy, NY, in Aug. 2011.She was a Research Assistant in the Institute

of RF&-OE-ICs. at Southeast University, Nan-jing, China, from 2006 to 2007. During summerof 2009, she was with TriQuint SemiconductorInc., Hillsboro, OR, developing high frequency,fully integrated DC-DC converter systems. Duringsummer and fall of 2010, she was with National

Semiconductor Inc., Santa Clara, CA, USA, working on ultra-high frequencysupply regulators. She is currently with GE Global Research, Niskayuna NYfocusing on high frequency power electronics. Her research interests are in thearea of power management circuit design.

David I. Anderson, photograph and biography not available at the time ofpublication.

Mona Mostafa Hella (SM’96–M’01) receivedthe B.Sc. and M.S. degrees (with honors) fromAin-Shams University, Cairo, Egypt, in 1993 and1996, and the Ph.D. degree in 2001 from TheOhio-State University, Columbus, OH, USA, all inelectrical engineering.She was a Senior Designer at Spirea AB, Stock-

holm, Sweden working on CMOS power amplifiers(2000-2001). From 2001 to 2003, she was a seniorcircuit designer at RF Micro Devices Inc., Billerica,MA working on Optical communication circuits

and silicon-based wireless systems. She joined the Electrical, Computer andSystems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY,USA, in 2004 where she is now an Associate Professor. Her research interestsinclude the areas of mixed-signal and high speed integrated circuits for wirelessand wireline applications.

a 100 mhz two-phase four-segment dc-dc converter with light load efficiency enhancement in...

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