A 12-bit Resolution, 200-MSample/second PhaseModulator for a 2.5GHz Carrier with Discrete

Carrier Pre-Rotation in 65nm CMOSTaylor W. Barton, SungWon Chung, Philip A. Godoy, and Joel L. Dawson

Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139

Abstract— A digital-to-RF phase modulator based on asingle current-steering DAC is presented, including a carrierpre-rotation scheme that prevents phase inaccuracy dueto carrier feedthrough. The phase modulator has beenfabricated in a standard 65-nm CMOS process and draws1.9 mW from a 1-V supply. The modulator achieves 12-bitresolution at a measured 200 MSamples/second, state-of-the-art performance in both resolution and sampling speed. Ithas sufficient speed to allow for oversampling to shape theoutput spectrum and therefore reduce filtering requirements,as demonstrated through a 32x oversampled 8-PSK signal at6.25 MSymbols/second with under 6.1% EVM.

Index Terms— Radio frequency integrated circuits, phaseshifters, CMOS, phase modulation.

I. INTRODUCTION

This paper presents a digital-to-RF phase modulator(DRFPM) that has both the speed and the accuracy re-quired for demanding applications such as outphasing andPSK transmitters. Such transmitters place a heavy demandon the phase modulator. For example, an outphasing-typearchitecture as in [1] relies critically on precise phasecontrol for highly linear modulation. At the same time, thephase modulator must handle a signal that is significantlybandwidth expanded due to the nonlinear transformationfrom an I/Q representation to amplitude/phase.

The DRFPM presented in this work, with its 12-bitphase resolution and 200 MSample/second sample rate,demonstrates state-of-the-art performance in terms of sam-ple rate, resolution, and power dissipation. It introduces acarrier pre-rotation scheme to overcome effects of carrierfeedthrough and thereby extend the accuracy and operatingrange.

II. TOPOLOGY

A block diagram of the single-DAC topology is shownin Fig. 1. The phase modulator works on the principleof vector addition, where a signal with arbitrary phaseis generated by summing weighted components of sineand cosine. Although in general this function can beperformed with arbitrary coefficients a and b, with outputSout(t) = ±a cos(ωt)± b sin(ωt), imposing the constraintthat b = 1−a has several advantages. With only one DACrequired, area and power are nearly halved compared toa rotator scheme as in [1], as is the number of current

φ [0 : 9]

a

1 − a

cos(ωt)

sin(ωt) quadrant[0:1]

Sout(t)

±1

±1CurrentDAC

Fig. 1. Block diagram for single-DAC phase modulator, excludingcarrier pre-rotation. The phase-modulated output signal is Sout =±a cos(ωt)±(1−a) sin(ωt), where coefficient 0 ≤ a < 1 is controlledby digital input φ[0 : 9].

sources requiring strict matching. Amplitude variation inthe output is limited to a factor of 1/

√2 within full scale,

and is removed with a limiter stage. This approach isrelated to those used in [2] and [3] to reduce the number ofrequired current cells over the more conventional approachof [1]. The relatively high phase resolution of this work ascompared to [2], [3] makes the area and power advantagesof a single-DAC topology significant.

The phase nonlinearity introduced by using a cos(ωt)and (1 − a) sin(ωt) instead of the conventional a cos(ωt)and (

√1 − a2) sin(ωt) is compensated for in our testing

using a static lookup table. Modern transmitters increas-ingly rely on such digital assistance [1]. Here we exploitthis trend to simplify the DRFPM and get higher speedand resolution for lower area and power consumption.

A. Core Topology

The current-steering DAC is implemented as shownin Fig. 2 using ten binary-weighted current sources thatare created by the parallel combination of identical unittransistors. The combination of PMOS and NMOS de-vices allows the use of NMOS transistors for the criticalswitching at the carrier frequency, with PMOS devicesselected for the relatively slow sample rate switching andstatic current generation. The current sources are steeredby latched differential switches that establish the currentscorresponding to a and b = 1 − a. The data switches andtheir drivers are scaled in area in a binary-weighted sense

978-1-4244-8292-4/11/$26.00 ©2011 IEEE

bit 3bit 8bit 9

Ia9 Ib9 Ia8 Ib8

Ia3 Ib3 Ia0 Ib0

bit 0

clk I

clk Q

coscos sinsin

Data

LatchLatch

Latch10

sign I sign Q

output

IIP IIN IQP IQN

512× 256× 8× 8×1×

8ILSB

RLRL

Fig. 2. Simplified schematic of the single-DAC DRFPM. Reducing the number of DACs from two reduces the power and area of this block by 50%.The output sinusoid is a sin(ωt)+ (1−a) cos(ωt), and amplitude variation is removed by the limiters. Ten bits are shown near the top of this figure.The remaining two bits are achieved through the sign of I and Q.

by combining unit cells based on the buffer-latch-switchstructure in [4]. The area scaling results in a matchedvoltage at the drain of the current sources, allowing asimple current mirror to be used because the data switchesact like a cascode.

Differential switches are driven by quadrature squarewaves at the carrier frequency to perform the multiplica-tion of a cos(ωt) and (1 − a) sin(ωt). As with the dataswitches and latches, the multiplicity of the differentialswitch pairs is scaled corresponding to the current. Theminimum size unit switching cell is used for the fourleast significant currents combined, then each higher bituses a binary-scaled number of parallel unit switchingcells. Scaling in this way reduces the total area cost ascompared to simply using binary-scaled sizing for all bits.The resulting code-dependent difference in drain voltagefor the four least significant bits has a limited effect onthose current sources due to the cascode effect from thedata switches.

The current-mode outputs of the multiplying switchesare summed. The sign of these now differential signals,and thus the quadrant of the output, is controlled by twocontrol inputs and is selected using differential switcheswith cross-coupled outputs. Currents are combined andconverted to voltages to produce a differential phase-

modulated signal. A limiter maintains the phase (zero-crossing) information while normalizing the signal ampli-tude.

B. Carrier Pre-rotation

Due to carrier feedthrough and transistor leakage, itis difficult with any current-steering-based architecture toprovide outputs directly aligned with the quadrature carriersignals, since the scaled vector coefficients a and (1 − a)can never be made zero. The resulting missing codes inoutput phase can limit the absolute phase accuracy. For thefabricated DRFPM a gap of 3.7 degrees was measured.

The missing codes problem was solved by using twosets of quadrature signals at the carrier frequency. In thisstrategy, one set is delayed with respect to the other tofunction as a pre-rotated carrier. By thus providing tworeference phases, any output phase can be produced solong as the output phase gaps do not overlap. Both carriersignals are generated on-chip from a differential source attwice the carrier frequency using the static 2:1 frequencydivider shown in Fig. 3. The phase delay between thetwo sets of quadrature carrier signals is generated usinginverter delays. A more well-controlled phase shift is notrequired as the precise amount of prerotation is not criticalso long as it is greater than the total angle subtended by themissing codes. The inverter delay was chosen to give an

2fc

sel

clk I

clk QD

D

D

D

Q

Q

Q

Q

Q

Q

Q

Q

Fig. 3. LO generation and discrete pre-rotation.

0 1024 2048 3072 4096Digital Code Word

0

90

180

270

360

Phas

e(D

egre

es)

Unrotated

Prerotated

(a) Raw static curves.

0 1024 2048 3072 4096Digital Code Word

0

90

180

270

360

Phas

e(D

egre

es)

(b) Combined LUT.

Fig. 4. Transfer curves showing (a) un- and pre-rotated outputs and (b)combined LUT made up of eight segments of the curves in (a). Detailin (a) shows missing codes due to carrier feedthrough.

approximately 45 degree phase shift under typical processconditions.

III. MEASURED RESULTS

The DRFPM was fabricated in a 65-nm CMOS process,with an area of 0.26 mm2. The static power consumptionby the current sources for two DRFPMs is 1.9 mW froma 1-V supply. The static raw transfer curve is shown inFig. 3(a), with the lower curve corresponding to unrotatedphases, and the upper demonstrating carrier pre-rotation.The gaps at quadrant transitions are removed by thestraightforward combination of eight segments of thesetwo curves, giving the transfer curve of Fig. 3(b). Thelargest incremental phase transition was measured to be0.99 degrees.

(a) 180◦ step command.

(b) Carrier rotation step command

Fig. 5. DRFPM response to step command. A constant-phase 2.5GHzsinusoid is shown for reference.

Included on-chip to enable communication betweenthe chip and the driving FPGA are LVDS receivers. Tolower pin count we use serialized transmission, in whicheach LVDS receiver handles two interleaved channels. Anerror in the on-chip deserialization block prevents a fullcharacterization above 200 MSamples/second. Thus theDRFPM’s speed is best observed from its step response asshown in Fig. 5. It can be seen that for the worst-case phasetransition of 180 degrees, the output phase settles within 4periods of the carrier, or 1.6 ns. This performance indicatesthat the fabricated circuit has the potential to perform atup to 625 MSamples/second. The carrier pre-rotation path,with its 1.4-ns step response as in Fig. 5(b), demonstratessimilar performance.

The benefit of using a high (32x) oversampling ratioin the baseband digital front-end before upconversion asa way to reduce filtering requirements has been demon-strated in [6]. The DRFPM in this work has an advantageover lower resolution phase modulators in that it can simi-larly exploit oversampling to push zero-order hold replicasto higher frequency. Fig. 6 shows the improvement ofthe spectrum of a 32x oversampled 6.25 MSymbol/second8PSK signal compared to one without oversampling. Both

(a) No oversampling. EVM=5.93% rms. (b) 32x oversampling. EVM=6.09% rms.

Fig. 6. 8-PSK constellation and spectrum at 6.25 MSymbols/second with and without 32x oversampling. Measurement span is 97MHz and 2000symbols.

TABLE I

COMPARISON OF THIS WORK WITH STATE-OF-THE-ART.

Parameter: Carrierfrequency

Measuredsamplerate

Phase res-olution Process

This work 2.5 GHz 200 MSPS 12 bits 65 nm

JSSC’09[1] 0.8-5GHz 50 MSPS 14 bits 90nm

JSSC’09[2] 60 GHz 2.5 GSPS 6 bits 90 nm

PRIME’09[3]

3.1-10.6GHz 3.8 GSPS 4 bits 65 nm

MTT’06[5]

1.75-3.5GHz 500 MSPS 4 bits 0.18 µm

Note: Power consumption figures are not available for refs. [1] and[2]. Power consumption is 2.78mW for ref [3], and 3.6mW for ref [5],compared with 1.9mW for this work.

measurements were performed without using the carrierpre-rotation mode of the phase modulator; i.e. using asingle transfer curve from Fig. 4(a). The comparison to thestate-of-the-art in Table I shows that this work representsstate-of-the-art performance in terms of its combination ofsample rate and resolution.

IV. CONCLUSION

A DRFPM has been shown to be capable of broad-band modulation at a phase accuracy suitable for moderncommunications standards. The phase modulator’s 12-bitresolution gives it the precision necessary to meet the strictlinearity requirements of modern standards.

Its speed allows for oversampling to shape the spectrumand therefore reduce filtering requirements. The single 12-bit plus 1 input control word and single-DAC topologyreduces complexity, size, and power consumption as com-pared to conventional current-steering phase modulators.

ACKNOWLEDGEMENT

The authors wish to thank the TSMC University ShuttleProgram for the fabrication of this design.

REFERENCES

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