A 20 Gbit/s RFDAC-based Direct-ModulationW-band Transmitter in 32nm SOI CMOS

Hasan Al-Rubaye and Gabriel M. Rebeiz

Department of Electrical and Computer EngineeringUniversity of California at San Diego

La Jolla, CA 92093, USA

Abstract—This paper presents a 94 GHz transmitter chipsetin 32nm SOI CMOS. The transmitter employs two 2-bit high-speed RFDACs driven in quadrature, 20 dB gain LO driversand 30 Gbps high-speed digital retimers and deserializers. Thetransmitter chip is capable of supporting BPSK/PAM4/QPSKmodulation schemes, at a saturated output power Psat of +4dBm. A maximum data rate of 20 Gbps was achieved whenoperating in QPSK mode, and 12 Gbps in BPSK and PAM4modes. The chip occupies 1.4 x 0.8 mm2, and consumes 110 mWin BPSK/PAM4 modes and 220 mW in QPSK mode, resulting ina state-of-the-art 9 pJ/bit and 11 pJ/bit efficiency, respectively.

Index Terms—RFDAC, QAM, CMOS, SOI, mm-wave, trans-mitter.

I. INTRODUCTION

There is increasing interest in the development of CMOS-based > 100 Gbps wireless transceivers for short-range server-to-server communications in data centers. Achieving such datarates necessitates moving the wireless carriers to the mm-wave regime. UCSD has successfully built a 155 GHz wirelesstransceiver with QPSK modulation rate up to 20 Gbps with aBER < 10−12 [1]. More recently, Tokgoz et al. measured a 56-Gbps 16-QAM link at W-band [2], which indeed demonstratedthe need to move to higher-order modulation schemes toachieve > 50 Gbps data rates. From a system point of view,however, the previous work falls short in addressing the de-sign bottleneck of high-speed mm-wave system-on-chip (SoC)transmitters. A key issue in these transmitters is the design ofthe digital-to-analog converter (DAC); where previous workopted to instead use external arbitrary waveform generators(AWGs) to generate the high-speed modulation at baseband.

There is a strong need for efficient and high-speed CMOSDACs. Stand-alone baseband DACs with output data rates ashigh as 40 Gbaud/s for PAM4 and PAM8 have been proven,but are inefficient and power hungry, consuming as muchas 2.5 Watts [3]. Direct modulation transmitters employingRFDACs are becoming increasingly attractive at mm-wavefrequencies [4]–[6]. In an RFDAC, the baseband data canbe viewed as being sampled by the LO carrier, with theRF output resembling an upconverted version of the DACimpulse response, thus alleviating the need for an additionalupconversion stage. This solution - besides maximizing theavailable RF bandwidth by bringing the TX modulator rightto the antenna - allows the transmitter to support multi-standards by moving the bulk of the design complexity to the

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RF-DAC

TIA

TIA

20

TIA

20

RF

ClockI_DATA

Q_DATA

Input Output

Gb

ps

20G

bp

s

GH

z

Fig. 1. 32nm SOI CMOS W-band I/Q transmitter architecture.

digital baseband domain, and takes advantage of deeply-scaledCMOS technologies that are becoming increasingly faster androbust as digital circuits but less so in analog blocks.

This work presents a mm-wave transmitter solution at 94GHz with 32nm SOI CMOS. The transmitter topology is basedon two RFDACs that are driven in quadrature and current-combined at the output, as shown in Fig. 1. The chipsetachieves BPSK, PAM4 and QPSK modulations, depending onthe data rate and the RFDACs mode of operation.

II. DESIGN

A. 2-bit RFDAC Design

The RFDAC design is based on a Gilbert cell where thebottom transistors are size-segmented in a binary fashion (Fig.2a). This is an alternative constant-current RFDAC topology tothe one used in [5], which allows the segmented transistors tobe driven by the 1 V thin-oxide SOI CMOS transistors, ratherthan the thick-oxide transistors, allowing the DAC to switchat higher speeds. The switching quad are driven differentiallyby an LO amplifier into saturation. It is not necessary to back-off to produce amplitude modulation in this topology, makingit possible to saturate the output stage, thus increasing itsefficiency at peak output power.

978-1-5090-1608-2/16/$31.00 ©2016 IEEE

20m

A

2.5V

LO+ LO-

D0

30 x 1.0 um

150p Out +Out -

60 x 1 um

Bias

LO+

D1 D0D1

(a)

RFOutput

+2+1 -1-2

OOK0OOK1 OOK1OOK0

LO

(b) (c)

Fig. 2. 2-bit W-band RFDAC. (a) schematic design of binary-weighted Gilbert cell, (b) RFDAC concept of operation, (c) Measured small-signal gain S21

and saturated output power Psat.

This topology can be thought of as an outphasing amplifier(Fig. 2b), where the amplifiers are instead biased in Class-A,which leads to poor efficiency for any constellation outputsother than the peaks. It does, however, allow for the fastestoperation since the output impedance is fixed and is notdependent on the digital-word, which would otherwise causeamplitude and phase distortion in the EVM constellation.Fig. 2c presents the measured small-signal gain S21 of thetransmitter chain, along with the measured saturated outputpower of 3-5 dBm at 85-105 GHz. The S21 of the transmitteris measured by setting the digital input to a static value of(D0 = 1, D1 = 1), thus effectively enabling a single arm ofthe Gilbert cell.

B. High-Speed Digital Design

The choice of the DAC operating mode, and consequentlythat of the modulation scheme, is carried out in the basebanddigital domain. This is consistent with the vision of buildingmulti-mode, reconfigurable and all-digital RF transmitters. Anexternal source of 231 − 1 PRBS data and full-rate clock isused. Upon entering the chip, the data stream is either retimedwith a flip-flop or deserialized into two data streams, each athalf the original data rate, using a 1:2 demultiplexer (Fig. 3a).

The digital blocks are based on TSPC logic which offershigher operating speeds than static CMOS logic and moremoderate power consumption than the CML logic family.The measured results in Fig. 3 show that the digital driveris capable of retiming and demultiplexing data streams fasterthan 30 Gbps and 20 Gbps, respectively. This performancemakes the digital blocks in this design sufficient to support 60Gbps and 40 Gbps data rates in a QPSK/16-QAM operatingmode.

C. W-band LO Driver Design

The LO amplifier used to drive the RFDAC consists ofthree differential cascode stages (Fig. 4a). By operating theamplifier under saturation it reduces the I/Q amplitude imbal-ance introduced by the I/Q coupler. A 1 V supply is used

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100ps

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(b)

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(c)

Fig. 3. Design and eye-diagram real-time measurements of the digital driver inits two modes. (a) Digital baseband RFDAC-driver design, (b) two deserialized10 Gbps outputs from a 20 Gbps PRBS input, (c) retimed 30 Gbps outputPRBS data in retimer mode.

throughout to remain within the safe voltage swing range.Transistor sizes in each stage are incrementally increased by afactor of 1.5 to ensure saturating the amplifier and the RFDAC.Fig. 4b presents the simulated and measured S-parameters.

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Fig. 4. LO amplifier: (a) transistor-level design of the first stage, (b) measuredand simulated S-parameters.

Small-signal gain > 10 dB is obtained from 90-110 GHz witha peak gain of 20 dB at 100 GHz. The differential amplifierconsumes 40 mW from a 1 V supply.

III. MEASUREMENTS

A. RFDAC Measurements

A breakout of the RFDAC shown in Fig. 2a was measuredby applying an external W-band LO signal using the VDIAMC-335 multiplier chain through a WR-10 waveguide probe(Fig. 5). The PRBS data and clock input are obtained from aTektronix 30Gb/s two-channel programmable pattern genera-tor PPG3002. The modulated RF output is then downconvertedwith an external Quinstar QMB waveguide balanced mixerto a 10 GHz IF. The modulated IF output is then directlyapplied to a real-time 100 GS/s DPO73304DX Tektronix scopewith 33 GHz of analog bandwidth. The constellation diagram,frequency spectrum, and eye diagrams are then observed usingthe SignalVu VSA software.

Fig. 6a presents the RFDAC output at 1 Gbps inPAM2/BPSK mode after downconversion to 10 GHz. Thedisplayed constellation shows little or no phase/amplitudedistortion. An EVM of 5% is obtained, limited by the SNR ofthe measurement setup.

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(a)

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(b)

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50ps/div

(c)

Fig. 6. RFDAC measurements: (a) 1 Gbps BPSK oscilloscope outputscreenshot (b) 12 Gbps BPSK eye diagram (c) 12 Gbps PAM4 output.

Fig. 6b and Fig. 6c present the eye diagrams at maximumdata rates obtained in PAM2/PAM4 modes, both at 12 Gbps,with an SNR of 9 and 13 dB, respectively. To our knowledge,this the first experimental demonstration of the EVM and eyediagrams of mm-wave RFDACs, which proves their feasibilityas building blocks for m-QAM transmitters.

B. Transmitter Measurements

A similar measurement setup is used to measure the I/Qtransmitter chip (Fig. 7). The I/Q transmitter employs a 50 Ω-matched varactor-tuned transformer-based quadrature coupler[7]. The accumulation-mode MOS varactors are externallycontrolled with analog voltages. Inevitably, the coupler pro-duces quadrature amplitude errors which are corrected bysaturating the amplifiers following it. Any AM-PM distortionresulting from saturating the driver amplifiers can be correctedby re-tuning the varactors. Two PRBS data sequences repre-senting I/Q data and a full-rate clock are obtained from thePPG and enter the chip through a 50GHz GSGSGSG probe,using 2.4mm coaxial cables. External wideband phase shiftersare used to compensate for any phase mismatch between thedifferent cables.

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90°

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IQ Coupler

Fig. 7. 32nm SOI transmitter chip micrograph.

Fig. 8 presents a 20 Gbps QPSK real-time measurementfor a 95 GHz LO carrier. The RF output occupies 20 GHzof bandwidth (85-105 GHz) and is downconverted with an85 GHz LO source to a 10 GHz IF. The constellation showsan EVM of 24%. This is, to our knowledge, the highest datarate ever reported for a CMOS transmitter below 100 GHz.The transmitter has 4 dBm of output power and consumes

20 Gbps

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Frequency (GHz)

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Fig. 8. Measured QPSK spectrum and constellation at 20 Gbps, LO frequencyset at 95 GHz.

TABLE ICOMPARISON TABLE WITH W-BAND TRANSMITTERS IN SILICON

TECHNOLOGIES.

Reference [7] [2] [5] [8]ThisWork

TechnologyBiCMOS0.18µm

65nmSOI

45nmSOI

45nmSOI

32nmSOI

Frequency [GHz] 88 68/102 90 94 94

Modulation16QAM/32QAM

16QAMASK/OOK

64QAMBPSK/PAM4/QPSK

On-Chip DAC No No Yes Yes YesData Rate [Gbps] 10/8.75* 56** 15 1 12/12/20

Pout [dBm] > 6 -8.4 19 > 10 4Power Cons. [W] 0.5 0.26 - 2.1 0.11/0.22

* For a 1-meter link; fully-packaged transceiver with antennas.** Using predistortion with an external AWG.

220 mW. Table I presents a comparison with state-of-the-artW-band transmitters in silicon.

IV. CONCLUSION

A state-of-the-art 94 GHz transmitter withBPSK/PAM4/QPSK modulation capabilities was presented.The transmitter consists of two current-combined RFDACsthat are driven in quadrature, and is capable of supportingmultiple modulation schemes including BPSK, PAM4and QPSK with max. data rates of 12, 12 and 20 Gbps,respectively, all with EVM values that guarantee < 10−6 ofuncoded BER.

REFERENCES

[1] Y. Yang, S. Zihir, H. Lin, O. Inac, W. Shin, and G. M. Rebeiz, “A 155GHz 20 Gbit/s QPSK transceiver in 45nm CMOS,” in 2014 IEEE RadioFrequency Integrated Circuits Symposium, June 2014, pp. 365–368.

[2] K. K. Tokgoz, S. Maki, S. Kawai, N. Nagashima, J. Emmei, M. Dome,H. Kato, J. Pang, Y. Kawano, T. Suzuki, T. Iwai, Y. Seo, K. Lim,S. Sato, L. Ning, K. Nakata, K. Okada, and A. Matsuzawa, “A 56Gb/s W-band CMOS wireless transceiver,” in 2016 IEEE International Solid-StateCircuits Conference (ISSCC), Jan 2016, pp. 242–243.

[3] H. Huang, J. Heilmeyer, M. Grozing, M. Berroth, J. Leibrich, andW. Rosenkranz, “An 8-bit 100-GS/s Distributed DAC in 28-nm CMOSfor Optical Communications,” IEEE Transactions on Microwave Theoryand Techniques, vol. 63, no. 4, pp. 1211–1218, April 2015.

[4] A. Agah, W. Wang, P. Asbeck, L. Larson, and J. Buckwalter, “A 42 to47-GHz, 8-bit I/Q digital-to-RF converter with 21-dBm Psat and 16%PAE in 45-nm SOI CMOS,” in 2013 IEEE Radio Frequency IntegratedCircuits Symposium (RFIC), June 2013, pp. 249–252.

[5] S. Shopov, A. Balteanu, and S. P. Voinigescu, “A 19 dBm, 15 Gbaud,9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-BandTransmitters,” IEEE Journal of Solid-State Circuits, vol. 49, no. 7, pp.1653–1664, July 2014.

[6] A. Balteanu, S. Shopov, and S. P. Voinigescu, “A High ModulationBandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays WithDirect Amplitude and Phase Modulation,” IEEE Journal of Solid-StateCircuits, vol. 49, no. 10, pp. 2103–2113, Oct 2014.

[7] S. Shahramian, Y. Baeyens, N. Kaneda, and Y. K. Chen, “A 70-100GHz Direct-Conversion Transmitter and Receiver Phased Array ChipsetDemonstrating 10 Gb/s Wireless Link,” IEEE Journal of Solid-StateCircuits, vol. 48, no. 5, pp. 1113–1125, May 2013.

[8] T. LaRocca, Y. C. Wu, K. Thai, R. Snyder, N. Daftari, O. Fordham,P. Rodgers, M. Watanabe, Y. Yang, M. Ardakani, W. Namoos, S. Poust,and M. C. F. Chang, “A 64QAM 94GHz CMOS transmitter SoC withdigitally-assisted power amplifiers and thru-silicon waveguide powercombiners,” in 2014 IEEE Radio Frequency Integrated Circuits Sympo-sium, June 2014, pp. 295–298.