a 2.1-ppm/°c all-mosfet voltage reference with a …...a 2.1-ppm/ c all-mosfet voltage reference...
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A 2.1-ppm/°C all-MOSFETvoltage reference with a1.2-V supply voltage
Huachao Xu1, Yuanzhi Zhang2, Ke Liang1, Jinlong Hu3,Chao Lu2b), and Guofeng Li1a)1 Key Laboratory of Photoelectronic Thin Film Devices and Technology of Tianjin,
College of Electronic Information and Optical Engineering, Nankai University,
China2 Department of Electrical and Computer Engineering, Southern Illinois University,
Carbondale, IL, USA, 629013 School of Electrical and Electronic Engineering, Tianjin University of Technology,
China
Abstract: This paper presents an ultra-low temperature coefficient sub-
threshold voltage reference, which is based on a novel compensation
principle without using any resistors or operational amplifiers. Being im-
plemented on a 0.18 µm standard CMOS process, the post-layout simulation
results show that the proposed design achieves a minimum temperature
coefficient (TC) of 2.1 ppm/°C over the temperature range of −40 °C to
100 °C with a 1.2V supply voltage. This proposed design also shows the
worst line regulation of 0.034%/V at room temperature, when the supply
voltage varies from 1.2V to 1.8V. Due to the elimination of resistors and
amplifiers, the circuit area is at least 91% less than existing designs.
Keywords: voltage reference, sub-threshold, low temperature coefficient
Classification: Integrated circuits
References
[1] K. Ueno, et al.: “A 300 nW, 15 ppm/°C, 20 ppm/V CMOS voltage referencecircuit consisting of subthreshold MOSFETs,” IEEE J. Solid-State Circuits 44(2009) 2047 (DOI: 10.1109/JSSC.2009.2021922).
[2] H. Xu, et al.: “A 0.45 ppm and low phase noise analog crystal oscillator usinga four order temperature compensation algorithm,” AEU Int. J. Electron.Commun. 90 (2018) 69 (DOI: 10.1016/j.aeue.2018.04.005).
[3] H. Xu, et al.: “A novel 0.84 ppm/°C CMOS curvature-compensated bandgapwith 1.2V supply voltage,” AEU Int. J. Electron. Commun. 91 (2018) 66(DOI: 10.1016/j.aeue.2018.05.001).
[4] Y. Zeng, et al.: “A 12.8 nA and 7.2 ppm/°C CMOS voltage reference withoutamplifier,” IEICE Electron. Express 15 (2018) 20171220 (DOI: 10.1587/elex.15.20171220).
[5] L. Magnelli, et al.: “A 2.6 nW, 0.45V temperature-compensated subthresholdCMOS voltage reference,” IEEE J. Solid-State Circuits 46 (2011) 465 (DOI:
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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LETTER IEICE Electronics Express, Vol.15, No.23, 1–6
10.1109/JSSC.2010.2092997).[6] Y. Liang and Z. Zhu: “A 42 ppm/°C 0.7V 47 nW low-complexity all-
MOSFET sub-threshold voltage reference,” J. Circuits Syst. Comput. 27 (2018)1850105 (DOI: 10.1142/S0218126618501050).
[7] Y. Liu, et al.: “An ultralow power subthreshold CMOS voltage referencewithout requiring resistors or BJTs,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst. 26 (2018) 201 (DOI: 10.1109/TVLSI.2017.2754442).
[8] A. C. de Oliveira, et al.: “Picowatt, 0.45–0.6V self-biased subthreshold CMOSvoltage reference,” IEEE Trans. Circuits Syst. I, Reg. Papers 64 (2017) 3036(DOI: 10.1109/TCSI.2017.2754644).
[9] I. Lee, et al.: “A subthreshold voltage reference with scalable output voltagefor low-power IoT systems,” IEEE J. Solid-State Circuits 99 (2017) 1 (DOI:10.1109/JSSC.2017.2654326).
[10] H. Zhang, et al.: “A nano-watt MOS-only voltage reference with high-slopePTAT voltage generators,” IEEE Trans. Circuits Syst. II, Exp. Briefs 65 (2018)1 (DOI: 10.1109/TCSII.2017.2654441).
1 Introduction
Voltage references are indispensable in many systems, such as ADCs, TCXOs, etc.
[1, 2]. In general, bandgap references based on vertical bipolar transistors are often
used in these systems [1]. With the rapid popularity of portable devices, the need
for low power supply voltage, small size, and low current consumption is increas-
ing. The low current consumption bandgap references need large resistors to
decrease currents, which largely increase the chip areas [1, 3]. Therefore, all-
MOSFET voltage references based on sub-threshold MOSFETs have been devel-
oped in recent years [1, 4, 5, 6, 7, 8, 9, 10]. These all-MOSFET voltage references
can operate at low current consumption and small chip sizes. However, due to the
inaccuracy of the temperature compensation principle, these voltage references
can only achieve an optimal TC of 7 ppm/°C [1, 4]. Based on this design challenge,
this paper proposes a new compensation principle without using any resistors or
amplifiers. The proposed voltage reference reaches a low TC of 2.1 ppm/°C.
2 The principle of proposed voltage reference
The schematic of the proposed all-MOSFET voltage reference is shown in Fig. 1.
The circuit consists of a startup circuit, a current source circuit, and a voltage
reference generation circuit. The startup circuit provides a bias current for the
current source circuit and helps to get rid of degeneration during a power-up phase.
The current source circuit provides a reference current for the voltage reference
generation circuit. All the transistors are 1.8V MOSFETs, except that MN5 is a
5V MOSFET.
If a MOSFET operates in a sub-threshold region, and its drain-source voltage
exceeds 100mV, its drain current can be approximately expressed as [4]
ID � �COXKð� � 1ÞVT2 exp
VGS � VTH
�VT
� �ð1Þ
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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where μ is the carrier mobility, COX is the gate oxide capacitance, K is the aspect
ratio of a MOSFET, VT ¼ kBT=q is the thermal voltage, kB is the Boltzmann
constant, T is the absolute temperature, q is the electron charge, VGS is the gate-
source voltage, VTH is the threshold voltage, η is the sub-threshold slope factor [1].
Among these device parameters, μ, VT and VTH are related to temperature. In a
typical CMOS process, the carrier mobility μ of 1.8V and 5V NMOS transistors is
almost equal. Due to the different VTH for 1.8V and 5V NMOS transistors, VTHA
and VTHB are marked for 1.8Vand 5V NMOS transistors, respectively. Despite that
threshold voltages of MOSFETs are weakly dependent on their source-substrate
voltages, for the sake of simplicity, the drain-induced barrier lowering (DIBL)
effect is ignored in the following analysis. Moreover, COXA and COXB represent for
1.8V and 5V NMOS transistors, respectively. �A and �B are labeled for 1.8V and
5V NMOS transistors, respectively.
In Fig. 1, MN1 and MN2 operate in strong inversion regions, while other
transistors operate in weak inversion, or sub-threshold regions. The aspect ratio of
MN2 and MN1 is 3:1. The aspect ratio of MN3 and MN4 is also 3:1. According to
Eq. (1), the difference between the gate-source voltages of MN3 and MN4 can be
expressed as [1]
�V ¼ VGSN3 � VGSN4 ¼ �AVT lnK4
K3
ð2Þ
The currents flowing through MN1 and MN2 are equal and expressed as
I0 ¼ 1
2�COXAK1ðVGS1 � VTHAÞ2 ¼ 1
2�COXAK2ðVGS1 þ �V � VTHAÞ2 ð3Þ
Thus,
I0 ¼ 1
2�COXAK1
�V2
ð ffiffiffiffiffiffiffiffiffiffiffiffiffiK1=K2
p � 1Þ2
¼ 1
2COXAK1�A
2 K2
ð ffiffiffiffiffiffiK1
p � ffiffiffiffiffiffiK2
p Þ2 lnK4
K3
� �2
�VT2 ¼ ��VT
2
ð4Þ
In Eq. (4), �VT2 is temperature dependent, while other parameters that are lumped
into σ, are constant. In [1], the temperature dependence of threshold voltage of a
MOSFET can be expressed by
Fig. 1. Proposed schematic of all-MOSFET voltage reference
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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IEICE Electronics Express, Vol.15, No.23, 1–6
VTH ¼ VTH0 þ �T ð5ÞHere VTH0 is the threshold voltage at 0K (hypothetical), α is a negative constant. In
our selected CMOS process, �A is −0.76mV/°C, and VTHA0 is 688mV for 1.8V
NMOS. For 5V NMOS, �B is −1.37mV/°C, and VTHB0 is 1352mV in this process.
The voltage at the node A of Fig. 1 can be expressed as
VA ¼ VGSN5 � VGSN6
¼ �BVT lnI0
�COXBK5ð�B � 1ÞVT2þ VTH5
� �AVT lnI0
�COXAK6ð�A � 1ÞVT2� VTH6
¼ �BVT ln�
COXBK5ð�B � 1Þ � �AVT ln�
COXAK6ð�A � 1Þþ VTHB0 � VTHA0 þ ð�B � �AÞT
¼ �T þ ð�B � �AÞT þ VTHB0 � VTHA0
ð6Þ
Where γ is a defined constant. In Eq. (6), γ is very small when compared with
the term of �B-�A. Therefore, the TC of VA is negative. In order to compensate
the negative TC of VA, MN7∼MN10 are adopted because MN7∼MN8 and
MN9∼MN10 are two proportional to absolute temperature (PTAT) voltage gen-
erators [1]. The reference voltage VREF can be expressed as
VREF ¼ VA þ ðVGSN7 � VGSN8Þ þ ðVGSN9 � VGSN10Þ
¼ ð� þ �B � �AÞT þ VTHB0 � VTHA0 þ �AVT lnK8K10
K7K9
ð7Þ
If Eq. (7) is satisfied with the following condition in Eq. (8),
� þ �B � �A þ �AkBqlnK8K10
K7K9
¼ 0 ð8Þ
a fully temperature independent voltage reference can be obtained and its output is
VREF ¼ VTHB0 � VTHA0 � 667mV ð9ÞThe perfect aspect ratios of the MOSFETs are set under TT corner according to
Eq. (8). However, η, μ, COX and VTH vary with process variation, and therefore
they worsen the temperature coefficient in different corners. From Eq. (4) to
Eq. (7), we can know that the local mismatches of the MOSFETs can change the
first order temperature coefficient in Eq. (7). In order to correct the process
variation and the mismatch effect, 5-bit trimming circuits for MN10 and MN8
are designed for the proposed voltage reference, as shown in Fig. 1.
3 Simulation and discussion
Fig. 2(a)–(c) show the post-layout simulation results of output reference voltages as
a function of temperature at five process corners after proper size trimming of MN8
and MN10 with a 1.2V supply voltage. The TC is 2.1 ppm/°C, 4.3 ppm/°C,
4.5 ppm/°C, 3.9 ppm/°C, and 3.9 ppm/°C at TT, FF, FS, SS, or SF corner,
respectively. The reference voltages at none-TT process corners and 27°C have
large deviations with that at TT corners. This is because the threshold voltage
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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differences for 5V and 1.8V NMOS transistors are quite large in these process
corners. In addition, it is observed that the output voltage at TT corner is about
596mV, which is smaller than the ideally expected value of 667mV. This is
because the threshold voltages of MN7∼MN8 and M9∼M10 are the functions of
their source-substrate voltages. For example, the source voltage of MN7 is lower
than that of MN8. Then the threshold voltage of MN7 is lower than that of MN8.
Therefore VGSN7-VGSN8 is lower than the ideal value in Eq. (7), and thus brings
extra deviation to the reference voltage.
Fig. 2(d) shows the post-layout simulation results of output reference voltages
as a function of temperature at TT corner with a supply voltage of 1.2V to 1.8V
with the step of 0.1V. The resultant worst line regulation (LR) at 27°C is
0.034%/V.
Fig. 2(e) plots the distribution of output reference voltage after Monte-Carlo
(MC) simulation at 27°C under 500 random mismatch samples. The mean
value and standard deviation are 596.45mV and 26.71mV, respectively. Fig. 2(f )
plots the distribution of TC after Monte-Carlo simulation under 500 random
mismatch samples. The mean TC is 11.73 ppm/°C and the standard deviation is
8.3 ppm/°C.
Fig. 3 shows the layout of the proposed voltage reference. Table I shows the
comparison results with state-of-the-art works. Compared with [2] whose core
circuit are BJTs, our design has advantages in the area and current consumption.
Compared with [1, 4, 5] that are all-MOSFET voltage references, our design has
advantages in TC and temperature range. The TC is reduced by at least 70% in the
proposed design, which also covers the widest temperature range.
(c) TCs at SS and SF corners(a) TC at TT corner (b) TCs at FF and FS corners
(f) MC simulation: TC(e) MC simulation:VREF(d) Line regulation at TT corner
Fig. 2. Post-layout simulation results and layout of proposed voltagereference
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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4 Conclusion
We present a new CMOS voltage reference by using a novel compensation
principle without using any resistors or operational amplifiers. A 0.18µm standard
CMOS process is adopted to implement the proposed design. The results after post-
layout simulation show that our design achieves a minimum TC of 2.1 ppm/°C
over a temperature range of −40°C to 100°C under a 1.2V supply voltage. At room
temperature, the resultant worst line regulation is 0.034%/Vover a supply voltage
range from 1.2 to 1.8V. Comparing with the existing sub-threshold voltage refer-
ences in the literature, the proposed design achieves a supreme temperature
coefficient and can operate in a wide temperature range. Due to the elimination
of resistors and amplifiers, the circuit area is at least 91% less than these existing
designs.
Acknowledgment
This research is supported by the Ph.D. Candidate Research Innovation Fund of
Nankai University.
Table I. Comparison with existing sub-threshold designs in theliterature
Parameter [1] [2] [4] [5] This work
Result source Tested Simulated Simulated Tested Simulated
Core device CMOS BJT CMOS CMOS CMOS
Process (µm) 0.35 0.15 0.18 0.18 0.18
Circuit area (mm2) 0.055 0.125 NA 0.043 0.0039
Supply voltage (V) 1.4 1.2 0.75 0.45 1.2
Supply current (nA) 214 51000 12.8 7 125
Ref. voltage (mV) 745 569 319 264 596
Temp. range (°C) �20�80 �40�120 �20�80 0�125 �40�100Best TC (ppm/°C) 7 0.6 7.2 142 2.1
LR (%/V) 0.002 0.023 0.075 0.44 0.034
Fig. 3. Layout of proposed voltage reference
© IEICE 2018DOI: 10.1587/elex.15.20180922Received October 5, 2018Accepted October 29, 2018Publicized November 14, 2018Copyedited December 10, 2018
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