a 2.4-ghz resistive feedback lna

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009 3019

A 2.4-GHz Resistive Feedback LNAin 0.13-�m CMOS

Sanghoon Joo, Student Member, IEEE, Tae-Young Choi, Member, IEEE, and Byunghoo Jung, Member, IEEE

Abstract—A -boosted resistive feedback low-noise amplifier(LNA) using a series inductor matching network and its applica-tion to a 2.4 GHz LNA is presented. While keeping the advantage ofeasy and reliable input matching of a resistive feedback topology, ittakes an extra advantage of -boosting as in inductively degener-ated topology. The gain of the LNA increases by the -factor of theseries RLC input network, and its noise figure (NF) is reduced bya similar factor. By exploiting the -boosting property, the pro-posed fully integrated LNA achieves a noise figure of 2.0 dB, S21of 24 dB, and IIP3 of �� dBm while consuming 2.6 mW from a1.2 V supply, and occupies 0.6 mm� in 0.13- m CMOS, which pro-vides the best figure of merit. This paper also includes an LNA ofthe same topology with an external input matching network whichhas an NF of 1.2 dB.

Index Terms— -boosted LNA, low-noise amplifier (LNA),noise figure, resistive feedback, voltage gain boosting.

I. INTRODUCTION

T HE demand for a low-cost, high performance wirelessfront-end system and aggressive device scaling has

triggered intensive research on CMOS radio-frequency (RF)front-end circuits. The ever increasing demands for high perfor-mance, low-cost, and constantly operating mobile devices haveencouraged researchers to explore the edge of state-of-the-artradio-frequency integrated circuits (RFIC) and pursue thecontradictional goal of high performance with low-powerconsumption.

In addition to low-power, as the first active block in thereceiver chain, the performance of an LNA dictates the overallnoise performance of receivers, thus various CMOS LNAtopologies have been studied [1]–[6]. Popular LNA topolo-gies are the inductively degenerated common-source LNA(L-CSLNA) [1], [2], the common-gate LNA (CGLNA) [3], andthe resistive feedback LNA (RFLNA) [4]. Each topology hasdistinct advantages and limitations. To overcome the limitationsand exploit the merits of each topology, many combined archi-tectures have been investigated. For example, the L-CSLNA hasbeen combined with an LC ladder filter or a resistive feedbackscheme to achieve broadband input matching [7]–[11], and theCGLNA has been merged with a common source scheme tocancel noise of an input device [12]–[20].

Manuscript received April 13, 2009; revised July 17, 2009. Current versionpublished October 23, 2009. This paper was approved by Associate Editor JanCraninckx. This work was supported in part by the Electronics and Telecom-munications Research Institute.

The authors are with the School of Electrical and Computer Engineering,Purdue University, West Lafayette, IN 47907 USA (e-mail: [email protected];[email protected]; [email protected]).

Digital Object Identifier 10.1109/JSSC.2009.2031912

Fig. 1. Input matching network. (a) Parallel RLC. (b) Series RLC.

This paper proposes a new low-power LNA scheme whichcombines the merits of -boosting from inductively degen-erated topology and input impedance matching from resistivefeedback topology. Section II begins with input matching net-works of LNAs and compares the pros and cons of conven-tional topologies. Section III describes the concept of the pro-posed LNA, performs a small-signal noise analysis includingthe drain channel noise and the induced gate noise, and com-pares its noise performance with the traditional architectures.The implementation and experimental results of the LNA arepresented in Sections IV and V, respectively. The paper con-cludes in Section VI.

II. CONVENTIONAL LNA TOPOLOGIES

The first active front-end RF block, which is an LNA, needsto match its input impedance to an external component such asan antenna, a band select filter, or an RF switch. This matchingnetwork can be a parallel or series resonator as shown inFig. 1. Typically, the shunt RLC easily achieves impedancematching, but it does not have any voltage gain across the ca-pacitor , which is usually a gate-source capacitor ,i.e., . For the LNAs with the shunt RLC matchingnetwork, a gain boosting block in front of a main stage isobserved in [3], [21], [22]. They utilize capacitive coupling ora transformer as a gain booster, which increases the voltageacross the gate and source of an input device and reduces thenoise figure by increasing the effective transconductance. Thevoltage gain stage using passive devices prior to an activedevice should add very little noise and amplify the RF signalbefore the signal is corrupted by noise from active devices. Itis also possible to match the input impedance using a seriesRLC network which could generate times of voltage gainacross [1]. At a resonant frequency , the quality factoris given by and the voltage acrossis . Therefore, the inductively degenerated commonsource topology with a series RLC input network can takeadvantage of the increased effective transconductance of aninput device to reduce the noise figure.

0018-9200/$26.00 © 2009 IEEE

3020 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

Fig. 2. Conventional LNA topologies. (a) Inductively degenerated common-source LNA (L-CSLNA), � � �� , � � � � �� . (b)Resistive-feedback LNA (RFLNA), � � � , � � �� . (c) Common-gate LNA (CGLNA), � � �� , � � �� . (d) � -boostedCGLNA [21], � � � �� , � � �� .

The shunt RLC configuration has been frequently employedin the RFLNA [Fig. 2(b)] and CGLNA [Fig. 2(c)], while theseries RLC has been used in the L-CSLNA [Fig. 2(a)]. TheL-CSLNA is the dominating topology for narrowband systemsdue to its advantages such as low NF, ease of input matching,high gain, and low-power consumption. However, these benefitscome at the cost of large chip area due to the two inductors; oneat the gate and another one at the source of the input device.For those inductors to resonate at low operating frequencies,impractically large inductance values would be required. Thiscan be avoided by using an extra capacitor between the gateand source of the transistor, but this topology reduces thegain and degrades NF [23]. The RFLNA [Fig. 2(b)] provideswideband input and output matching and small die area becauseno inductor is required for input matching. However it has apoor NF and consumes a large amount of power. When thesize of is increased to reduce the NF, it requires a shuntinductor to improve input matching. The CGLNA [Fig. 2(c)]can also provide wideband input matching, but suffers frompoor noise performance compared with the L-CSLNA whenthe operating frequency is considerably lower than theunity gain frequency [3]. Matchingthe input impedance of the CGLNA to the sourceimpedance limits the choice of power consumption and devicesize. Narrowband matching can be improved by adding a shuntinductor that resonates with the parasitic shunt capacitor ofthe input device. A -boosted CGLNA shown in Fig. 2(d)has been proposed to remedy the high NF issue, but still hastheoretically higher NF than L-CSLNA at practical operatingfrequencies [21]. It is worthwhile to emphasize that the inputof an L-CSLNA forms a series RLC network, whereas thatof a CGLNA forms a parallel RLC network. In addition, thevoltage across the capacitor of an L-CSLNA corresponds to

( , where is the source resistance)times the input voltage at the resonance frequency due to theseries RLC matching network which is the key for its high gainand low NF.

III. PROPOSED LNA ARCHITECTURE

To take advantage of voltage gain boosting in LNA design,the proposed LNA merges a series RLC input matching networkwith a resistive feedback topology.

Fig. 3. Proposed LNA architecture.

Fig. 4. Equivalent input matching network of the proposed LNA.

A. Principle of Operation

Fig. 3 shows the schematic of the proposed LNA. Thegoal is to adopt the advantages of L-CSLNA and RFLNA.Its equivalent circuit for input matching analysis is shownin Fig. 4. Since the original resistive feedback LNA has aparallel input network, the input network can be simplifiedto the left figure of Fig. 4. If the frequency band of interestis relatively narrow, a parallel-to-series impedance conver-sion can be applied to the input matching network. To useseries matching for the resistive feedback topology, the inputimpedance at the gate of is converted into a series net-work, as shown in the right figure of Fig. 4, using series

and , where is , is

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS 3021

Fig. 5. Small-signal model of the � -boosted resistive feedback LNA for noise analysis.

, is the impedanceof the output load at the operating frequency, and

is for the frequency band of interest.The impedance can be easily matched to the source by set-

ting to the source impedance , and adding a series in-ductor that resonates with at the operating frequency. Theseries matching topology boosts the voltage at the gate of by

, and hence the effective transconductance is boostedby . Theoretically, the proposed LNA can achievea higher voltage gain compared to an inductively degeneratedLNA by a factor of . A small-signal analysisof the input impedance shows that

(1)

is equal to at theresonance frequency .

In the proposed LNA, the inductor at the source of is re-moved compared with the L-CSLNA. Removing the source in-ductor not only reduces the chip area but also gives other bene-fits. Typical of an integrated inductor is in the range of 5–20[24]. As the target NF approaches 1 dB, the parasitics, such asinductor series resistance, substrate resistance and ESD devices,start to dominate the LNA noise performance. Because the realand imaginary terms in (1) are dependent on , , , ,and , the topology provides more freedom for the choice ofthe single inductor whose quality factor is crucial for highnoise performance design.

B. Noise Analysis

The small-signal model of Fig. 5 is employed to perform thenoise analysis. The gate resistance of the input transistor, isignored with the assumption that the gate impedance is mainlycapacitive, and the DC blocking capacitor in the feedback path isshorted since it has a small impedance at the desired frequency.

is the loss of the gate inductor . The noise contributionof the cascode transistor, is neglected due to the noise can-cellation mechanism of the cascode transistor when the outputimpedance of the input device is much higher than the inverseof the transconductance of the cascode transistor. is the load

impedance when and resonate at the frequency of in-terest.

The noise factor of the proposed topology is

(2)

where is the ratio between the device transconductance andthe zero-bias drain conductance, is the factor of channelthermal noise, is the factor of induced gate noise, and isthe correlation coefficient between the induced gate noise andthe drain noise. For long channel devices, , ,

, and [1], [25]. In (2), there are three mainnoise contribution terms originating from the active device. Thefourth term comes from the drain current noise and the fifthrepresents the correlated portion of the drain current noise andthe induced gate noise. The last term is the contribution of theuncorrelated induced gate noise.

The relation thatequals for the narrowband LNA inFig. 3 under the input matching condition can be ap-plied to (2). When , it can be assumed that

. Then, the noise factor as afunction of can be expressed by

(3)

To optimize the NF for a given specification and power condi-tion, all design parameters need to be represented by one designvalue. This is discussed in Appendix. After applying the NF op-timization for a fixed power condition [1], the minimum NF andoptimum factor are given by

(4)


and

(5)

Assuming , , and for a shortchannel device [1] and , , (4) and (5)become

(6)

(7)

C. Comparison of Noise Performance

The following noise analysis assumes that all LNA topolo-gies have matched input impedances. Also, the noise from pas-sive devices, loads, and the cascode transistor are neglected tosimplify the noise factor and focus on the noise contribution ofthe drain and induced gate noises of the input device.

In [1], the optimum NF of the L-CSLNA for a fixed powercondition is given as

(8)

which was corrected later as follows [2]:

(9)

This optimal NF shows a smaller noise factor compared to (4).The reason for this difference can be explained by comparingthe NF expressions before optimization. The NF expression ofthe L-CSLNA using the factor is stated as

(10)

which neglects the noise contribution from the loss of induc-tors. In (10), the second, third, and last terms are the noise con-tribution of the drain current noise, the correlation portion be-tween the drain and the induced gate noises, and the uncor-related induced gate noise, respectively. The correlation termhas negative sign which cancels a portion of noise factor of theL-CSLNA. However, the correlated part between the drain noiseand the induced gate noise for the proposed LNA has a positivesign and thus increases the NF. The effect of the noise cancel-lation by the correlated portion between the drain and the in-duced gate noises is also crucial in the comparison of (8) with(9), because the former is the optimized NF when the correlatedportion set a false positive sign. For this reason, the inductivelydegenerated common-source topology shows better noise per-formance for the optimum design condition, theoretically. The

optimum design condition assumes no power and area limita-tions, as well as use of ideal passive devices and no parasitics.Indeed, the achievable minimum noise figure of each topologyis determined by many other factors such as specifications, ap-plications, frequency of interest, and technology.

The noise factor of the resistive feedback LNA in Fig. 2(b) isderived as

(11)

As (11) implies, the NF can be improved by burning morepower.

It can be shown that the noise factor of the CGLNA inFig. 2(a) is given by

(12)

Interestingly, the noise expressions of the the CGLNA andRFLNA seem very similar but have one big difference. Be-cause the input matching condition of the CGLNA is thatequals to , the noise factors of the CGLNA and RFLNAbecome exactly same when the RFLNA has the condition that

. It is possible to improve the noise factor of theCGLNA by drawing more current in the input device or having

larger than one, which increases the transconductance ofthe input device [3].

Fig. 6 shows the theoretically analyzed NF plots of variousLNA topologies. Plots of the L-CSLNA and the proposed LNAare minimum NFs for fixed power condition. The CGLNAis not optimized for a fixed power condition since its inputmatching condition determines its transconductance (or )and its minimum NF. The minimum NF without a fixed powerlimitation is used for the RFLNA by the same reason as theCGLNA, and is assumed to be 30 mA/V. A comparison ismade for the short channel model ( , , )including the drain current noise, the induced gate noise and thecorrelation between them. It is observed that the CGLNA andRFLNA that have a shunt input network exhibit less frequencydependency and high NF at low frequencies because of thedominant constant term in the NF equation. On the other hand,the L-CSLNA and the proposed LNA that use the series RLCinput network show strong frequency dependency and a lowNF at low frequencies. For the analysis excluding the parasiticsof the passive components, the NF of the proposed LNA iscomparable to that of the L-CSLNA and lower than that of theCGLNA or RFLNA at most practical operating frequencies.Since the NF of the L-CSLNA deviates from the theoreticalminimum value because of the parasitics of inductors for typicalapplications where [23], the proposed topologythat requires only one inductor at the gate provides a significantadvantage for NF optimization including passive parasitics.Due to the intrinsically higher NF of the CGLNA and RFLNA,


Fig. 6. Comparison of noise figure versus normalized unity gain frequency�� for different LNA topologies such as inductively degenerated LNA(L-CSLNA[1] for (8), L-CSLNA[2] for (9)), proposed LNA, common-gate LNA(CGLNA), and resistive feedback LNA (RFLNA). � � ��, � � ��,� � �, and � � �� mA� (for RFLNA).

those topologies have been modified and combined in realapplications.

A literature survey has been performed to compare re-cently reported CMOS LNAs for narrowband and widebandapplications in Fig. 7. The LNAs are categorized into threefundamental topologies (common gate (CG), inductivelydegenerated common-source (L-CS), and resistive feedback(RF)) and others. CGLNAs [12]–[22], [26]–[28] include noisecanceling CG using a common-source amplifier or transformer,

-boosted CG, and so on. L-CSLNAs [8]–[11], [28]–[38]include typical inductively degenerated LNAs, wideband inputmatching LC filter merged LNA, and bandwidth extendedresistive feedback L-CSLNA. RFLNAs [4], [39]–[45] consistof mainly wideband LNAs with resistive feedback. Finally,the others [5], [6], [46]–[54] include NMOS shunt feedbackLNAs, distributed LNAs, reactive feedback LNAs, and trans-former based LNAs. Fig. 7 clearly shows that most of the L-CStopologies have NFs lower than 3 dB, but RF, CG and otherschemes have higher noise figures. As expected from the NFexpressions, the CG and RF architectures have similar NFdistributions, and the noise performances of both LNAs aremainly determined by the power consumption of the input de-vices. Many L-CSLNAs have NFs lower than 2 dB. This figureshows that recently reported measurement data agrees withthe theoretical noise performance analysis of Fig. 6, althoughmeasured data shows a smaller NF gap between the L-CSLNAand RF/CGLNA topologies than the theoretical analysis.

D. Sensitivity to Process and Temperature Variations

The reliability of LNAs over process and temperaturechanges is one of the main design considerations. In thissubsection, the proposed LNA performance has been sim-ulated for different process corners and temperatures at 2.4GHz. Table I lists five corner simulation results at 27 forthe fully integrated LNA whose design details are describedin Section IV. Though S21 is highly dependent on processcorners, the LNA maintains an S11 less than dB, and thevariation of NF is less than 0.6 dB. The main reasons for thelarge variation of S21 shown in Table I are the variation of the

Fig. 7. Comparison of the literature’s noise figure over frequencies normal-ized to unity gain frequency for different LNA topologies: inductively degener-ated LNA (L-CS), common-gate LNA (CG), resistive feedback LNA (RF), andothers. The markers with black filling represent narrowband LNAs, while whitefilings represent wideband LNAs.

TABLE ICORNER SIMULATION FOR THE FULLY INTEGRATED LNA OF FIG. 8(A)

TABLE IISIMULATED VARIATION OVER TEMPERATURE FOR THE FULLY INTEGRATED

LNA OF FIG. 8(A)

input device transconductance and the detuning of the LCload due to the changes in parasitics. The simulated gain andnoise figure variations over a temperature range of to100 are smaller than 1.3 dB and 0.8 dB, respectively whilekeeping dB as shown in Table II. This is becauseof the voltage gain in front of the transistor in the input stage.Equation (3) implies that if the voltage gain is stable for typicalapplications , the overall noise figure becomesless sensitive to the variation of the transistor. These simulationresults show that the variation of noise performance of the LNAdue to process and temperature variation is not significant, andthe proposed LNA is able to operate as the first active block todeliver required noise and gain performance for the followingblocks.

IV. LNA IMPLEMENTATION

To demonstrate the performance of the proposed LNA, twodifferent versions, a fully integrated LNA and an LNA with


Fig. 8. Complete schematics of (a) fully integrated LNA, and (b) LNA having off-chip matching network.

off-chip input matching network, have been designed and fabri-cated in a standard 8 metal 0.13- m RF CMOS technology for2.4 GHz operation. The complete schematics of the LNAs areshown in Fig. 8. Both amplifiers have a two-stage cascaded ar-chitecture of a core amplifier and an open-drain output buffer.The core amplifier has cascode configuration to improve the re-verse isolation and reduce the Miller capacitance between thegate and drain of the input device, . The size of is 200

m/0.13 m which gives minimum NF, when the transistor isbiased at 2 mA with a 1.2 V supply.

The NMOS, and PMOS, which have thicker gateoxide than normal transistors for higher threshold and break-down voltages, are added to protect the gate of the input de-vice from electro-static discharge (ESD) [55]. The ESD pro-tection devices increase the noise figure by 0.1 dB due to theparasitic capacitance and the finite output resistance. The gateinductance, or is 8.8 nH. The feed-back resistance, is 8.4 and the load inductance, is8 nH. The quality factor of the on-chip spiral inductor, and

is around 10 at 2.4 GHz. It is assumed that the factor ofthe bondwire inductor, and the surface mounted ex-ternal inductor, are 30 and 60 respectively in the LNAsimulation. Except for the ESD protection transistors, the LNAhas been designed using standard transistors, metal-insu-lator-metal (MIM) capacitors, and standard spiral inductors. Inthe simulation, the LNA with off-chip matching network showsan NF of 0.9 dB, while the NF of the fully integrated LNA is1.9 dB. Since both LNAs have the same design besides the gateinductor, the NF simulation results assure the importance of thequality of passive components for high noise performance de-sign. The second stage of the LNA is an open-drain structure to

Fig. 9. Chip photograph of (a) fully integrated LNA, and (b) LNA with off-chipmatching network.

utilize the entire output signal current and use the test equipmentas a load. The load of the first stage is tuned to 2.4 GHz using

and the total capacitance of , the input capacitance of thesecond stage, and the parasitic capacitance of the output node.The voltage gain of the output buffer is about 3.5 dB when it isconnected to a 50 load.

Fig. 9 shows the chip microphoto of the proposed LNAs.The chip sizes including pads and bypass capacitors are 900

m 670 m and 850 m 680 m for the fully integratedLNA and the off-chip matched LNA, respectively. 100 pF by-pass capacitors are integrated between the power supply andground for a better ac ground. The ground of all MIM capacitorsis shielded to minimize noise injection from the substrate andevery transistor is protected by double guard rings including an


Fig. 10. Measured S parameters of the LNA for the fully integrated and off-chipmatching (partially integrated) version. (a) S11 and S22, and (b) S21 and S12.

Nwell ring. The noise of the substrate is also reduced by puttingmany substrate contacts between wide ground metal and thesubstrate. The two designs were fabricated in different batches.

V. EXPERIMENTAL RESULTS AND DISCUSSION

On-wafer measurement has been performed for the fullyintegrated LNA of Fig. 9(a). For the LNA using an off-chipmatching network, a PCB has been fabricated using a low lossRF substrate. For the NF measurement, the off-chip matchingLNA was tested inside of a shielding case to prevent interfer-ence from ambient interferers.

Fig. 10 shows the measured scattering (S) parameters. Themeasured input reflection coefficients, S11s of the fully inte-grated LNA and the LNA with off-chip matching network are

dB and dB, while the gains (S21) are 28.3 dB and32.0 dB at 2.4 GHz, respectively. The measured and simulatedNFs are plotted in Fig. 11, and they show good agreement at thetarget frequency. The measured NF of the LNA with an off-chipinductor is 1.2 dB, while that of the fully integrated LNA is 2.0dB. As anticipated, the LNA with a high off-chip gate in-ductor attains 0.8 dB better NF than the fully integrated one.The measured performances of the two versions of the proposedLNA are compared with those of reported LNAs of different

Fig. 11. Measured and simulated NF of the LNA for the fully integrated (FI)and off-chip matching (PI) version.

Fig. 12. Linearity of the fully integrated LNA. (a) Simulated IIP3 of the LNAcore, and (b) simulated and measured IIP3 of the LNA with the output buffer.

topologies as shown in Fig. 7, and they demonstrate that the re-sistive feedback topology using series RLC matching overcomesthe theoretical limits of the RFLNA that uses a shunt input net-work.

The simulated and measured results of two-tone tests using2.395 GHz and 2.4 GHz inputs show good agreement as shownin Fig. 12(b) for the fully integrated version. The measuredinput-referred third-order intercept point (IIP3) including thebuffer is dBm and the measured 1-dB compression pointis dBm. The linearity of the overall LNA is limited by


Fig. 13. Measured and simulated � factors of the fully integrated LNA.

the open-drain buffer stage introduced for testing purposes.The simulated IIP3 of the LNA core is dBm as shown inFig. 12(a).

The measured and simulated factors of the fully integratedLNA are shown in Fig. 13. These stability factors are calcu-lated using the measured and simulated S parameters. Due tothe open-drain output buffer, the measured factor is less than1 from 1.4 GHz to 2.1 GHz. Fig. 14 shows the measured sourceand load stability circles of the fully integrated LNA from 0.5 to2.2 GHz. The source and load stability circles stay away fromthe center of the smith chart and demonstrate that the LNA isstable for the intended operation with 50 source and loadimpedances. Furthermore, the simulation using an impedance-matched output buffer shows a factor larger than 6 up to 10GHz, which ensures unconditional stability in this frequencyrange. It should be noted that the stability of LNAs is essentiallydetermined by the reverse isolation of the input and output whenboth terminals are matched. The negative feedback path of thecore LNA also helps to stabilize the LNA.

The LNA core and the buffer for the fully integrated LNAdraw only 2.2 mA and 1.8 mA respectively from a 1.2 V powersupply. Table III shows a performance summary and compar-ison with previous works. To compare the performance of theLNAs, the figure of merits (FOM1 and FOM2) defined in [28]are used. The FOM1 is a function of the operating frequency,gain, noise factor, and power consumption, and is given by

(13)

FOM2 includes IIP3 and is given by

(14)

The proposed work shows the best FOM1 and excellentFOM2. The theoretical analysis and experimental resultsdemonstrate the effectiveness of the proposed topology interms of gain, noise and power.

Fig. 14. Measured stability circles of the fully integrated LNA. (a) Source sta-bility circles, and (b) load stability circles.

VI. CONCLUSION

We have presented a -boosted resistive feedback LNAusing a series RLC matching network at 2.4 GHz. The proposedLNA achieves easy and reliable input matching, low NF, andhigh gain at the same time. The complete noise analysis forthe proposed LNA is performed and its optimal NF is com-pared with CGLNA, RFLNA, and L-CSLNA topologies. It isconfirmed that the theoretical minimum NF of each topologyhas good agreement with those of the fabricated LNAs by asurvey. Even though the inductively degenerated LNA showsthe best theoretical noise performance at the same normalizedoperation frequency assuming ideal passive components, theproposed topology is a promising candidate for a narrowbandLNA considering all design parameters including area, power,degree of design freedom, and limited quality of passive com-ponents. A fully integrtated and an off-chip matching versionsof the proposed LNA have been fabricated, and they achievean NF of 2.0 dB and 1.2 dB, S21 of 24 dB and 29 dB, whileproviding an S11 of dB and dB, respectively. Thetest results demonstrate the advantages of the proposed schemeand achieve the best figure of merit.


TABLE IIILNA PERFORMANCE SUMMARY & COMPARISON

APPENDIX

The minimum noise factor of the proposed LNA can be foundusing (3). First of all, needs to be expressed by the physicalparameters. Since ,

in Fig. 3, the quality factor, is given by

(A-1)

where

is . For simplicity, by applying the ap-proximation to (A-1), whenis much larger than 1, we get and

from [1]. Shaeffer [1] has definedthat , is the power consumption ofthe amplifier, and , whereis the saturation velocity, and is the velocity saturationfield strength.

The factor can be rewritten using physical technologicalparameters and design specifications, under the assumption that

, by

(A-2)

where is the ratio of and . For 0.13- m CMOSwith a 1.2 V supply, , mW,(for typical LNA designs), and K is less than 0.01. Thus, (1-K)can be considered as a constant term to simplify the followingderivation.

On the other hand, can be rewritten as. Applying above equality to (3) with the input

impedance matching condition, the noise factor can be ex-pressed as

(A-3)

To simplify the optimization procedure of the noise factor, wehave neglected the contribution of the inductor loss, to thenoise factor. By substituting (A-2) and [1, (39)] into (A-3), thenoise factor is expressed in terms of the relative gate overdrive,

, , and , by

(A-4)

(A-5)

This equation is minimized for a fixed when

(A-6)

The solution of the equation is given by

(A-7)


under the assumptions that and . By inserting(A-7) to (A-2), an optimum for a fixed power condition isachieved by

(A-8)Finally, the minimum NF for a fixed power condition can beevaluated using (A-8), which is given in (4).

ACKNOWLEDGMENT

The authors would like to thank the Electronics and Telecom-munications Research Institute for the chip fabrication.

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Sanghoon Joo (S’08) received the B.S. degree fromKorea University, Korea, in 2003. He is currently pur-suing the Ph.D. degree in electrical and computer en-gineering at Purdue University, West Lafayette, IN.

His research interests include RF circuit design forwireless communication in CMOS and bipolar pro-cesses.

Mr. Joo was the first place winner in Phase Oneand Phase Two of the 2007–2008 SRC/SIA IC De-sign Challenge.

Tae-Young Choi (S’02–M’09) received the B.S.degree in electrical engineering from Seoul NationalUniversity, Seoul, Korea, in 1999, and the M.S. andPh.D. degrees in electrical engineering from theUniversity of Michigan at Ann Arbor in 2002 and2007, respectively.

He is currently a post-doc at Purdue University,West Lafayette, IN. His research interests are in RFintegrated circuits for wireless applications.

Byunghoo Jung (S’00–M’05) received the B.S.degree from Yonsei University, Korea, in 1990, theM.S. degree from KAIST, Korea, in 1992, and thePh.D. degree from the University of Minnesota,Twin Cities, in 2005.

From 1992 to 1999, he was with Samsung Elec-tronics, Korea, where he was involved in the designof video signal driver circuits for flat panel displays.After receiving his Ph.D. in January 2005, he waswith Qualcomm in San Diego, CA, as a Senior RFIC Design Engineer until he joined the School of

Electrical and Computer Engineering at Purdue University, West Lafayette,IN, as an Assistant Professor in August 2005. His research interests includehigh-speed analog/RF circuit design for wireless and wired communicationsand bio-telemetry systems. He holds 10 U.S. patents

Dr. Jung is the first place winner of the 2002–2003 SRC SiGe BiCMOSDesign Challenge (as a lead designer) and the 2007–2008 SRC/SIA IC De-sign Challenge (as a lead faculty). He has been serving as a Co-Chair of theDAC/ISSCC Student Design Contest (SDC) since October 2006, as an Asso-ciate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since January 2009,and as a member of the Analog Signal Processing Technical Program Committee(ASPTPC) in the IEEE Circuits and Systems Society since May 2006.

a 2.4-ghz resistive feedback lna

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