a 5 to 31 ghz four-phase mixer-first receiver - dtic
TRANSCRIPT
Paper Title (use style: paper title)A 5 to 31 GHz Four-Phase
Mixer-First Receiver Sandeep Hari, Avinash Bhat, Charley Wilson,
and Brian Floyd
North Carolina State University Raleigh, NC 27695-7911
Email: [email protected]; [email protected]
Abstract—A 5 to 31 GHz mixer-first receiver implemented in 45 nm SOI CMOS is presented. The receiver employs four-phase passive mixing, enabling tunable input matching up to 31 GHz through a digitally-tuned baseband. Broadband local oscillator signals are provided through a 2:1 frequency divider. The receiver achieves an 8 dB noise figure, >20 dB conversion gain, and -17 dBm in-band input 1 dB compression point, while consuming 164 mW at 5 GHz, increasing to 300 mW at 31 GHz.
Keywords—passive mixer; receiver; N-path; direct-conversion
I. INTRODUCTION
Mixer-first direct-conversion receivers enable frequency- selective downconversion over wide local-oscillator (LO) and radio frequency (RF) ranges. Also, a mixer-first receiver employing passive mixers enables tuning of the input impedance using tunable feedback resistors within the baseband network. These properties have been demonstrated at lower frequencies [1] and more recently at 20-30 GHz [2]. Operation up to millimeter-wave (mm-wave) frequencies is however limited by circuit parasitics and broadband LO signal generation. In this work, we present design techniques to mitigate these concerns and demonstrate a receiver which operates across 5 to 31 GHz. Such a receiver can serve as a reusable intellectual property (IP) downconversion core for RF/mm-wave radio and phased-array systems. Also, the circuit can be used within wideband, frequency-selective digital beamforming receiver arrays.
II. CIRCUIT DESCRIPTION
A block diagram and die micrograph of the receiver are shown in Fig. 1. The receiver is implemented in GlobalFoundries 45 nm RFSOI technology. A passive four- phase mixer is driven with non-overlapping 25% duty-cycle LO signals. Each mixer switch is realized with 15.6 µm wide floating-body transistors, providing an on-resistance of ~19 and. Four phases are used as opposed to six or eight to minimize the challenges associated with LO generation and the input parasitic capacitance, both to be discussed shortly.
Input impedance matching for wideband receivers can be challenging. In our design, a 200 pH series inductor (Lin) and a short transmission line are included on the RF input to compensate for the mixer shunt capacitance at high frequencies. Ignoring the input transmission line and assuming an ideal inductor, the input impedance can be expressed as [1]-[3]
( ) ( ){ } ( )1 IN in SW N BB o SH o
in
ω ω γ ω ω ω ω
= + + − (1)
where RSW is the switch on-resistance, ZBB is the tunable baseband termination impedance which is upconverted to RF,
represents the “round-trip” conversion loss of the mixer, Cin is the parasitic capacitance of the mixer, and ZSH models signal loss due to harmonic re-radiation. For a four-phase mixer, ZSH is related to the following [1]:
( ) ( ) ( ) ( )* *9 3 25 5 49 7 ...SH o BACK o BACK o BACK oZ Z Z Zω ω ω ω∝ (2)
where ZBACK is the impedance looking back from the baseband through the switch towards the RF input source, equal to
( ) ( )1 BACK SW src in
in
ω ω ω ω
= + + (3)
The harmonic impedances appear in parallel, indicating that RF power is being delivered back to the input at harmonics of the LO. Note that the presence of Cin tends to short out the source impedance at high harmonics; thus, ZBACK approaches RSW for high-order harmonics, as discussed in [3]. Also, as the LO frequency becomes larger, this “shorting out” effect occurs for earlier harmonics and thus, ZSH reduces. This reduction to ZSH is one limitation in operating mixer-first receivers at very high frequencies, reducing the overall input impedance tuning range.
Nevertheless, a proper match can be provided around the LO frequency across the full LO tuning range through baseband tuning of the termination impedance provided by the mixer across frequency. For example, at 5 GHz, the receiver input impedance is primarily that of the mixer which is tuned to achieve a matched condition. Components Cin and Lin have minimal effect. However, at 31 GHz, the mixer input impedance is tuned to achieve a higher input impedance which is then transformed down to 50 through the shunt-Cin, series-Lin matching network. Note that the input series inductor compensates for the input capacitance at the fundamental frequency; however, it does not counteract the effects of shunt capacitance at harmonics of the LO [3], as discussed above.
Another key challenge in wideband receiver design is LO generation. In [2], quadrature LO signals were generated using a passive polyphaser filter. This has the benefit of not consuming power and allowing for increasing the amplitude swing of the input LO signal at the upper end of the frequency range to improve noise figure and conversion gain. However, the polyphase filter limited the frequency range to 20-30 GHz. In this work, the quadrature LO signals are generated using a wideband current-mode logic (CML) divide-by-two (2:1) frequency divider driven with a double-frequency clock signal (2XLO), as shown in Fig. 2(a). In our prototype, we do not integrate a frequency multiplier; however, in a real system, a multiplier could be used to generate the upper range of LO signals and avoid the need for off-chip generation of multi- octave (i.e., 10-62 GHz) clock signals.
DISTRIBUTION STATEMENT A. Approved for public release: distribution is unlimited.
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The 2:1 frequency divider has been optimized to provide wideband performance at moderate power consumption. A transformer is used at the clock input to generate differential signals for the divider. Fig. 2(b) shows a schematic of the latch used within the device. Inductive peaking (100 pH) is used to increase the maximum clock frequency to 62 GHz, although this
comes at the cost of increasing the lowest frequency to 10 GHz. The simulated self-oscillation frequency of the divider is designed for 26 GHz, meaning the input sensitivity for the divider is minimum at 52 GHz.
Non-overlapping clock signals are created using four parallel transmission gates, as shown in Fig. 2(a). These transmission gates generate non-overlapping “pulse trains” by “ANDing” a given 50% duty cycle signal with an adjacent signal which is shifted by 90o [2]. These signals theoretically overlap by a quarter period. Rise time is however limited by the strength of the buffers and the mixer capacitive load. In our design, we target a rise time much less than a quarter of a 30 GHz period, meaning rise time must be less than 4 ps. This is another aspect of the design which relies on the high performance of the 45 nm SOI CMOS technology. Our rise time target requires the insertion of strong buffers between the divider output and the transmission gates. These buffers are designed to have output impedances of <10 ; hence, buffer power consumption is high. Total power consumption of the LO network is between 86 and 230 mW for 5 to 31 GHz output signals, respectively. This represents the largest power consumption for the receiver.
A schematic of the baseband amplifiers is shown in Fig. 3. A complimentary differential topology is used to increase transconductance and reduce noise. Common-mode feedback is provided using a buffered resistor averaging network, an error amplifier, and then a PMOS follower (Mcmfb). Simulated open- loop gain of the amplifier is 16 dB whereas simulated input- referred noise is 0.6 nV/√(Hz). Linearity of the overall receiver is limited by these baseband amplifiers. The target baseband bandwidth is 500 MHz, set by the total capacitance at the baseband input nodes. This includes the shunt sampling capacitance (Cbb) as well as a negative Miller capacitance, connected using positive feedback around the baseband amplifier using Cn. The negative capacitor allow us to increase overall baseband bandwidth. Each differential baseband chain consumes 38 mW from 1.8 V. Following the baseband amplifiers, broadband output test buffers for driving external 50 test equipment are included. Their power consumption is not included in the overall summary.
Fig. 1 (a) Block diagram and (b) block diagram of mixer-first receiver. Die size is 1.6 x 1.1mm2.
(a) (b)
Input match
Baseband Amps
LO Network
Fig. 2 (a) Block diagram of LO network and (b) simplified schematic of the divider latch.
270°
0°
90°
180°
180°
180°
0°
270°
90°
270°
Divider
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Each baseband amplifier is configured as a transimpedance amplifier (TIA) with programmable feedback resistors. As introduced in [1], intra-phase and inter-phase feedback are used to synthesize real and imaginary RF input impedance, although the presence of the input shunt capacitance reduces the maximum achievable impedance [2], [3] as already mentioned. Here, our intra-/inter-phase feedback resistors can be switched from 0.8 to 60 k. Each tunable resistor is realized as selectable logarithmically-spaced arrays. With these feedback resistors, conversion gains of 12 to 22 dB are realizable for the entire receiver across the band.
III. MEASUREMENT RESULTS The receiver chip was mounted on a printed circuit board
(PCB) with all inputs and outputs aside from the RF and 2XLO clock input wire bonded to the board. The RF and 2XLO ports were probed. To simplify testing, PCB-based transformers are used at the baseband I and Q outputs to convert from differential to single-ended. Total power consumption excluding output buffers is 164 mW at 5 GHz, increasing to ~300 mW at 31 GHz.
Fig. 4 shows the measured frequency-selective conversion gain and double-sideband noise figure (NF), where the LO
frequency is stepped from 5 to 31 GHz and then the RF is swept by ±600 MHz around the LO. Across 6-27 GHz, peak gain is 20-22 dB and NF is <8 dB. Measured gain, NF, and input one- dB compression point (iP1dB) at 25 GHz versus feedback resistance are shown in Fig. 5. The iP1dB is -20 dBm at maximum gain and -9 dBm at minimum gain. Output compression is roughly constant, limited by the output swing in the baseband TIA and output buffers.
Fig. 6 shows the blocker compression point and gain at 25 GHz for different resistor settings. Blocker compression point (B1dB) is the blocker power at which gain of the desired RF signal reduces by 1dB and is plotted by sweeping the blocker power at different RF frequencies around the LO while measuring the gain of desired RF signal at a fixed 20MHz offset from the LO. Outside the bandwidth of the receiver, B1dB flattens out since the impedance seen by RF port is just RSW. Fig. 7, also shows the channel bandwidth varying from 230 MHz to 600 MHz for high-gain and low-gain settings. The receiver achieves an in-band IIP3 above -10 dBm and in-band IIP2 above +7dBm at the highest gain setting.
Fig. 7 shows the measured S11 of the receiver at 6, 18, 24, and 30 GHz LO on a Smith chart. These are measured for all possible intra-/inter-resistor feedback values for a ±500 MHz RF sweep, with the asterisk markers indicating match at LO frequency and shaded region indicating 10 dB return loss. Note
Fig. 5 Measured conversion gain, noise figure, and iP1dB vs. feedback resistor setting at LO frequency of 25 GHz.
Fig. 6 Measured blocker compression (B1dB) and gain across RF frequency at an LO frequency of 25 GHz for three different feedback resistor settings.
Mtail
- out +
Fig. 3 Schematic of the baseband amplifier.
Fig. 4 Measured NF versus LO frequency at both high-gain and low-gain settings. Representative swept-RF conversion-gain curves included for different LO frequencies.
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that the overall trend of this locus of points is first a clockwise rotation due to the presence of the input LC network and the input transmission line. Second, the locus shrinks in its radius due to the reduction of Zsh at high frequencies, as discussed in section II. Nevertheless, these results indicate that a proper input match can be achieved across the full band. Furthermore, an impedance tuning range of between 2:1 to 3:1 can be achieved, useful for compensating package effects. As evident, a redesign of the receiver could target reduced input impedances to allow improved S11 at the lower end of the frequency range.
IV. CONCLUSIONS This work has demonstrated a wideband, frequency-
selective mixer-first receiver in 45 nm RFSOI technology. It can operate over a 6:1 LO tuning range (5-31 GHz) while maintaining consistent conversion gain, linearity, NF, and input matching. Table 1 compares our measured results in high-gain mode to prior art. Our mixer-first receiver provides wider frequency range, higher linearity, and slightly worse NF at increased power consumption compared to amplifier-first receivers. To our knowledge, this represents the highest and broadest frequency range for a mixer-first direct-conversion receiver using passive mixers with non-overlapping clocks. This mixer-first receiver may be a suitable candidate for both reusable IP downconversion cores and potentially digital beamformers. Future work includes the investigation into novel approaches for low-power LO network and techniques for lower noise figure and higher linearity for millimeter-wave N-path.
TABLE I. PERFORMANCE SUMMARY AND COMPARISONS
Ref. Freq. (GHz)
Pwr. (mW) Tech.a, Topology
This 5-31 22 8 -17 <300 45-SOI, mix-first [2] 20-30 20.6 8 -13 41 45-SOI, mix-first [4] 0.3-12 3 to 5 12.7 -10 1200 130-BC, mix-first [5] 28 33 5.7 -30 53 65-CM, amp-first [6] 24 30 5.6 -36.5 22 180-CM, amp-first
ACKNOWLEDGMENTS This material is based on research sponsored by AFRL and
DARPA, under agreement FA8650-16-1-7629. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements of AFRL, DARPA, or the U.S. Government.
REFERENCES [1] C. Andrews and A. C. Molnar, “Implications of passive mixer
transparency for impedance matching and noise figure in passive mixer- first receivers,” IEEE Trans. Circuits and Sys. I: Regular Papers, vol. 57, no. 12, pp. 3092-3103, Dec. 2010.
[2] C. Wilson and B. A. Floyd, “A 20-30 GHz mixer-first receiver in 45-nm SOI CMOS,” IEEE RF Integrated Cicrcuits Symp., 2016, pp. 344-347.
[3] D. Yang, C. Andrews, and A. Molnar, “Optimized design of N-phase passive mixer-first receivers in wideband operation,” IEEE Trans. Circuits and Sys. I: Regular Papers, vol. 62, no. 11, pp. 2759-2770, Nov. 2015.
[4] R. Ying, M. Morton and A. Molnar, "A HBT-based 300 MHz-12 GHz blocker-tolerant mixer-first receiver," IEEE European Solid-State Circuits Conf., 2017, pp. 31-34
[5] S. Mondal, R. Singh and J. Paramesh, " A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation, " IEEE International Solid - State Circuits Conference, 2018, pp. 72-74.
[6] N. Shiramizu, T. Nakamura, T. Masuda, K. Washio, “A 24-GHz low- power fully integrated receiver with image-rejection using rich- transformer direct-stacked/coupled technique,” IEEE RFIC Symp., May 2010, pp. 369-372.
a. Unit given in nm, SOI=SOI CMOS, BC=SiGe BiCMOS, CM=Bulk CMOS
(a) LO=6 GHz (b) LO=18 GHz (c) LO= 24 GHz (d) LO=30 GHz
Fig. 7 Measured S11 of the receiver at (a) 6, (b) 18, (c) 24, and (d) 30 GHz for all possible feedback resistor settings.
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North Carolina State University Raleigh, NC 27695-7911
Email: [email protected]; [email protected]
Abstract—A 5 to 31 GHz mixer-first receiver implemented in 45 nm SOI CMOS is presented. The receiver employs four-phase passive mixing, enabling tunable input matching up to 31 GHz through a digitally-tuned baseband. Broadband local oscillator signals are provided through a 2:1 frequency divider. The receiver achieves an 8 dB noise figure, >20 dB conversion gain, and -17 dBm in-band input 1 dB compression point, while consuming 164 mW at 5 GHz, increasing to 300 mW at 31 GHz.
Keywords—passive mixer; receiver; N-path; direct-conversion
I. INTRODUCTION
Mixer-first direct-conversion receivers enable frequency- selective downconversion over wide local-oscillator (LO) and radio frequency (RF) ranges. Also, a mixer-first receiver employing passive mixers enables tuning of the input impedance using tunable feedback resistors within the baseband network. These properties have been demonstrated at lower frequencies [1] and more recently at 20-30 GHz [2]. Operation up to millimeter-wave (mm-wave) frequencies is however limited by circuit parasitics and broadband LO signal generation. In this work, we present design techniques to mitigate these concerns and demonstrate a receiver which operates across 5 to 31 GHz. Such a receiver can serve as a reusable intellectual property (IP) downconversion core for RF/mm-wave radio and phased-array systems. Also, the circuit can be used within wideband, frequency-selective digital beamforming receiver arrays.
II. CIRCUIT DESCRIPTION
A block diagram and die micrograph of the receiver are shown in Fig. 1. The receiver is implemented in GlobalFoundries 45 nm RFSOI technology. A passive four- phase mixer is driven with non-overlapping 25% duty-cycle LO signals. Each mixer switch is realized with 15.6 µm wide floating-body transistors, providing an on-resistance of ~19 and. Four phases are used as opposed to six or eight to minimize the challenges associated with LO generation and the input parasitic capacitance, both to be discussed shortly.
Input impedance matching for wideband receivers can be challenging. In our design, a 200 pH series inductor (Lin) and a short transmission line are included on the RF input to compensate for the mixer shunt capacitance at high frequencies. Ignoring the input transmission line and assuming an ideal inductor, the input impedance can be expressed as [1]-[3]
( ) ( ){ } ( )1 IN in SW N BB o SH o
in
ω ω γ ω ω ω ω
= + + − (1)
where RSW is the switch on-resistance, ZBB is the tunable baseband termination impedance which is upconverted to RF,
represents the “round-trip” conversion loss of the mixer, Cin is the parasitic capacitance of the mixer, and ZSH models signal loss due to harmonic re-radiation. For a four-phase mixer, ZSH is related to the following [1]:
( ) ( ) ( ) ( )* *9 3 25 5 49 7 ...SH o BACK o BACK o BACK oZ Z Z Zω ω ω ω∝ (2)
where ZBACK is the impedance looking back from the baseband through the switch towards the RF input source, equal to
( ) ( )1 BACK SW src in
in
ω ω ω ω
= + + (3)
The harmonic impedances appear in parallel, indicating that RF power is being delivered back to the input at harmonics of the LO. Note that the presence of Cin tends to short out the source impedance at high harmonics; thus, ZBACK approaches RSW for high-order harmonics, as discussed in [3]. Also, as the LO frequency becomes larger, this “shorting out” effect occurs for earlier harmonics and thus, ZSH reduces. This reduction to ZSH is one limitation in operating mixer-first receivers at very high frequencies, reducing the overall input impedance tuning range.
Nevertheless, a proper match can be provided around the LO frequency across the full LO tuning range through baseband tuning of the termination impedance provided by the mixer across frequency. For example, at 5 GHz, the receiver input impedance is primarily that of the mixer which is tuned to achieve a matched condition. Components Cin and Lin have minimal effect. However, at 31 GHz, the mixer input impedance is tuned to achieve a higher input impedance which is then transformed down to 50 through the shunt-Cin, series-Lin matching network. Note that the input series inductor compensates for the input capacitance at the fundamental frequency; however, it does not counteract the effects of shunt capacitance at harmonics of the LO [3], as discussed above.
Another key challenge in wideband receiver design is LO generation. In [2], quadrature LO signals were generated using a passive polyphaser filter. This has the benefit of not consuming power and allowing for increasing the amplitude swing of the input LO signal at the upper end of the frequency range to improve noise figure and conversion gain. However, the polyphase filter limited the frequency range to 20-30 GHz. In this work, the quadrature LO signals are generated using a wideband current-mode logic (CML) divide-by-two (2:1) frequency divider driven with a double-frequency clock signal (2XLO), as shown in Fig. 2(a). In our prototype, we do not integrate a frequency multiplier; however, in a real system, a multiplier could be used to generate the upper range of LO signals and avoid the need for off-chip generation of multi- octave (i.e., 10-62 GHz) clock signals.
DISTRIBUTION STATEMENT A. Approved for public release: distribution is unlimited.
581
The 2:1 frequency divider has been optimized to provide wideband performance at moderate power consumption. A transformer is used at the clock input to generate differential signals for the divider. Fig. 2(b) shows a schematic of the latch used within the device. Inductive peaking (100 pH) is used to increase the maximum clock frequency to 62 GHz, although this
comes at the cost of increasing the lowest frequency to 10 GHz. The simulated self-oscillation frequency of the divider is designed for 26 GHz, meaning the input sensitivity for the divider is minimum at 52 GHz.
Non-overlapping clock signals are created using four parallel transmission gates, as shown in Fig. 2(a). These transmission gates generate non-overlapping “pulse trains” by “ANDing” a given 50% duty cycle signal with an adjacent signal which is shifted by 90o [2]. These signals theoretically overlap by a quarter period. Rise time is however limited by the strength of the buffers and the mixer capacitive load. In our design, we target a rise time much less than a quarter of a 30 GHz period, meaning rise time must be less than 4 ps. This is another aspect of the design which relies on the high performance of the 45 nm SOI CMOS technology. Our rise time target requires the insertion of strong buffers between the divider output and the transmission gates. These buffers are designed to have output impedances of <10 ; hence, buffer power consumption is high. Total power consumption of the LO network is between 86 and 230 mW for 5 to 31 GHz output signals, respectively. This represents the largest power consumption for the receiver.
A schematic of the baseband amplifiers is shown in Fig. 3. A complimentary differential topology is used to increase transconductance and reduce noise. Common-mode feedback is provided using a buffered resistor averaging network, an error amplifier, and then a PMOS follower (Mcmfb). Simulated open- loop gain of the amplifier is 16 dB whereas simulated input- referred noise is 0.6 nV/√(Hz). Linearity of the overall receiver is limited by these baseband amplifiers. The target baseband bandwidth is 500 MHz, set by the total capacitance at the baseband input nodes. This includes the shunt sampling capacitance (Cbb) as well as a negative Miller capacitance, connected using positive feedback around the baseband amplifier using Cn. The negative capacitor allow us to increase overall baseband bandwidth. Each differential baseband chain consumes 38 mW from 1.8 V. Following the baseband amplifiers, broadband output test buffers for driving external 50 test equipment are included. Their power consumption is not included in the overall summary.
Fig. 1 (a) Block diagram and (b) block diagram of mixer-first receiver. Die size is 1.6 x 1.1mm2.
(a) (b)
Input match
Baseband Amps
LO Network
Fig. 2 (a) Block diagram of LO network and (b) simplified schematic of the divider latch.
270°
0°
90°
180°
180°
180°
0°
270°
90°
270°
Divider
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Each baseband amplifier is configured as a transimpedance amplifier (TIA) with programmable feedback resistors. As introduced in [1], intra-phase and inter-phase feedback are used to synthesize real and imaginary RF input impedance, although the presence of the input shunt capacitance reduces the maximum achievable impedance [2], [3] as already mentioned. Here, our intra-/inter-phase feedback resistors can be switched from 0.8 to 60 k. Each tunable resistor is realized as selectable logarithmically-spaced arrays. With these feedback resistors, conversion gains of 12 to 22 dB are realizable for the entire receiver across the band.
III. MEASUREMENT RESULTS The receiver chip was mounted on a printed circuit board
(PCB) with all inputs and outputs aside from the RF and 2XLO clock input wire bonded to the board. The RF and 2XLO ports were probed. To simplify testing, PCB-based transformers are used at the baseband I and Q outputs to convert from differential to single-ended. Total power consumption excluding output buffers is 164 mW at 5 GHz, increasing to ~300 mW at 31 GHz.
Fig. 4 shows the measured frequency-selective conversion gain and double-sideband noise figure (NF), where the LO
frequency is stepped from 5 to 31 GHz and then the RF is swept by ±600 MHz around the LO. Across 6-27 GHz, peak gain is 20-22 dB and NF is <8 dB. Measured gain, NF, and input one- dB compression point (iP1dB) at 25 GHz versus feedback resistance are shown in Fig. 5. The iP1dB is -20 dBm at maximum gain and -9 dBm at minimum gain. Output compression is roughly constant, limited by the output swing in the baseband TIA and output buffers.
Fig. 6 shows the blocker compression point and gain at 25 GHz for different resistor settings. Blocker compression point (B1dB) is the blocker power at which gain of the desired RF signal reduces by 1dB and is plotted by sweeping the blocker power at different RF frequencies around the LO while measuring the gain of desired RF signal at a fixed 20MHz offset from the LO. Outside the bandwidth of the receiver, B1dB flattens out since the impedance seen by RF port is just RSW. Fig. 7, also shows the channel bandwidth varying from 230 MHz to 600 MHz for high-gain and low-gain settings. The receiver achieves an in-band IIP3 above -10 dBm and in-band IIP2 above +7dBm at the highest gain setting.
Fig. 7 shows the measured S11 of the receiver at 6, 18, 24, and 30 GHz LO on a Smith chart. These are measured for all possible intra-/inter-resistor feedback values for a ±500 MHz RF sweep, with the asterisk markers indicating match at LO frequency and shaded region indicating 10 dB return loss. Note
Fig. 5 Measured conversion gain, noise figure, and iP1dB vs. feedback resistor setting at LO frequency of 25 GHz.
Fig. 6 Measured blocker compression (B1dB) and gain across RF frequency at an LO frequency of 25 GHz for three different feedback resistor settings.
Mtail
- out +
Fig. 3 Schematic of the baseband amplifier.
Fig. 4 Measured NF versus LO frequency at both high-gain and low-gain settings. Representative swept-RF conversion-gain curves included for different LO frequencies.
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that the overall trend of this locus of points is first a clockwise rotation due to the presence of the input LC network and the input transmission line. Second, the locus shrinks in its radius due to the reduction of Zsh at high frequencies, as discussed in section II. Nevertheless, these results indicate that a proper input match can be achieved across the full band. Furthermore, an impedance tuning range of between 2:1 to 3:1 can be achieved, useful for compensating package effects. As evident, a redesign of the receiver could target reduced input impedances to allow improved S11 at the lower end of the frequency range.
IV. CONCLUSIONS This work has demonstrated a wideband, frequency-
selective mixer-first receiver in 45 nm RFSOI technology. It can operate over a 6:1 LO tuning range (5-31 GHz) while maintaining consistent conversion gain, linearity, NF, and input matching. Table 1 compares our measured results in high-gain mode to prior art. Our mixer-first receiver provides wider frequency range, higher linearity, and slightly worse NF at increased power consumption compared to amplifier-first receivers. To our knowledge, this represents the highest and broadest frequency range for a mixer-first direct-conversion receiver using passive mixers with non-overlapping clocks. This mixer-first receiver may be a suitable candidate for both reusable IP downconversion cores and potentially digital beamformers. Future work includes the investigation into novel approaches for low-power LO network and techniques for lower noise figure and higher linearity for millimeter-wave N-path.
TABLE I. PERFORMANCE SUMMARY AND COMPARISONS
Ref. Freq. (GHz)
Pwr. (mW) Tech.a, Topology
This 5-31 22 8 -17 <300 45-SOI, mix-first [2] 20-30 20.6 8 -13 41 45-SOI, mix-first [4] 0.3-12 3 to 5 12.7 -10 1200 130-BC, mix-first [5] 28 33 5.7 -30 53 65-CM, amp-first [6] 24 30 5.6 -36.5 22 180-CM, amp-first
ACKNOWLEDGMENTS This material is based on research sponsored by AFRL and
DARPA, under agreement FA8650-16-1-7629. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements of AFRL, DARPA, or the U.S. Government.
REFERENCES [1] C. Andrews and A. C. Molnar, “Implications of passive mixer
transparency for impedance matching and noise figure in passive mixer- first receivers,” IEEE Trans. Circuits and Sys. I: Regular Papers, vol. 57, no. 12, pp. 3092-3103, Dec. 2010.
[2] C. Wilson and B. A. Floyd, “A 20-30 GHz mixer-first receiver in 45-nm SOI CMOS,” IEEE RF Integrated Cicrcuits Symp., 2016, pp. 344-347.
[3] D. Yang, C. Andrews, and A. Molnar, “Optimized design of N-phase passive mixer-first receivers in wideband operation,” IEEE Trans. Circuits and Sys. I: Regular Papers, vol. 62, no. 11, pp. 2759-2770, Nov. 2015.
[4] R. Ying, M. Morton and A. Molnar, "A HBT-based 300 MHz-12 GHz blocker-tolerant mixer-first receiver," IEEE European Solid-State Circuits Conf., 2017, pp. 31-34
[5] S. Mondal, R. Singh and J. Paramesh, " A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation, " IEEE International Solid - State Circuits Conference, 2018, pp. 72-74.
[6] N. Shiramizu, T. Nakamura, T. Masuda, K. Washio, “A 24-GHz low- power fully integrated receiver with image-rejection using rich- transformer direct-stacked/coupled technique,” IEEE RFIC Symp., May 2010, pp. 369-372.
a. Unit given in nm, SOI=SOI CMOS, BC=SiGe BiCMOS, CM=Bulk CMOS
(a) LO=6 GHz (b) LO=18 GHz (c) LO= 24 GHz (d) LO=30 GHz
Fig. 7 Measured S11 of the receiver at (a) 6, (b) 18, (c) 24, and (d) 30 GHz for all possible feedback resistor settings.
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