A 5.8 GHZ LOW NOISE AMPLIFIER FOR WIRELESS LAN APPLICATIONS IN SILICON BIPOLAR TECHNOLOGY

Gerd Schuppener; Mehrun Mokhturi, and Boris Kerzur

Royal Institute of Technology, Department of Electronics, Electrum 229

S-164 40 Kista-Stockholm, Sweden

ABSTRACT A monolithic low-noise amplifier for operation in the

5.8-GHz band is described. Different versions have been implemented each operating over a different range of supply voltage. At 5-V, the amplifiers gain is about 16-dB, with a noise figure of 4.1-dB and 1-dB compres- sion point at -15-dBm input power.

The circuits have been designed utilizing Ericsson Components 0.6-micron silicon bipolar technology (P71), featuring npn transistors with fT and f,,,, of about 20-GHz.

1. INTRODUCTION Todays typical Local Area Network (LAN) environ-

ment requires costly planning and investment to build and maintain. Radio based (wireless) LANs might soon become a more flexible and even less expensive option in dynamic environments, than todays wired systems. Prerequisite is that the required hardware can be imple- mented using low-cost, low-power IC technologies. Desirable candidates are silicon based technologies since they offer low-cost and high integration levels. However, recent standards propose the usage of 5-GHz bands for WLAN applications challenging the design task.

We have investigated the use of a conventional Si bipolar production technology to implement a low- noise amplifiers (LNA) which is a key component in the receiving end of a radio link.

2. DEVICES AND TECHNOLOGY The circuits are fabricated in Ericsson Components

Si-bipolar technology (P71). The technology with 0.6- pm minimum feature size consists of trench isolated npn-bipolar transistors with fT and fmax of about 20- GHz at a collector current density around 220-pA/pm2. It offers four levels of metallization and poly-silicon resistors with 100 and 500-Q/sq. MIM capacitors with 0.85-fF/pm2 are available. Using a 3-pm thick AI film for the fourth layer the sheet resistance is as low as I1- mQ/sq and hence, high Q inductors can be formed in that layer.

3. LOW NOISE AMPLIFIER TOPOLOGY The LNA performance is determined by RF parame-

ters such as low noise figure, sufficiently high gain and good impedance matching at input and output. Addi- tionally, the non-linear performance must be adequate to ensure sufficient dynamic range of the receiver. A common measure is the 1-dB compression point of the amplifier. Usually, it is difficult to achieve a good over- all performance with only one gain stage. As can be seen from Fig. 1, a two stage amplifier has been imple- mented, where the first stage ensures noise and input impedance matching, whereas the second stage in con- junction with shunt feedback ensures good output matching and prohibits overload [ 11.

In conventional MMIC design, impedance matching networks are used to transform the impedance at the system interface - commonly 50-Sz - to the impedance of the device. E.g. the 5 0 4 input is transformed to the optimum source impedance required by the device to achieve noise match.

However, using conductive Si substrate, high Q impedance matching networks are difficult to realize. Instead, simultaneous noise and impedance match is widely used. First, the collector current density is deter- mined, which gives the lowest noise figure. Next, the emitter length is scaled to yield an optimum source impedance of 50-Q. The resulting emitter area gives the required collector current for biasing. Finally, the input impedance is matched to 50-Q by introducing inductive feedback at the emitter [l]. If high-Q inductors are available, this impedance match can be accomplished without affecting the optimum source impedance and the noise performance significantly. The value of the inductance can be estimated using well known equation I., resulting in 400-pH for the presented design, which can be easily integrated on-chip.

Zi, E 2 x f T , LE = 50Q ( 1 )

If necessary, the transistors input capacitance can be compensated by an inductance at the base, commonly

0-7803-5682-9/99/$10.0001999 IEEE. 773

realized by a bond wire, with a value equal to: [2] 1 L =-- B - 2 L, (2)

0 Cin

However, when operating the transistor in the first stage close to its frequency limit there is a trade off between gain and noise figure. If the stage is only opti- mized for low-noise the gain might be small which implies that the noise contribution of the second stage will have an increased influence according to Friis' for- mula (eq.3)

where F and G denote noise figure and gain, respec- tively. This effect is emphasized by the fact that the sec- ond stage is not optimized for low noise but biased at a higher current to achieve good linearity. Furthermore, the resistive load and the feedback network will contrib- ute to the total noise. It was found that in this case the noise figure is increased considerably (more than 1-dB) and that the same noise figure but higher gain can be achieved when trading noise against gain in the first stage. Both transistor stages were therefore biased at a collector current around 6-mA (at 3.3-V supply volt- age), although the collector current resulting in the low- est minimum noise figure (2.3-dB) for transistor Q1 (2 x 0.6 x 30 pm2 emitter area) was found to be around 2- mA

The two implemented versions have been designed for supply voltage ranging from 3.3 to 5-V, and 2 to 3.3- V, respectively.

4. INDUCTOR MODEL The on-chip octagonal spiral inductor is modelled

using the equivalent circuit depicted in Fig. 2. The inductance L, is calculated with inner radius and number of turns as parameters using the method pre- sented in [3]. R, is the serial resistance calculated from metal 4 sheet resistance and inductor length. No skin effect has been taken into account, but to reduce the serial resistance and to increase the Q a interconnect (25-pm) is used for the turns. C,, is the underpass

X X

ou t

Figure 1: LNA circuit schematic

Rsub l .=$ 1 C s u b l Csub2 4 .$ Rsub2 T i - - 1 i

Figure 2: Inductor model

'lnd

capacitance only. The fringing capacitance has been neglected since the distance between spiral turns are rather large (5.6-pm) and coupling only can occur over a quarter turn, as can be seen from Fig. 3, which shows the layout of the LNA. C, and C, are equal to half the parallel- plate capacitance of the inductor turns to the substrate. Csub,,, and RSuhl,, are half the substrate capaci- tance and resistance taking into account the substrate thickness and the area which is covered by the inductor.

5. RESULTS Measurements have been performed by on-wafer

probing using Picoprobe Multicontact Wedges. Wiltron 60-GHz network analyser has been used to measure the small signal scattering parameters. Fig 4 shows the S parameters for the LNA at 5-V supply voltage. As can be seen, a gain of 16-dB (S,,) is achieved while main- taining good matching-at input (SI,) and output (S22) of less than -10-dB. The output to input isolation, repre- sented by SI,, is better than 38-dB.

The 1-dB compression point has been determined using Wiltron sweep generator and Tektronix 33-GHz spectrum analyser. Table 1 shows the compression points at different supply voltage.

Figure 3: Chip photograph

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0 CfBlSlZl LNA

-35.00

-40.00

-45.00

-1o.m

-15. w

-20.00

IlBlS2ll LN4

20.00

15.W

10.00

-10.00

-1 5.00

-20.00

Figure 4: Measured S-parameters of the LNA at 5-V

The noise figure has been measured using the Y- method. Here, a noise source at the input of the LNA is switched from a cold to a hot mode, where the excess noise ratio (ENR), i.e. the difference in noise power between the two modes, is known. Measuring the noise power at the output of the LNA in both modes gives Y=Nho/Nro,d and the noise figure can be calculated according to eq. 4

6. CONCLUSION A low noise amplifier for operation in the 5.8-GHz

band has been implemented in a conventional Si bipolar production technology. The amplifier provides 11 to 16- dB gain for supply voltage of 2 to 5-V. The noise figure is around 4-dB. Despite of the rather simple topology, which relies on one reactive tuning element only, the circuit exhibits a fairly good performance comparable to other Si based amplifiers published so far [2, 41. A lower noise figure can be achieved using the same Si technology but changing the amplifier topology involv- ing inductive loads which also can act as interstage matching networks. This, of course, requires a thorough modelling of the lumped matching components and will be subject of further investigations

The amplifier chip size is 550 x 550 pm2.

F = - E N R (4) Y-1

The measured noise figure is presented in Table 1 for different supply voltage. The power dissipation of the amplifier including biasing is presented in table 1 as well.

[VI [dBl [dBl [dBl

-15 -39

3.3 -12 -38

2.5 -10 -41 12

ACKNOWLEDGMENTS The authors gratefully acknowledge the fabrication of

the circuit by Ericsson Components AB and would like to thank Dr. Urban Westergren for his advises concern- ing the noise measurements.

-9 na 4.0 18 2 -10 -41 11

Table 1: Summary of LNA Performance @ 5.8-GHz

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REFERENCES [l] R. G. Meyer, and W. D. Mack, A 1-GHz BiCMOS RF

Front-End IC, IEEE Journal of Solid-state Circuits, Vol. 29, pp. 350-355, March, 1994.

[2] S. P. Voinigescu, et al., A Scalable High Frequency Noise Model for Bipolar Transistors with Application to Opti- mal Transistor Sizing for Low-Noise Amplifier Design, IEEE Proc. Bipolar Circuits and Technology Meeting, Sept. 1996, pp. 61-64.

[3] H. M. Greenhouse, Design of Planar Rectangular Microe- lectronic Inductors, IEEE Trans. on Parts, HyDrids, and Packaging, Vol. PHP-IO, pp. 101-109, June, 1974.

[4] M. Madihian, et al., A 5-GHz-Band Multifunctional BiC- MOS Transceiver Chip for GMSK Modulation Wireless Systems, IEEE Journal of Solid-state Circuits, Vol. 34, pp. 25-32, Jan. 1999.

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