Abstract — A millimeter-wave CMOS frequency multiplier by

two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

I. INTRODUCTION The ever increasing speed of CMOS devices in ultra-scaled nodes enables new applications in the millimeter-wave frequency range. Around 60GHz, 7GHz of unlicensed spectrum, have been allocated for gigabit/sec wireless connectivity. Next generation of automotive radars will operate at 77GHz. Several CMOS transceivers realizations, tailored to these applications have been recently presented. Beyond 100GHz, envisioned applications include imaging systems for security, medical diagnostic, industrial control and chemical sensors. Still a long path toward complete systems of any commercial interest is required, even though simple building blocks in CMOS technologies have already been presented [1-5]. A major obstacle to low power high frequency transceiver realizations beyond 100GHz is due to the degradation, with increasing frequency, of key passive components on silicon substrates. For frequency synthesis, adoption of Voltage Controlled Oscillators (VCOs) at fundamental frequency sets an increasingly severe trade-off between high spectral purity and frequency tuning range due to a dramatic reduction of varactors quality factor and large device parasitics. State of the art varactors-tuned VCOs beyond 100GHz, in standard CMOS technology, display a tuning range of less than 3%, not enough to cover processing spreads[3-5]. An alternative approach, usually pursued with compound semiconductor technologies, relies on a frequency multiplier driven by a VCO running at a lower frequency, as shown in figure 1. Circuits for frequency multipliers usually exploit the non-linearity of active devices to generate harmonics of the input signal.

A resonant output network selects the desired frequency component (e.g. 2nd harmonic for frequency doublers). With CMOS devices, this technique suffers from low-conversion gain or even loss and large input capacitance loading the VCO. Moreover, the multiplier output is typically single-ended not suited, in general, to drive high performance monolithic mixers [6-8]. We have recently presented a new topology of frequency doublers, based on an injection locking technique, which provides differential output, large swing and low core power dissipation. Combining the multiplier and a half frequency VCO, we have realized a frequency generator showing 13.1% tuning range at 115GHz [9]. This paper focuses on the frequency doubler, shown in figure 2, describing the operating principle and detailed experiments. The doubler alone, driven by an off-chip signal source, has been realized in a 65nm CMOS technology. It displays a locking bandwidth ranging from 106GHz to 128GHz and a single-ended on-chip peak output swing, at the center output frequency, of 330mV, with a core power dissipation of 6mW only. Section II describes the principle of operation. The circuit design is described in Section III while the experimental results are presented in Section IV. Finally, Section V draws conclusions.

II. FREQUENCY DOUBLER The proposed frequency doubler topology is shown in figure 2. The circuit relies on sub-harmonic injection locking of a differential oscillator. A Pierce oscillator is formed by the π-network (C-L-C) and transistor M1. Transistors M2’-2’’, are connected as a push-push pair and inject a current in the resonator node 1 at twice the input signal frequency to lock the oscillator.

Enrico Monaco1, Massimo Pozzoni2, Francesco Svelto3, Andrea Mazzanti3

1Università degli Studi di Modena e Reggio E. and Istituto Universitario Studi Superiori di Pavia, Italy 2STMicroelectronics, Pavia, Italy

3Università degli Studi di Pavia, Italy

A 6mW, 115GHz CMOS Injection-Locked Frequency Doubler with Differential Output

Figure1. Voltage controlled oscillator followed by a frequency doubler.

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Two current mirrors Mb, bias the core transistors independently at constant DC current. Capacitors Cb are large enough to behave as AC shorts. The supply to the circuit is provided through a choke inductor (Lck) to the center tap of the resonator. Notice that grounded capacitors are explicitly required in each node of the circuit, for proper operation, and absorb all the device parasitics, making the circuit particularly suited for a very high operation frequency. Notice that, even if transistor M1 sets 180° between V1 and the current injected in the resonator node 2, the two ports of the π-network are not driven symmetrically and the outputs are not balanced. Capacitor CCM is introduced to suppresses the output common mode voltage (VCM). As an intuitive view, VCM is shorted to ground by the low impedance provided by the series resonator formed by CCM and the L/2 branches. To gain quantitative insight on the effect of capacitor CCM, figure 3 shows the simulated amplitude mismatch and phase deviation from 180° of the two outputs of the circuit in figure 2 with and without capacitor CCM. Without CCM the amplitude and phase mismatches, over a bandwidth of 20GHz around 115GHz, are up to 6dB and 30° respectively. When CCM is introduced, the errors are suppressed down to about 1dB and 5° respectively. The frequency locking range of the doubler can be estimated by the analysis of the equivalent circuit in figure 4. The push-push locking pair is modeled by the current generator Iinj. The voltage controlled current source represents transistor M1. The resonator is represented by the π-network, characterized by the 2x2 impedance matrix. Being the network passive a symmetric, Z11=Z22=Z and Z12=Z21=ZT. By inspection, the following two simplified expressions for the impedances can be derived:

( )

( ) ( )0

12 1 2

T

RZj Q

Z Z

ω ωω

ω ω

≈ Δ+

≈ −

(1)

where

0 02 ; Q= RC

LCω ω= (2)

Under large signal operation, the magnitude of the current (Iosc) is constant while the phase is the same of the driving voltage (ϕ1). The operation of the circuit is captured by the following system of equations, which links the two output voltages (in magnitude and phase) to the resonator impedances and currents:

1 1

2 1

1

2

j jT osc inj

j josc T inj

V e Z I e Z IV e Z I e Z I

ϕ ϕ

ϕ ϕ

⎧ = − ⋅ − ⋅⎪⎨ = − ⋅ − ⋅⎪⎩

(3)

Solution of the system proves that the two outputs are balanced (e.g. |V1|=|V2| and ϕ2=ϕ1+ π), as expected, and provides expressions for the output signal swing and the frequency locking range of the circuit (Δωmax). In particular, the latter is given by:

max2

0

1 12

1

ωω

Δ =⎛ ⎞

− ⎜ ⎟⎝ ⎠

inj

osc inj

osc

IQ I I

I

(4)

From the above equation, given the tank quality factor, the locking range increases by increasing Iinj/Iosc. Actually, when designing the circuit, being the oscillation amplitude primarily set by the oscillator core current, Iosc, the locking range is determined by the magnitude of Iinj. Referring to the schematic in figure 2, a larger Iinj is achieved either maximizing the driving amplitude (Vi), the biasing current (I2) or the aspect ratio of the push-push devices (M2’-2’’).

Figure 2. Schematic of the injection locked frequency doubler.

Figure 3. Amplitude and phase errors of the two outputs with and without CCM.

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III. CIRCUIT DESIGN A test chip of the doubler has been designed, in a 65nm CMOS provided by STMicroelectronics, targeting a center output frequency of 115GHz. Capacitors of the resonator are device parasitics only. The center capacitor is also realized with the gate capacitance of a dummy nMOS device. The resonator inductor has been maximized for maximum output amplitude at given power consumption. It is a 80pH single turn spiral of 2.6μm width trace, realized shorting together the two top-most Cu metal layers. Estimated quality factor is 15. The loaded resonator quality factor is much lower (~4). Losses are primarily determined by series resistances of capacitors (gate and bulk resistances) and output conductances of the active devices. For maximum series impedance and self resonance frequency, the choke inductor (Lck), which provides the supply to the circuit, is realized as a 15μm diameter 3.5 turns spiral of a thin trace in the topmost metal only. From electromagnetic simulations, the self resonant frequency of the two inductors is close to 200GHz. M1 is 20μm/65nm while M2’,2’’ are 10μm/65nm each one. Transistors sizes are relatively small, leading to a low capacitance (~15fF on each input) loading the half-frequency signal source. The two biasing currents have been set equal to 3mA and supply voltage is 1V. From simulations, assuming 300mV input swing on each push-push transistor, the frequency locking range is 18% while the single-ended peak output swing, at center frequency, is 340mV.

The locking signal at half the output frequency is provided by an off-chip millimeter-wave synthesizer. To make the signal differential, a balun has been integrated. The schematic is shown in figure 5. It is a lumped transformer where the secondary winding, driving the doubler, resonates with the gate capacitance of transistors M2’-2’’ of figure 2 and an explicit capacitor C2. Resistor R shunts the primary winding and the input pad and realizes the input signal termination. The biasing voltage for the push-push pair (M2’-2’’) is provided through the center tap of the secondary winding. For measurement purposes, the doubler drives a two stages buffer. The first stage is a pseudo differential common-source amplifier with a resonant load while the second stage is an open-drain differential pair, driving the 50Ω impedance of the measurement setup and supplied off-chip with bias tees. The power dissipation of the buffer is 17mW and the estimated loss is 3dB.

IV. MEASUREMENTS A photomicrograph of the realized test-chip is shown in figure 6. The core active area is 150μm x 180μm. For characterization, dies have been glued on PCB. Supply and biasing signals have been connected through wire bonding while the high frequency input and output signals are provided with microprobes. Measured S11 at the input of the on-chip balun is shown in figure 7. The minimum of S11 is at a frequency slightly lower than expected. However the balun provides a relatively good input matching over a broad frequency range.

Figure 4. Equivalent circuit of the Injection Locking Frequency Doubler.

Figure 5. Schematic of the balun to make the input signal differential.

Figure 7. Measured input matching.

Figure 6. Photomicrograph of the test-chip.

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The input signal is provided by an Agilent E8257G continuous wave signal source, while the output signals have been monitored single-ended on a spectrum analyzer. An external compatible harmonic mixer has been adopted to extend the bandwidth coverage of the spectrum analyzer. The measured single ended output power versus frequency, with a constant input power of 0dBm, at half frequency, is shown in figure 8. The doubler is locked over a frequency range spanning from 106GHz to 128GHz. The peak output power, at center frequency is -2.6dBm. Considering the loss of the buffer, the estimated on-chip single ended voltage swing is about 330mV zero-peak, in good agreement with simulations. The estimated peak voltage conversion gain, from the single-ended input of the balun to the differential output of the doubler is ~6dB. The measured amplitude matching between the two outputs, is shown in figure 9. With the available experimental setup, measurements of the phase difference of the two output signals was not possible. On the other hand, the multiplier provides very well balanced outputs, being the maximum amplitude difference, from figure 9, always below 1dB, i.e. within the estimated accuracy of the setup. Finally the experimental performances of the circuit are summarized in Table I and compared against recently reported CMOS frequency doublers for millimeter-wave applications.

Ref. fout [GHz]

Conv. Gain [dB]

Pdiss (core+buffer) [mW]

Out.

[6] 27 1.5 10 s.e. [7] 40 -15.8 4 s.e. [7] 60 -15.3 4 s.e. [8] 54 -0.45 9 (4+5) s.e.

This work 115 6 23 (6+17) diff.

Table I. Performance summary and comparison against CMOS doublers.

V. CONCLUSIONS Frequency doublers are key building blocks for frequency synthesis at millimeter-waves. Traditional circuit topologies in CMOS technology have poor performances leading to large conversion loss and a single-ended output. In this work a new circuit topology has been described. A pair of transistors, arranged in push-push configuration, generates the 2nd harmonic current component to lock a differential LC oscillator. The circuit, provides a differential output and large swing at limited core power dissipation. From experimental results on a 65nm CMOS test chip, working a 115GHz, the performances of the proposed solution compares favorably against state of the art.

ACKNOWLEDGMENT This work has been partially supported by Italian national funding programs PRIN, contract # 2007B5RZLE and FIRB, contract # RBA06L4S5.

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[9] A. Mazzanti, E. Monaco, M. Pozzoni ,F. Svelto “A 13.1% Tuning Range 115GHz Frequency Generator Based on Injection-Locked Frequency Doubler in 65nm CMOS”, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 2010.

Figure 8. Measured single-ended output swing.

Figure 9. Amplitude difference between the two outputs.

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