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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.4, AUGUST, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2016.16.4.436 ISSN(Online) 2233-4866 Manuscript received Mar. 7, 2016; accepted Mar. 29, 2016 1 School of EE, KAIST, 291 Daehak-roYuseong-gu, Daejeon, Republic of Korea 2 K-Healthware, 71 Jukdong-ro, Yuseong-gu, Daejeon, Republic of Korea E-mail : [email protected] A 95% accurate EEG-connectome Processor for a Mental Health Monitoring System Hyunki Kim 1 , Kiseok Song 2 , Taehwan Roh 2 , and Hoi-Jun Yoo 1 Abstract—An electroencephalogram (EEG)-connect- ome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user’s mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG- connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer’s disease case. The proposed processor occupies 3.8 mm 2 and consumes 1.71 mW with 0.18μm CMOS technology. Index Terms—Connectome, EEG processor, brain disease, synchronization likelihood, wearable I. INTRODUCTION Todays, mental diseases such as Alzheimer’s disease (AD), depression, schizophrenia, and epilepsy, etc. have become serious social issues. For example, as shown in the Fig. 1, about 10-20% of seniors are suffered from those mental diseases, and the number of AD patients are rapidly growing. Techniques using electroencephalogram (EEG) have emerged to diagnose mental health and treat mental disease. In this context, several EEG processors have been proposed for continuous mental health monitoring systems [2, 3]. However, most of them used only power spectral analysis or nonlinear analysis. Both of those methods discard the inter-channel information, resulting in low diagnosis accuracy about 90%. To increase the diagnosis accuracy over 95%, connectome algorithms which use all of the amplitude, phase, and inter-channel information were proposed [4, 5]. Connectome represents the neural connections in the human brain, and synchronization likelihood (SL) is one of the most widely used connectome features. SL is effective to diagnose mental health, such as AD, depression, autism, and attention-deficit hyperactivity disorder (ADHD) [6]. Consequently, the EEG processor for mental health monitoring system should include the SL calculation. There is a critical problem to realize the SL calculation in continuous mental health monitoring system. As shown in Fig. 2, it requires much heavier computational cost leading to larger memory size and higher power consumption than previous methods. To solve this problem, some technical blocks are proposed; reconstruction optimizer (ReOpt) block, synchronization likelihood extractor (SLE) block with sparse matrix

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Page 1: A 95% accurate EEG-connectome Processor for a Mental ... · 440 HYUNKI KIM et al : A 95% ACCURATE EEG-CONNECTOME PROCESSOR FOR A MENTAL HEALTH MONITORING SYSTEM based SVM operate

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.4, AUGUST, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2016.16.4.436 ISSN(Online) 2233-4866

Manuscript received Mar. 7, 2016; accepted Mar. 29, 2016 1 School of EE, KAIST, 291 Daehak-roYuseong-gu, Daejeon, Republic of Korea 2 K-Healthware, 71 Jukdong-ro, Yuseong-gu, Daejeon, Republic of Korea E-mail : [email protected]

A 95% accurate EEG-connectome Processor for a Mental Health Monitoring System

Hyunki Kim1, Kiseok Song2, Taehwan Roh2, and Hoi-Jun Yoo1

Abstract—An electroencephalogram (EEG)-connect-ome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user’s mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG-connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer’s disease case. The proposed processor occupies 3.8 mm2 and consumes 1.71 mW with 0.18μm CMOS technology. Index Terms—Connectome, EEG processor, brain disease, synchronization likelihood, wearable

I. INTRODUCTION

Todays, mental diseases such as Alzheimer’s disease (AD), depression, schizophrenia, and epilepsy, etc. have become serious social issues. For example, as shown in the Fig. 1, about 10-20% of seniors are suffered from those mental diseases, and the number of AD patients are rapidly growing. Techniques using electroencephalogram (EEG) have emerged to diagnose mental health and treat mental disease.

In this context, several EEG processors have been proposed for continuous mental health monitoring systems [2, 3]. However, most of them used only power spectral analysis or nonlinear analysis. Both of those methods discard the inter-channel information, resulting in low diagnosis accuracy about 90%. To increase the diagnosis accuracy over 95%, connectome algorithms which use all of the amplitude, phase, and inter-channel information were proposed [4, 5]. Connectome represents the neural connections in the human brain, and synchronization likelihood (SL) is one of the most widely used connectome features. SL is effective to diagnose mental health, such as AD, depression, autism, and attention-deficit hyperactivity disorder (ADHD) [6]. Consequently, the EEG processor for mental health monitoring system should include the SL calculation.

There is a critical problem to realize the SL calculation in continuous mental health monitoring system. As shown in Fig. 2, it requires much heavier computational cost leading to larger memory size and higher power consumption than previous methods. To solve this problem, some technical blocks are proposed; reconstruction optimizer (ReOpt) block, synchronization likelihood extractor (SLE) block with sparse matrix

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inscription (SMI) scheme, small word feature extractor (SWFE) with a look-up-table (LUT), and radial basis function (RBF) kernel-based support vector machine (SVM) with LUTs.

In this paper, an EEG-connectome processor for a mental health monitoring system is proposed. Fig. 3 shows the headgear-type wearable system for the EEG-connectome processor, which is a modification of a previous work [3]. Under the headgear, there are 19-channel electrodes to measure EEG signals. The EEG-connectome processor is connected to all of those 19 electrodes, which is able to determine the mental state with 95% of diagnosis accuracy from gathered 19-channel EEG signals.

The rest of this paper is organized as follows. Section II describes the top architecture of the proposed processor, and the details of each key building block. Section III shows the implementation results, including the chip evaluation and the experimental EEG verification of patients with severe AD versus controls case. Finally, the conclusion is presented in Section IV.

II. ARCHITECTURE

Fig. 4 shows the top architecture of the proposed EEG-connectome processor. It consists of 4 main blocks; 1) ReOpt to find the optimal parameters for SL calculation, 2) SLE to compute SLs, 3) SWFE to convert SLs into smaller size information, and 4) RBF kernel-based SVM.

1. Accuracy-improving ReOpt

Before computing SLs, EEG signals should be

converted into reconstructed vectors as in Eq. (1), where y: reconstructed vector, x: value of original EEG signal at time t. There are two parameters for EEG reconstruction, named the delay “τ”, and the embedding dimension “d” [7].

y(t) = [x(t), x(t+τ), x(t+2τ), …, x(t+(d-1)τ)] (1)

Fig. 1. Motivation of the mental health monitoring system.

Fig. 2. Pros and cons of proposed connectome approach versus traditional methods.

Fig. 3. Headgear-type wearable system implementation of EEG-connectome processor.

Fig. 4. Top architecture.

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It is known that improper delay degrades the accuracy, and improper embedding dimension degrades both of the accuracy and the computational cost. However, previous works did not compensate for these parameters, but merely fix them because of additional computational cost [2]. In the proposed processor, the ReOpt works to find the optimal delay and the optimal dimension. This block results in 5% improvement in accuracy, and averagely 50% reduction of required operation.

Fig. 5(a) shows the block diagram of the ReOpt. The optimal delay is determined by the autocorrelation method, which is one of the most widely used ones [7]. The autocorrelation is calculated until it reaches the first concave upward curve, and that inflection point is determined as the optimal delay. To check whether it is the inflection point or not, last five autocorrelation values are stored in registers and they are transferred into a comparator. To determine the optimal dimension with a small computational cost, the true nearest neighbor method is adopted [8]. Based on the brutal method, the ratio of true nearest neighbors is calculated and the

optimal dimension is selected if this ratio goes near to 100%. During the calculation, we use 1-norm distance instead of 2-norm distance to remove the multiplication operation.

Fig. 5(b) presents the measurement results of the ReOpt and the corresponding diagnosis accuracy. The points of highest accuracy correspond to the optimal delay and the optimal dimension. Moreover, optimal dimension makes it possible to remove the redundant calculation since the computational cost in SLE is proportional to the dimension value. The number of operations reduces by 50%, from 2.0×105 to 1.0×105 in average.

2. Memory-efficient SLE with SMI Scheme

Computing SLs is composed of 1) calculating the

distance between reconstructed vectors from 19-channel EEG signals, 2) finding epsilon distance (or cutoff distance), and 3) calculating Heaviside function [5]. During this process, a lot of inter-channel distances are required, so the large memory size is required compared to traditional power spectral method. In order to reduce the required memory size, the SMI which stores position data instead of distance data is proposed.

Fig. 6(a) shows the block diagram of the SLE. Similar to ReOpt block, 1-norm distance is used rather than 2-norm one to reduce the computational cost. After calculating the distance, the SMI block in each channel computes both of the epsilon distance and corresponding

(a)

(b)

Fig. 5. ReOpt (a) block diagram, (b) measured results of diagnosis accuracy.

(a)

(b)

Fig. 6. SLE (a) block diagram, (b) SMI scheme.

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Heaviside function for each channel. Using those information, the SLE gains 171 SL values.

Fig. 6(b) shows the detailed SMI scheme in the SLE. Among the reconstructed EEG data in one window, averagely 94% of the values of Heaviside function are equal to 0, while only 6% of those are equal to 1. Thus, to reduce memory size, the SMI stores only the position information whose Heaviside function results are 1, instead of saving all the distance information. Thanks to this distance-to-position conversion, the required memory decreases to 1/16. Moreover, there is an additional memory reduction; the number of bits for one datum decreases to 2/3, because the distance is of 12-bit and the position is of 8-bit. As a result, the proposed SMI scheme reduces the required memory size to 1/24, form 7.3 KB to 0.3 KB.

3. Computational-cost-reduced SWFE and RBF kernel-based SVM with LUTs

The RBF kernel-based SVM shows higher accuracy

than linear classifiers, but it requires a large amount of computational cost due to the big size of input dimension and the difficulty for RBF calculation. To reduce the input dimension of the SVM, the SWFE converts 171 SLs into 6 small world features; 3 of them are named clustering coefficients and other 3 are named the shortest path lengths [4, 5]. For the calculation of SWFE and RBF, LUTs are implemented to replace the complicated floating-point operation.

Fig. 7(a) shows the block diagram of the SWFE and the RBF-based SVM. To compute the shortest path length, floating-point operations for inverse are needed. Thus, an LUT is implemented to replace the floating-point inverse operation. The RBF also uses an LUT instead of the complicated floating-point exponential operation for the same reason. Thanks to those LUTs, the required computational cost decreases by 54%, 2.4×104 to 1.1×104.

Fig. 7(b) shows the details of the LUT architecture for RBF calculation. As shown in the left of Fig. 7(b), the LUT has 7-bit resolution where the accuracy becomes saturated, over 97%. For the learning with various parameters, different kinds of RBFs with their own standard deviation are needed. This processor adopts 8 kinds of LUTs with different standard deviations, and the

table in Fig. 4(b) shows an example of the LUT for the RBF where the standard deviation is 40,000. To reduce the number of comparators, as shown in the right of Fig. 4(b), the RBF is calculated from the MSB to the LSB with the sequential fetching with only one 18-bit comparator. Since the RBF has 7-bit resolution, the RBF is calculated in 7 cycles for this scheme.

III. IMPLEMENTATION RESULTS

1. Chip Evaluation Fig. 8 shows the timing diagram of the whole blocks.

Thanks to the pipelined structure, each block is able to operate concurrently. ReOpt consumes 0.5-6 seconds, but it does not have to be always turned on since ReOpt only compensates the reconstruction parameters. Hence, ReOpt operates once per every 5-10 minutes. SLE consumes about 0.6 seconds; 0.5 seconds for SMI scheme and 0.1 seconds for calculating SLs, and it is the net latency of the whole system. SWFE and RBF kernel-

(a)

(b)

Fig. 7. SWFE and RBF kernel-based SVM (a) block diagram,(b) LUT implementation.

Fig. 8. Timing diagram.

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based SVM operate in almost real-time. Fig. 9 shows the chip photograph and summary. It

occupies 3.8 mm2 in 0.18μm CMOS technology and consumes 1.71 mW at 1.8 V and 20 MHz clock frequency. The window size is set to be 256 to keep the 1-second EEG signals whose sampling rate is usually 256, and the net latency is 0.6 seconds.

Table 1 shows the performance comparison. Previous works do not consider the inter-channel information and used only power spectrum or nonlinear approach, resulting in relatively low accuracy although their applications such as stress treatment and seizure detection are not complicated ones. On the other hand, the proposed work achieved 95% of diagnosis accuracy for complicated mental diseases such as AD by adopting connectome approach. Moreover, thanks to ReOpt, SMI, and LUT schemes, the proposed work is able to reduce the computational cost and memory size, resulting in the better energy FOM than previous works.

2. Experimental Results To confirm the proposed work, analysis with real

measured EEG data from 44 subjects is progressed. 22 of them were controls and 22 were severe AD patients. EEGs are measured 10 times for each subject, respectively. Hence, there are totally 440 measured data.

Left two graphs in the Fig. 10 shows the SL results of controls versus AD patients. The right upper graph is the difference of the controls and patients, describing only the edges whose difference values exceed threshold. The right lower graph is the difference of the controls and patients in [5]. According to the similarity of those two graphs, the result of the proposed work is consistent with the previous algorithm.

The diagnosis accuracy is 95%, with 96.8% of sensitivity and 93.2% of specificity. Fig. 11(a) shows the

Fig. 9. Chip photograph and summary.

Table 1. Comparison table

Fig. 10. SL results.

(a)

(b)

Fig. 11. Diagnosis accuracy results (a) accuracy versus SVM kernel, (b) overall diagnosis accuracy improvement.

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diagnosis accuracy of various SVM kernels. The proposed work adopts RBF kernel because it shows the highest accuracy. RBF kernel usually consumes more computational costs than polynomial ones, but this is negligible because of LUT.

Fig. 11(b) shows the overall diagnosis accuracy improvement for the proposed work. Compared to the conventional method such as power spectral analysis, the proposed work shows 6%p improvement of diagnosis accuracy by adopting connectome approach. Although SWFE reduces the size of input information of the classifier, it preserves the diagnosis accuracy as 95%.

IV. CONCLUSIONS

The proposed EEG-connectome processor for mental health monitoring system is successfully implemented in 0.18μm CMOS technology. To improve the diagnosis accuracy, the proposed processor adopts SLE which calculates connectome and ReOpt which gives the optimized parameters for connectome. Thanks to those blocks, the diagnosis accuracy increases by 6%p, from 89% to 95%. As the connectome approach requires more memory and computational cost than conventional methods, the memory reduction and computational cost reduction schemes are also adopted. For memory reduction, SLE contains SMI scheme which makes the memory size to be ×1/24, and SWFE decreases the feature size to be ×1/29. For computational cost reduction, LUTs substitute the floating-point operation resulting in decrease of the computational cost by 54%, and ReOpt averagely halves the computational cost for connectome. Consequently, although it deals with more complicated mental diseases, the proposed processor achieves 95% of diagnosis accuracy with lower energy FOM and shorter latency than previous works.

REFERENCES

[1] H. Kim, K. Song, T. Roh, and H. –J. Yoo, “A 95% accurate EEG-connectome processor for a mental health monitoring system,” Asian Solid-State Circuits Conference (A-SSCC), Nov. 2015.

[2] T. Roh, S. Hong, H. Cho, and H. –J. Yoo, “A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental

health monitoring,” ISSCC Dig. Tech. Papers, Feb. 2012, pp. 294-296.

[3] T. Roh, K. Song, H. Cho, D. Shin, U. Ha, K. Lee, and H. –J. Yoo, “A 2.14mW EEG neuro-feedback processor with transcranial electrical stimulation for mental-health management,” ISSCC Dig. Tech. Papers, Feb. 2014, pp. 318-319.

[4] M. Ahmadlou, H. Adeli, and A. Adeli, “Graph theoretical analysis of organization of functional brain networks in ADHD,” Clinical EEG and Neuroscience, vol. 43, no. 1, pp. 5-13, 2012.

[5] C. J. Stam, B. F. Jones, G. Nolte, M. Breakspear, and Ph. Scheltens, “Small-world networks and functional connectivity in Alzheimer’s disease,” Cerebral Cortex, vol. 17, no. 1, pp. 92-99, 2007.

[6] E. T. Bullmore, and D. S. Bassett, “Brain graphs: graphical models of the human brain connectome,” Annual review of clinical psychology, vol. 7, pp. 113-140, 2011.

[7] C. J. Stam, “Nonlinear dynamical analysis of EEG and MEG: review of an emergning field,” Clinical Neurophysiology, vol. 116, no. 10, pp. 2266-2301, 2005.

[8] M. Kennel, R. Brown, and H. D. Abarbanel, “Determining embedding dimension for phase-space reconstruction using a geometrical construction,” Physical review A, vol. 45, no. 6, p. 3404, 1992.

[9] W. Chen, et al., “A fully integrated 8-channel closed-loop neural prosthetic SoC for real-time epileptic seizure control,” ISSCC Dig. Tech. Papers, Feb. 2013, pp. 286-287.

[10] M. A. B. Altif, C. Zhang, and J. Yoo, “A 16-ch patient-specific seizure onset and termination detection SoC with machine-learning and voltage-mode transcranial stimulation,” ISSCC Dig. Tech. Papers, Feb. 2015, pp. 394-395.

Hyunki Kim received the B.S. degree in mathematical sciences and the M.S. degree in Electrical Engi- neering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2010 and 2015, respectively. Currently, he

is working toward the Ph.D. degree at KAIST. His research interests include biomedical SoC design, especially focused on low-power signal processors.

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Kiseok Song received the B.S., M.S., and Ph.D. degrees in Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2009, 2011, and 2015, respectively. He is currently working

as a CTO of K-Healthwear R&D Center, which is mobile healthcare solution company. His current research interests include bio-medical SoC design especially focused on mobile (wearable) healthcare application. He is also interested in body channel analysis for low power wireless-body-area-network (WBAN). As a chief researcher at the Semiconductor System Laboratory in KAIST, he developed multi-modal (electromyograph and temperature) feedback electro-acupuncture stimulator SoC and bio-feedback (load impedance, tissue impedance, and skin temperature) iontophoresis controller SoC. Mr. Song received the Marconi Society’s Paul-Balan Young Scholar Award for his contribution to novel bio-medical communications in 2014.

Taehwan Roh received the B.S., M.S., and Ph.D. degrees in Depart- ment of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2009 and 2011, and 2014, respectively. He has

researched a biomedical processor for mental health monitoring and management. He has worked for K-Healthwear to commercialize his researches since 2015. His research interests include a low-power biomedical SoC for wearable healthcare device. He is also interested in wearable healthcare systems for cardiac and mental monitoring.

Hoi-Jun Yoo (M’95 – SM’04 – F’08) graduated from the Electronic Department of Seoul National Univer- sity, Seoul, Korea, in 1983 and received the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science

and Technology (KAIST), Daejeon, in 1985 and 1988, respectively. Since 1998, he has been the faculty of the Department of Electrical Engineering at KAIST and now is a full professor. From 2001 to 2005, he was the director of Korean System Integration and IP Authoring Research Center (SIPAC). From 2003 to 2005, he was the full time Advisor to Minister of Korea Ministry of Information and Communication and National Project Manager for SoC and Computer. In 2007, he founded System Design Innovation & Application Research Center (SDIA) at KAIST. Since 2010, he has served the general chair of Korean Institute of Next Generation Computing. His current interests are computer vision SoC, body area networks, biomedical devices and circuits. He is a co-author of DRAM Design (Korea: Hongrung, 1996), High Performance DRAM (Korea: Sigma, 1999), Future Memory: FRAM (Korea: Sigma, 2000), Networks on Chips (Morgan Kaufmann, 2006), Low-Power NoC for High-Performance SoC Design (CRC Press, 2008), Circuits at the Nanoscale (CRC Press, 2009), Embedded Memories for Nano-Scale VLSIs (Springer, 2009), Mobile 3D Graphics SoC from Algorithm to Chip (Wiley, 2010), Bio-Medical CMOS ICs (Springer, 2011), Embedded Systems (Wiley, 2012), and Ultra-Low-Power Short-Range Radios (Springer, 2015). Dr. Yoo received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011, and Order of Service Merit from Ministry of Public Administration and Security of Korea in 2011 and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC and the TPC chair of the A-SSCC 2008 and ISWC 2010, IEEE Fellow, IEEE Distinguished Lecturer (’10-’11), Far East Chair of ISSCC (‘11-‘12), Technology Direction Sub-Committee Chair of ISSCC (’13), TPC Vice Chair of ISSCC (’14), and TPC Chair of ISSCC (’15).