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Contents lists available at SciVerse ScienceDirect

International Journal of Electronics andCommunications (AEÜ)

jo ur n al homepage: www.elsev ier .com/ lo cate /aeue

background calibration in pipelined ADCs

amid R. Mafia,∗, Amir M. Sodagarb,c,d

Electrical Engineering Department, Azad University, Qazvin Branch, Barajin, Qazvin, IranResearch Laboratory for Integrated Circuits and Systems (ICAS), Electrical Engineering Department, K. N. Toosi University of Technology (KNTU), Tehran, IranPolytechnique Montreal, QC, CanadaSchool of Cognitive Sciences, Institute for Research in Fundamental Sciences, Tehran, Iran

r t i c l e i n f o

rticle history:eceived 2 August 2012ccepted 1 March 2013

a b s t r a c t

In this paper, a novel background calibration is presented. The proposed scheme continuously measuresand digitally compensates conversion errors caused by residue amplifier nonlinearity. This scheme can be

eywords:ackground calibrationipelined analog to digital convertersADCs)

used to relax analog circuit requirements for high-precision residue amplifier, accordingly decreasing thepower consumption and/or increasing sampling rates in pipelined ADCs. The proposed scheme employs afifth-order polynomial to eliminate conversion errors. One unique feature of the proposed scheme is thata single pseudorandom sequence, pn, is exploited. The simulation results show that, using the proposedcalibration technique, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 40 to 66 dB andthe spurious-free-dynamic-range (SFDR) is increased from 48 to 80 dB.

seudorandom sequence

. Introduction

Analog-to-digital converters (ADCs) are key components in dig-tal receivers. Demand for higher data-rate ADCs increases for

ultimedia applications in mobile and fixed communications fromeneration to generation. Recent work on ADCs has made sig-ificant progress toward resolutions in the range of 10–14 bitsnd bandwidths in the range of 50–500 MHz. Pipelined ADCs areopular because they can realize high-speed and high-resolutionimultaneously [1–17].

Within the scope of pipelined ADC research the focus has beenn schemes to reduce the power consumption of pipelined ADCs5,6]. Each stage of pipelined ADC has an op-amp. High resolutionipelined ADCs tend to be large power consumption because thep-amp must have high-gain, high-slew-rate, and wide-bandwidtho meet the accuracy and speed requirements [7]. Designingigh-gain, high-swing op-amps in deep-submicron technologiesecomes increasingly more difficult [2]. To reduce power consump-ion and relax designing op-amps in deep-submicron technologies,t is proposed to exploit low-gain op-amps [1,2,5,6]. The relativeisadvantage of using a low-gain is inaccurate and dependent onmbient (such as temperature), which causes conversion errors [8].

Please cite this article in press as: Mafi HR, Sodagar AM. A background chttp://dx.doi.org/10.1016/j.aeue.2013.03.005

The availability of low-power digital signal processing in mod-rn CMOS technologies has fueled a trend toward the digitalompensation of analog circuit imperfections [9]. Various digital

∗ Corresponding author. Tel.: +98 09127830052.E-mail addresses: h.mafi@qiau.ac.ir, hamid.mafi@gmail.com (H.R. Mafi),

msodagar@kntu.ac.ir (A.M. Sodagar).

434-8411/$ – see front matter © 2013 Published by Elsevier GmbH.ttp://dx.doi.org/10.1016/j.aeue.2013.03.005

© 2013 Published by Elsevier GmbH.

calibration techniques have been developed, such as [1–4,8–17].For high resolution applications nonlinearity in residue ampli-fier must be considered [1,2,8–12]. Digital calibration methodscan be categorized into foreground and background techniques.Foreground calibrations measure non-idealities during a calibra-tion phase which usually occurs during startup [4]. In contrastbackground methods operate during normal operation of thepipelined ADC, consequently it adapts to environmental chargeswithout the need to interrupt normal operation of the ADC [10].The pseudorandom-sequence dithering [8–11] has been used indigital background calibration to continuously measure the ADCerrors. Thus, the errors can be continuously calibrated in the digitaldomain.

This brief reports a novel digital background calibration whichreduces harmonic distortion introduced by residue amplifier non-linearity. To compensate the effect of nonlinear residue amplifier inpipeline ADC, a fifth-order polynomial inverse function is exploited.The organization of the paper is as follows. Section 2 introduces theproposed calibration scheme. The simulation results are providedin Section 3.

2. The proposed calibration scheme

In order to simplify the analysis, this paper focuses on the cal-ibration of the first stage and the next stages are considered asideal backend ADC, as illustrated in Fig. 1. For simplicity, we con-

alibration in pipelined ADCs. Int J Electron Commun (AEÜ) (2013),

sider both analog and digital signals as unit-less quantities whosefull-scale ranges are normalized to one. The first stage consistsof a sub-ADC, a sub-DAC, and a residue amplifier. For the pur-pose of demonstrating the proposed scheme, it is assumed that

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First-Stage

Dout[n]

Vin[n]

D[n]=Vin[n]+ εq[n]

-

Vd[n]

εq[n]

gd()·

ga()·

Ideal BackendADC

Vres[n]

Dres[n]

Sub-ADC Sub-DAC

CorrectionBlock

Dd[n]

pn[n]

pn[n]

gd() · 1

()· 3α1

α3()· 5

α5

ga()·1

()· 3

β1

β3

Dest[n]

re of t

taDm[vitA

D

wssprba

wtenitbtTT

D

w˛cb

D

wt

Proposed Technique

Fig. 1. The architectu

he residue amplifier, which is denoted by ga(·), is non-ideal andll other components in the first stage are ideal. In practical sub-AC implementations, the sub-DAC nonlinearities are critical andust be minimized by a separate calibration mechanism (such as,

9]), in addition to the proposed technique. In order to identify con-ersion errors, a two-level, zero-mean, and independent from thenput signal of the ADC, pseudorandom sequence, pn[n], is addedo the output of the sub-ADC in the first stage as shown in Fig. 1.ccordingly, the digital output of the first stage is given by

[n] = Vin[n] + εq[n] (1)

here D[n], Vin[n], and εq[n] represent the digital output of the firsttage, the sampled input, and the quantization error of the firsttage, respectively. The amplitude of the pseudorandom sequence,n[n], has maximum amplitude of |εq|max. In this case, maximumange of the output of the first stage must be double or |εq|max muste divided by two. The input–output characteristics of the residuemplifier are modeled as follows [8]:

Vd[n] = −εq[n] = pn[n]

Vres[n] = ga(Vd[n] ≈ Vres[n] ≈ ˇ1Vd[n] + ˇ3Vd3[n])(2)

here Vd[n] and Vres[n] denote the differencing node voltage andhe residue output of the first stage, and ˇ1 and ˇ3 represent the lin-ar gain and the third-order error. (The second-order error can beeglected due to the differential architecture). The residue Vres[n]

s then digitized into Dres[n]. The digitized residue Dres[n] is equalo Vres[n] + εbe[n], which εbe[n] is the quantization error of the idealackend ADC. The proposed scheme performs a digital inverse func-ion gd(·) to compensate the effect of nonlinear residue amplifier.he digital inverse function, gd(·), can be well-modeled by a fiveaylor series as follows [8–10]:

d[n] = gd(Dres[n]) ≈ ˛1Dres[n] + ˛3D3res[n] + ˛5D5

res[n] (3)

here Dd[n] represents the digitalized versions of Vd[n], and1, ˛3, and ˛5 represent first-order, third-order, and fifth-orderoefficients of gd(·). From the block diagram of Fig. 1, the relationetween Dout[n] and Vin[n] is as follows:

Please cite this article in press as: Mafi HR, Sodagar AM. A background chttp://dx.doi.org/10.1016/j.aeue.2013.03.005

out[n] = Vin[n] + εq + gd(Dres[n]) (4)

here Dout[n] represents the digital output of the ADC. As men-ioned in [10], by assuming that gd(·) is the only weakly nonlinear

he proposed scheme.

over the range of the small additive term εbe[n], we can approxi-mate Dd[n] by a first-order as follows:

Dd[n] ≈ gd(ga(Vd[n])) + ˛1εbe[n] (5)

By plugging (3) and (4) into (5), the following relation betweenDd[n] and Vd[n] is obtained

Dd[n] ≈2∑

j=0

˛j

[1∑

m=0

ˇm(Vd[n])2m+1

]2j+1

+ ˛1εbe[n] (6)

In the remainder of the analysis, the backend quantization errorεbe[n] is ignored to simplify the analysis. It is easy to shows thatDd[n] has error terms, which are given by

e1[n] ≈ Vd[n](˛1ˇ1 + u1 − 1)

em[n] ≈ (Vd[n]m)[um + ˛mˇm1 ], m = 3, 5, 7, 9

(7)

where u1 denotes the unwanted first-order error term, and um (form = 3, 5, 7, 9) denote the unwanted mth-order terms. Fortunately,the seventh-order and ninth-order error terms tend to be small inpractice in which case they can be ignored [9]. The pseudorandomsequence, pn[n], is also added to the output of the digital inversefunction Dd[n]. Accordingly, the result is as follows:

Dest[n] = e1[n] + e3[n] + e5[n] − εq[n] (8)

As seen from (7), the first-order, e1[n], the third-order, e3[n],and the fifth-order, e5[n], error terms in Dd[n] are directly pro-portional to ˛1, ˛3, and ˛5, and have the terms V1

d[n], V3

d[n],

V5d

[n], respectively. When Vmd

[n] is expanded, the power seriesproduces different cross terms between εq[n] and pn[n] [9,11]. Ifεq[n] is known, we can measure em[n] by correlating Dest[n] andpn[n]εm−1

q [n]. From (1), D[n] can be exploited instead of εq[n],because εq[n] is correlated with D[n]. Hence, the proposed schemeuses the moment correlation between Dest[n] and pn[n]Dm − 1[n] atnth sample as following

alibration in pipelined ADCs. Int J Electron Commun (AEÜ) (2013),

e′m[n] = Dest[n]Dm−1[n]pn[n]; m = 1, 3, 5 (9)

where e1′[n], e3

′[n], e5′[n] denote the instantaneous estimations

for e1[n], e3[n], e5[n] at nth sample. As a result, a search algorithm

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Correction Block

pn[n]

Z-1 α1[w]

μ

D2[n]

Z-1 α3[w]

μ

Dest[n]

Z-1α5[w]

μD4[n]

e1'[n]

e3'[n]

e5'[n]

Δα1[w]

Δα3[w]

Δα5[w]

Averaging

Averaging

Averaging

Momentum

Momentum

Momentum

osed correction block.

ct

wstk˛˛alvctio(

�

wrct

3

su1olaefnc

0 1 2 3 4 5 6 7 8 9 104

6

8

10

12

14

TIme(s)

EN

OB

(Bit

s)

fin = 5MHz

fin = 20MHz

fin = 1MHz

tion for three input frequencies (fin = 1 MHz, 5 MHz, and 20 MHz).As shown in Fig. 3, convergence time of the proposed techniquedepends on the sampling rate of the ADC. According to simulations,

6

7

8

9

10

11

12

EN

OB

(Bit

s)

With nonl inearity Calib ration

Withou t nonlin earity Calibration

Fig. 2. The prop

ould be designed to minimize e1[n], e3[n], e5[n], [10]. In this case,he update expression is given by

˛m[w + 1] = ˛m[w] + �˛m[w], m = 1, 3, 5

�˛m[w] = �

k

n=wk∑n=(w−1)k

e′m[n], m = 1, 3, 5

(10)

here �, w are the step-size and the iteration of the update expres-ion. Because of using averaging to obtain the update size, �˛m[w],he update expression is updated every k. n sample (w = kn), which

is an integer value (k > 1). At first, initial values are given to ˛1,3, and ˛5. Then, the iterations to approach the optimum values of1, ˛3, and ˛5, are started. After a number of iteration steps, ˛1, ˛3,nd ˛5 will converge to their optimum values. In all three correctionoops, the presence of a discrete-time integrator forces the meanalue of the loop inputs to zero, which corresponds to optimumalibration [10]. In order to accelerate the convergence process,he proposed scheme uses momentum [18,19]. The momentumncreases the convergence speed by adding a term that dependsn the gradient of the last update size to the update expression in10), as follows:

˛m[w] = �

k

n=wk∑n=(w−1)k

e′m[n] + M�˛m[w − 1], m = 1, 3, 5 (11)

here M is called the momentum constant. The details of the cor-ection block are illustrated in Fig. 2. One unique feature of thisalibration approach is that a two-level pn[n] is utilized to adjusthe coefficients of gd(·).

. Simulation results

In order to verify the validity of the proposed technique, it wasimulated using MATLAB/Simulink. The ADC used in these sim-lations, is a 12-bit pipelined ADC with a 2-bit first stage and a0-bit ideal backend ADC. The ADC is operated at a sampling ratef 50 M sample/s. According to transistor-level design and simu-ations in a 0.18 �m standard N-Well CMOS process, the residuemplifier of Fig. 1 (i.e., ga(·)) is modeled using the non-ideal param-

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ters ˇ1 and ˇ3. These parameters range from 3.326 to 3.869 androm −20.08 to −24.26, respectively, for the four process cor-ers. The first-order ˛1, the third-order ˛3, and the fifth-order ˛5oefficients of gd(·) are initialized to 0.25, 0, and 0, respectively. The

Fig. 3. Convergence of the ENOB during fifth-order calibration for three input fre-quency.

step-size �, averaging window size k, and momentum constant Mare set to 1 × 10−4, 1000, and 0.85, respectively. Before calibration,SNDR and SFDR are 40 dB and 48 dB By using 5th-order calibration,SNDR and SFDR are improved to 66 dB and 80 dB, respectively. Fig. 3illustrates the convergence of the ENOB during fifth-order calibra-

alibration in pipelined ADCs. Int J Electron Commun (AEÜ) (2013),

0 1 2 3 4 5 6 7 8 9 105

Time(s)

Fig. 4. Convergence of the ENOB.

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0 1 2 3 4 5 6 7 8 9 10-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

a1

a5

a3

at

nfa

ot

4

ahcAt

R

[

[

[

[

[

[

[

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2010;57(November (11)):853–7.

Time(s)

Fig. 5. Convergence of the coefficients of gd(·) during fifth-order calibration.

s input sampling rate approaches the Nyquist rate, the proposedechnique takes more time to converge.

Fig. 4 shows the convergence of the ENOB over time withoutonlinearity calibration and with nonlinearity calibration (with

in = 5 MHz). The ENOB reaches ∼11b (equivalent to SNDR ≈ 66 dB)fter approximately 1.5 s, which involves around 75 × 106 samples.

Fig. 5 shows the convergence of the first-order ˛1, the third-rder ˛3, and the fifth-order ˛5 coefficients of gd(·) over time duringhe 5th-order calibration (with fin = 5 MHz).

. Conclusion

A novel background calibration for pipelined ADC was proposednd verified. It can be used to relax analog circuit requirements forigh-precision residue amplifier, accordingly decreasing the poweronsumption and/or increasing the sampling rate in pipelinedDCs. The proposed scheme has employed a fifth-order polynomial

o eliminate nonlinearities.

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eferences

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