a basic guide to the ac specifications of adcs

04/03/20

A Basic Guide to the AC Specifications of ADCs, Part 1

Question:It's always good to go over the basics from time-to-time. In this column, I discuss the "AC" specifications associated with analog-to-digital converters. Such specifications include signal-to-noise ratio, total harmonic distortion, signal-to-(noise plus distortion), and spurious-free dynamic range. If you need to know what the numbers mean, how to interpret them, how to measurethem yourself, or are just curious about the specifications in general, read on.

Answe

Most ADC specifications can be broken into two general categories: DC and AC. These terms can be confusing because they don't really have anything to do with direct current or alternating current. Instead, they refer to the method that is used to measure the performance of

The "DC" performance of an ADC is typically measured with a stable, low-noise voltage source. The specifications in this category include offset error, gain error, integral non-linearity (INL), and differential non-linearity (DNL)."AC" performance is measured with the use of one or more sinewave generators. The specifications in this category include signal-to-noise ratio (SNR), total harmonic distortion (THD), signal-to(noise plus distortion) (SINAD), spurious-free dynamic range (SFDR), and intermodulation distortion (IMD).Increasingly, AC specifications also include multi-tone power ratio and the more general noise-power ratio (these won't be covered here).

Basic Test Requirements for Measuring AC PerformanceMeasuring the AC performance of an ADC is simple (in theory): provide one sinewave (or multiple sinewaves) to the ADC, make sure that the signal (or the sum of the signals) exercises the ADC's full-scale input range without clipping, perform continuous conversions on the input signal, collect the conversion results, perform a discrete Fourier Transform (DFT) on the data set, and calculate the ADC's performance.

Of course, the reality of AC testing is a different matter, and there are a number of compromises that are made in order to perform AC measurements. Some of these compromises are minor and create few problems, while others are more significant.

First, the Fourier Transform can be a problem for a several reasons: a general purpose discrete Fourier Transform algorithm can be computationally demanding and the data set must be "windowed" in order to provide useful results. Rather than use a general purpose discrete

Transform, a specialized form know as the Fast Fourier Transform (FFT) is used. The FFT algorithm requires that the number of conversion results collected from the ADC be a power of 2: 2, 4, 8, 16, 32 ,64, etc. In order to produce repeatable AC measurements, larger data sets are used-typically in the range of 1,024 to 8,192.

Windowing of the data set presents a rather significant problem. Basically, the DFT and FFT algorithms assume that the data set represents a repetitive waveform. The two ends of the data set must fit together. (Specifically, the very first data point in the data set must be the same number that would have appeared after the very last data point.)

Assuming no particular relationship between the conversion rate and the frequency of the input signal to the ADC, the last result in the data set is unlikely to align properly with the first. Thus, the data must be forced into this state through the use of a window function which tapers the ends to zero. Unfortunately, this changes the results produced by the FFT and these changes must be taken into account. Another problem is that the AC numbers are less repeatable. The reason is that some of the performance "information" collected from the ADC has been lost due to the window. This can be corrected by collecting a much larger data set. However, it will then take more time to process the data.(A brief side note: Bob Masta has a number of columns on the Fourier Transform and windowing in his archive section. The first article in the series is: Gut-Level Fourier Transforms: Everything You Need, You Got in High School.)

The end result of the "window problem" is that most ADC manufacturers test with "coherent" input signals. By carefully choosing the input frequency (and/or conversion rate), each data set will be repetitive with the next. Thus, no window function is required.

For coherent testing, the following mathematical relationship must be met:

Lowest Coherent Frequency = Conversion Rate ÷ Sample Size Test Frequency = M × Lowest Coherent Frequency (where M is an integer)

For example, if the data set to be collected is for 4,096 conversion results and the ADC will convert at a rate of 100kHz, then the lowest coherent frequency is 100,000/4,096 or 24.4140625Hz. For any input frequency lower than this value, the data set will not represent a complete cycle of the input frequency. A higher frequency input signal is permitted as long as it is an integer multiple of the lowest coherent frequency. An input frequency higher than the "Nyquist rate" (1/2 of the conversion rate, or 50kHz in this case) of the converter is also permitted (it will alias back to a lower frequency which is also coherent).

Coherent testing is done with signal generators that can be locked to a common reference signal (typically 1MHz, 5MHz, or 10MHz) and whose frequency can be set very precisely. The locking and precision are critical in order to keep the input signal aligned with the conversion signal. Without going into the equations, you can figure out how closely the two frequencies must match by assuming that the input signal cannot be off by more than 1/2 of a least significant bit (LSB) by the end of the data set.

I've heard claims that coherent testing is "cheating" because it isn't very likely that the input frequencies to an ADC will be coherent with the conversion rate in the "real world." There are also concerns that coherent testing may only test a few spots on the converter's transfer function rather than the entire transfer function.

I don't buy the first claim at all. I have personally tested hundreds of ADCs with and without windowing. I've never seen a case where coherent testing yielded numbers better than non-coherent testing. In each case, coherent testing provided more repeatable numbers, but not better numbers.

The second concern is very real. Because of the mathematical relationship between the conversion rate and the input frequency (or frequencies), it's possible for the input signal to keep "hitting" the same spots in the converter's transfer function over and over. The solution is to require that M be, at the very least, an odd number and that it should, ideally, be a prime number. In both cases, M should not be one (which generally is not very useful anyway).

Another problem is the suitability of the sine generator. The AC source must have lower noise and distortion than the converter being tested. For a 16-bit converter, the signal-to-noise ratio of the source must generally be 100dB or better, while total harmonic distortion (first few harmonics) must be less than -100dB. For high resolution converters, such as 20-bit or 24-bit delta-sigma audio ADCs, finding a suitable sine source can prove to be impossible.

Even for 12-bit converters, finding a suitable generator can be difficult or impossible. The newest 12-bit ADCs on the market support conversion rates greater than 100MHz. AC testing for these converters will be done with input frequencies up to 200MHz. The AC source should have SNR of greater than 80dB and THD of less than -80dB.

The solution to this problem is very simple, but is difficult to implement: filter the generator's output with a lowpass or bandpass filter. The reason that this proves difficult in practice is that filters can be nonlinear. So, while a filter might remove distortion, it can also add distortion. As a general rule, active filters are not used to filter the AC source, so the filter is usually a passive design made up of capacitors and inductors. Capacitors can be nonlinear (see Dielectric Absorption and Distortion for more information), but the main culprit is usually the inductors.

The generator or circuit that provides the digital signal to the ADC for starting the conversion process can also be a source of problems. Remember that the AC source and the "convert command" generator must be locked together, so the generator must provide this feature. In many cases, the convert command generator is actually a sine generator and its output is converted to a digital TTL, CMOS, or ECL level signal with a fairly simple "sine-to-digital" converter.

The convert command signal must have very little jitter from sample-to-sample. Keep in mind that the ADC's sample-and-hold must grab the AC input signal very precisely. If this point changes in time from conversion to conversion, then sample-and-hold will capture the wrong portion of the input signal, corrupting the AC measurements. The amount of jitter that is acceptable will depend mostly on the frequency of the input signal and the resolution of the ADC. Note that long term changes in the conversion time are acceptable as long as the frequency of the command generator and AC source drift together (in other words, if their common reference frequency changes, then there will not be a problem as long as both generators can track the change).

AC SpecificationsTo quickly review, measuring the AC performance of an ADC requires:

A low-noise, low-distortion, lockable sine source or sources (with filter(s), if needed) A low jitter, lockable convert command generator (or system) A means of capturing the digital results from the ADC (at least 1024 conversions) Software to process the ADC's results and display the AC performance

The software must perform an FFT on the collected data set and then, using one-half ofthe FFT result (both halves are mirror images if the input data is real, which it is in this case), convert the result from complex format (real and imaginary) to polar format (magnitude and phase).Generally, the phase data is not of interest, but there are very special cases where it can be useful (I will not cover those here).The magnitude data provides the necessary numbers to compute the AC specifications. The end result is displayed in a 20 × log(magnitude) format so that the FFT result can be viewed (seeFigure 1).

Figure 1. Frequency Spectrum of a 16-bit, 40kHz ADC Digitizing a 980Hz Input Signal.

It should be noted that Figure 1 is sometimes called an FFT, as in "Let me seethat FFT." Technically, this usage is incorrect. Figure 1 is actually the frequency spectrum of the ADC's discrete time domain output which has been arrived at with the use of a Fast Fourier Transform algorithm. There are other ways that the frequency spectrum could have been computed. However, "FFT" has slipped into common usage as meaning the actual frequency spectrum itself.

Figure 1 defines the key terminology that is needed in order to describe the AC specifications. The fundamental represents the AC input signal. Since the testing is coherent (no window function has been applied to the data), the fundamental is contained in the center of exactly one "bin" of theFFT. At twice the frequency of the input signal lies the first harmonic of the fundamental. If the test setup is good, then the power in the harmonic bin is due only to the ADC and not the AC source. At three times, the input frequency is the second harmonic of the fundamental.

There can be a lot of confusion in regards to naming the harmonics. Obviously, the first harmonic of the fundamental should be called the "first harmonic." Unfortunately, there are other considerations in naming the harmonics. For example, if the harmonic number is referred to as N times the fundamental frequency, then the first harmonic will actually be called the second harmonic (meaning 2 times the fundamental). Then, the first harmonic is the fundamental itself. This has the added benefit in that harmonic "0" is actually the "DC" bin (0 times the fundamental frequency). In some cases, it's desirable to know the power in the DC bin. Thus, software can treat the various "harmonics" in a similar way. On the other hand, a problem with this approach occurs when specifying THD-that will be covered shortly in part two.

The convention adopted here is that the harmonic number refers to N times the fundamental frequency. So, the first (leftmost) of the three harmonics shown in Figure 1 is 2, the second is 3, and the third is 4.

The noise floor of the FFT represents the inherent noise in the ADC as well as the quantization noise of the analog-to-digital conversion process (which replaces an infinitely variable analog input with a discrete digital output). The level of the noise depends on the SNR of the ADC as well as the number of points in the FFT. The overall power doesn't change, but more bins in the FFT result means that the same power is divided up among them, so the noise floor drops. This will be discussed in detail in part two of this series.

The spurious-free dynamic range of the ADC is the range between the fundamental power level and the power in the largest bin of the FFT which is not the DC bin. In some special signal processing applications, harmonic distortion is not a concern, and spurious-free dynamic range is defined as the difference between the fundamental and the highest bin which is not the DC bin or a harmonic bin.

Looking at Figure 1, we have the following definitions for the various AC specifications:

SNR Fundamental power divided by the power of all the bins other than the DC, fundamental, and first N harmonic bins

THD Power of the first N harmonic bins (usually expressed relative to some reference power)

SINAD Fundamental power divided by the power of all the bins in the FFT other than the DC and fundamental bins (SINAD can also be computed as SQRT(SNR2+THD2))

SFDR Difference between fundamental bin and highest bin that is not DC or fundamental (or, sometimes, not first N harmonic bin)

Each of these calculations is a power calculation: the result is the square-root(SQRT) of the sum of squares of the power in the defined bins: result = SQRT(b2 + c2 + d2 + ...). Keep in mind that this is not an RMS calculation, the results are total power not average power.

UnitsThe units for AC specifications are given in most ADC datasheets as "dB." Unfortunately, the numbers and units are sometimes not consistent.

SNR is a simple ratio of two powers, so its unit should be dB. However, THD is simply a straightforward power calculation, so its unit could be expressed in watts, but that would imply a certain load value. Instead, THD is specified relative to some total power, making the THD calculation a ratio similar to SNR.

Herein lies the main problem - defining a value that will serve as a reference for THD. The simplest reference level is the full-scale range of the ADC (in Figure 1, full-scale is at the top of the graph). Referencing THD to this level and then computing a log of the result provides a number whose units are "dBFS" (decibels relative to full-scale). This has an interesting side effect: if the power in the fundamental is lowered, the THD number generally gets better because THD is not relative to the input signal, but relative to converter's full-scale range (which is constant). Harmonic distortion in most ADCs becomes much lower (better) when the input signal is lowered and/or has a slower slew rate.

It is very tempting to express not only THD in units of dBFS, but also SNR, SINAD, and SFDR. As can expected, this does occur. In nearly all cases, the text in the units column will still say "dB."

Generally, the "abuse" is fairly small. For example, a 16-bit ADC might provide 88.2 dB of SNR with an input of -0.5 dBFS. However, the typical SNR shown in the datasheet will be "89 dB" (88.2 + 0.5 = 88.7 or approximately 89). To be correct, the specification should read "89 dBFS."

One-half to one dB of error is not too bad. However, I have seen extreme cases where the input amplitude was -6 dBFS and the AC specifications were still given in units of "dB." This can make the SNR appear to be somewhat better and can make THD much better that it otherwise would be if specified correctly.

A great deal more information about AC specifications and AC testing will be presented in Part 2.

Copyright ©1999-2000 ChipCenter

| Part2 | Part3 | Part4

04/14/2000

A Basic Guide to the AC Specifications of ADCs, Part 2By Jerry Horn

It's always good to go over the basics from time to time. In this column, I discuss the "AC" specifications associated with analogto-digital converters (ADCs). Such specifications include signal-to-noise ratio (SNR), total harmonic distortion, signal-to-(noise plus distortion), and spurious-free dynamic range. If you need to know what the numbers mean, how to interpret them, how to measure them yourself, or are just curious about the specifications in general, read on.

This is Part 2 of a series concerning the AC Specifications of ADCs. Part 1 looked at the basic test requirements for measuring AC performance and defined the terms.Figure 1 from Part 1 is referenced several times in the following text, so Figure 1 has been reproduced here for reference purposes.

Figure 1 - Frequency Spectrum of a 16-bit, 40 kHz ADC Digitizing a 980 Hz Input Signal

Oddities of the FFTThere are a number of items regarding the FFT that may not be immediately obvious and can be downright confusing when first dealing with FFTs. I will do my best to make these as clear as possible.

The ADC's digital output represents a discrete-time system. Nothing can be known about any inputs to such a system that exceed 1/2 of the conversion rate of the system (called the Nyquist rate). This is why the FFT of Figure 1 is limited to a 20 kHz bandwidth (the conversion rate of the

ADC is 40 kHz). What happens to the harmonics of the AC source that are greater than the Nyquist rate, do they "disappear?"

Figure 2 - Frequency Spectrum of a 16-bit, 40 kHz ADC Digitizing a 9.8 kHz Input Signal

Actually, the harmonics are still there within the frequency spectrum. This can be seen in Figure 2. However, the frequency of those harmonics beyond the Nyquist point aliases back into the frequency spectrum. Assuming a 40 kHz ADC, a harmonic at 21 kHz will alias back to 19 kHz. A harmonic whose frequency is 39 kHz aliases back to 1 kHz, while one at 41 kHz also aliases back to 1 kHz. (This aliasing somewhat complicates the code for computing the THD result.)

At this point, harmonics and aliasing can become very confusing. If a harmonic is at 41 kHz, but the alias is at 1 kHz, does the 41 kHz signal actually exist within the ADC or is it a 1 kHz signal? The best answer is that both can occur. If the sample-and-hold is the source of the distortion, then a 41 kHz tone actually is present "within" the ADC (I am somewhat oversimplifying this case). However, the converter itself only sees a 1 kHz tone because its view of the world is limited to the discrete time domain. On the other hand, if the distortion comes from the conversion process, then a "true" 41 kHz tone is not present - the 1 kHz tone is a result of the mixing between the input signal and the converter's transfer function.

The noise floor of the FFT is related to the signal-to-noise ratio of the converter. For a simple case, assume that four conversion results are taken from an ADC and processed with the FFT. The result will be two bins: the fundamental and another bin. While the other bin will also be the DC bin, let's ignore that for now. The SNR of the converter is then distributed between the fundamental bin and the second bin. So, the average noise floor that will be observed in the second bin is 3 dB lowerthan the converter's SNR.

Likwise, an FFT on eight conversion results will result in a noise floor that is 6 dB lower than the converter's SNR.

From this, a general equation can be defined for the noise floor of the FFT:

Noise Floor (in dBFS) = -Converter's SNR (in dB) - 3 dB * (N - 1)

where N is the log2 of the number of results in the data set (the "power" of two of the FFT). To confirm this, the first example was with four conversion results, so N equals 2 (log2 of four). The noise floor would then be the converter's SNR minus 3 dB.

Another way of looking at this is to consider the FFT itself. The FFT result is actually the output of a group of digital bandpass filters. As the data set is doubled, the width of the filter is reduced by 1/2, and the average noise power within that filter's bandwidth falls by 3 dB. However, the total power remains the same. I find that the most confusing aspect of the noise floor calculation is to remember to subtract one from N.

The noise floor equation is very helpful for "eyeballing" the FFT result. If you look at Figure 2, you can see that the "average" noise floor is around -123 dB. Since the spectrum is based on an 8K FFT, the noise floor is 36 dB lower than the converter's SNR, which must be -123dB + 3dB * (13 - 1), or around 87 dB. Actually, the converter's SNR is slightly better than this at around 89 dB. However, the FFT plot has been done with a fairly thick line width, and this somewhat hides the fact that the average noise floor is slightly lower than shown in Figure 2. Still, getting within 2 dB via a simple trick is not bad.

The ideal SNR of an ADC with a given J-bit resolution is defined by the equation:

Ideal SNR (in dB) = 6.02 * J + 1.76 dB

The next question is then a simple "Why?" The answer is somewhat complex, but I will try a simpler approach. Figure 3 depicts a sine input being digitized by an ideal 6-bit ADC over 32 samples. The converter holds the analog input at the start of each conversion period. The digital output is the best estimate of the analog input voltage. As shown in the enlarged section of the figure, the digital output might be in error by as much as plus or minus 1/2 of a least significant bit (LSB).

[ ... that is: ]

Figure 3 - 64 Conversions from a 6-bit ADC

The definition of SNR is signal-to-noise ratio or (signal power)/(noise power). In the caseof Figure 3, the signal power [... correctly: effective value of signal ] is 0.707 * 1/2 Vpp, where Vpp is the peak-to-peak input voltage. Noise power is somewhat trickier. From the discussion so far, the noise signal that rides on top of the actual sine signal varies between ±0.5 LSB. An assumption can be made that the error is random. Thus, if the error in each digital result is graphed relative to the actual input signal, the distribution of the errors over multiple conversions is rectangular (compared to say a gaussian distribution). This means that, on average, the noise voltage is ±0.25 LSB. However, this is not the noise power. Computing the average power of a function with a rectangular probability density is not trivial for those of us who are "mathematically challenged."

Instead, I will simplify the calculation. Assume five ADC results that are in error by the following amounts: 0.05 LSB, 0.15LSB, 0.25LSB, 0.35LSB, and 0.45LSB. This is a valid assumption because the distribution is even (or rectangular). I do not need any negative numbers because the power computation will square all of them, so the sign drops out. The averagepower [... correctly:the effective value ] for this case is the square root of the mean of the squares:

So, the average noise power is 0.288 time the LSB size, where the LSB size is Vpp/2J. Then:

Ideal SNR = (0.707 * 0.5 * Vpp) / ((0.288 * Vpp) / 2J) = 1.2274 * 2J

If this is converted to dB ( 20 * log(result) ):

Ideal SNR (in dB) = 20*log(1.2274) + J * 20 * log(2) = 1.78 dB + J * 6.02 dB

which is pretty dang close to the actual equation (the difference is due to the simplification of the average noise power).

The ideal SNR equation raises a number of questions: "Can the SNR of an ADC be any better than the ideal?" and "How close to typical converters come to the ideal SNR?"

Actually, a low-resolution ADC (say 6 bits or less) can actually exceed the ideal SNR by a few tenths of a dB or more. The reason lies in the assumption for the ideal SNR equation: that the noise signal has a rectangular probability density. When doing AC testing, the input is a sine wave and this sine wave can be placed within the quantization levels of the ADC in such a way that the density of the error signal is not rectangular. Thus, the assumption is invalid. Unfortunately, this observation is not of much use in the real world.

Real ADCs come fairly close to matching their ideal SNR numbers within a dB or so, particularly converters with a resolution of 12 bits or less. However, when the ADC becomes very high speed, then the SNR suffers (see Practical Limits of Analog-to-Digital Conversion for more information). As a rough rule, most low-frequency 12-bit ADCs should come within 1 dB to 2 dB of their ideal number (74 dB) unless something is wrong with the converter. Higher speed 12-bit ADCs may reach only 65 dB SNR. For 16-bit converters, SNRs are generally in the 86 dB to 92 dB range.

General Observations about AC SpecificationsThe SNR of an ADC does not generally decrease as the frequency of the input signal is increased. Once the ADC samples the input, the conversion process sees only a DC signal. Since SNR is related to DNL, and DNL does not change with input frequency, SNR does not change. However, the SNR number calculated by the AC test setup may get worse at higher frequencies. The usual reason for this is that high-order harmonics may increase and some of those will be included in the SNR calculation. For most real-world applications, you can assume that the SNR is as stated in the data sheet without too much concern for the input frequency.

A similar statement does not apply to THD, which depends on the converter's overall INL at low input frequencies and the sample-and-hold performance at higher frequencies. The connection between INL and THD is described in The Relationship between Harmonic Distortion and Integral Non-Linearity.

The number of harmonics used for calculating THD from manufacturer to manufacturer seems to be "all over the map." In general, the number is set (somewhat arbitrarily) by the marketing department in order to show the ADC in the best light for the intended applications. If the ADC has a lot of harmonic distortion, marketing will attempt to steer the ADC towards applications where SNR is important. THD will then include a large number of harmonics so that SNR looks good. On the other hand, if harmonic distortion is important, THD will include fewer harmonics. In general, THD will include the first five to nine harmonics of the fundamental. (This can be confusing relative to the harmonic naming convention. As used here, the first five harmonics are the second (2fIN) through the sixth (6fIN).)

There is no "ideal THD" equation similar to the ideal SNR equation because the integral nonlinearity of the converter can be perfect. Thus, for very linear ADCs, the THD is set by the noise floor of the converter. Since this is related to the FFT size, THD would then be directly related to the number of conversion results used to calculate the AC performance. As a side note, this can create and has created a number of correlation issues for production testing. Here is a tip for achieving better correlation: if the absolute magnitude of a converter's THD is 10 dB better than the SNR, then repeatability will become increasing difficult as the THD value approaches the ideal noise floor of the FFT. Realize that, in this case, the THD is so good that nobody cares about correlation anyway.

The THD of a converter can improve dramatically with a modest decrease in the fundamental amplitude. For example, it may improve 6 dB with only a 2 dB reduction in input power. This fact can be used to achieve considerably better THD performance from an ADC with only a modest increase (worsening) in SNR.

SFDR is generally the difference between the fundamental power and the power in the second (2fIN) or third harmonic (3fIN) bin. Since these harmonics can decrease considerably with slightly lower input amplitude, the worst-case SFDR would seem to be defined by a full-scale input signal. This is not always true. For some converters, SFDR (relative to the converter's full scale) may suddenly increase at certain points as the input amplitude is lowered. When the input amplitude is very low, SFDR can dramatically increase because of the local INL over a small number ofLSBs. Large-scale dither can sometimes be used to overcome this problem.

Audio ADCsFor years, the audio industry has created its own specifications that are specific to the audio market. AC specifications are no exception. Some of the specifications are the same, others share thesame name but have different meanings, and some are completely different.

There are three key audio specifications:

Audio Specification AC Specification Definition

SNR Noise power relative to FS(full scale) with the no input signal (inputgrounded)

DynamicRange SNR with a -60 dBFS input signal, but expressed relative to FS

THD+N SINAD with a -1 dBFS to -6 dBFS input signal, but expressed relativeto FS

For most audio ADCs, SNR and Dynamic Range are equivalent. (For audio DACs, the two can differ, particularly in cases when the DAC detects that the digital input stream represents "all zeros" [called infinity zero] and physically mutes the DAC output by connecting the DAC's output to ground or to a stable reference voltage. When comparing audio DACs, read the SNRspecification carefully. Some manufacturers will turn off infinity detect for the SNR test, which is a more honest measurement of SNR.)

Note the general practice within the audio community of referencing everything to full scale. This is fairly common, but not everyone does it, so read the specifications carefully.

Generally, audio ADC data sheets almost never specify THD by itself. Within audio applications, very low level harmonic distortion is considered to be inaudible. In some cases, high-level harmonic distortion can even "enhance" the sound. However, the audio community does look for reasonable (and low) THD+N numbers that come close to the SNR and Dynamic Range values. Note that, as with non-audio ADCs, some manufacturers of audio ADCs test THD+N with an input signal that is considerably below full scale (for example, -6 dBFS).


Part1 | | Part3 | Part4

04/28/2000

A Basic Guide to the AC Specifications of ADCs, Part 3By Jerry Horn


This is Part 3 of a series concerning the AC specifications of ADCs. Part 1 looked at the basic test requirements for measuring AC performance, and Part 2 examined FFT in some detail.Figure 1 from Part 1 is referenced several times in the following text, so Figure 1 has been reproduced here for reference purposes.

Figure 1 - Frequency Spectrum of a 16-bit, 40 kHz ADC Digitizing a 980 Hz Input Signal

ExamplesIn all of my columns, I attempt to reduce the number of graphic images to the bare minimum. I believe this improves the readability of the material and reduces download time for those with lower speed Internet connections. However, for this column, I have included a rather large number of graphic images. My goal is to provide concrete examples of many of the items I have discussed in this particular series of columns as well as past columns. My apologies to those of you with lower speed connections, I hope the wait is worthwhile.

The examples that follow focus on one analog-to-digital converter (ADC): the ADS8320. This is a 16-bit, 100 kHz ADC manufactured by Burr-Brown. As was stated in the columns The ADS8320: A 16-bit, 8-pin, low power SAR ADC - Part 1 and Part 2, this device is very handy for use in various situationss concerning ADCs.

In some cases, the ADS8320 will be "short-cycled" after the twelfth bit decision has been made (the conversion process will be stopped). For more information about short cycling, see Benefits of Short Cycling.

Also note that all AC results are relative to full scale (dBFS) and not to the input level (dB and dBc). This makes it easier to compare the numbers from different FFTs. However, the numbers should normally be in either dB or dBc (dB relative to the carrier).

Ideal 12-bit Performance

Figure 2 - The ADS8320 as an "Ideal" 12-bit Converter

Figure 2 shows the performance of the ADS8320 when short-cycled to produce a 12-bit result. When used in this manner, the ADS8320 approximates an ideal 12-bit converter. The signal-to-noise ratio (SNR) for such a converter should be 6.02 * 12 + 1.76 or 74 dB. As shown in Figure 2, the SNR is only slightly less than perfect at 73.94 dBFS.

Limiting Full-Scale Range to Improve THDShort-cycling the ADS8320 produces a 12-bit converter with excellent differential nonlinearity (DNL) and good integral nonlinearity (INL). However, the INL still contributes some harmonic distortion. By limiting the full-scale range of the converter to 80% of normal, the INL ends up being more linear over the shorter span. This improves total harmonic distortion (THD) as shown inFigure 3. The cost is a worsening of SNR by 2 dB, but an improvement in THD by 2 dB. (The AC results shown in Figure 3 still reference 0 dBFS, but the actual input range of this "limited" converter would be 2 dB lower, so 2 dB must be subtracted from the numbers shown).

Figure 3 - Limiting Full-Scale Range to Improve Harmonic Distortion

THD Increases at Higher FrequenciesAn ADC's harmonic distortion generally increases with increasing input frequency. This can be seen by comparing Figure 2 (with a 10 kHz input signal) to Figure 4 (with a 55 kHz input signal). THD has worsened by 8 dB. Note that SNR also decreases, but only by 0.17 dBhardly enough to matter.

Figure 4 - Increasing the Input Frequency Worsens THD

As a sidebar, Figure 4 shows the ADC being used in an "undersampling" situation. This means that the input frequency is beyond the Nyquist rate of the converter (one-half of the conversion rate). Keep in mind that the input signal to an ADC can be any frequency, but all input frequencies

will alias to a bandwidth of one-half the conversion rate. If the input signal is properly bandlimited and the ADC's sample-and-hold is good enough, the ADC can theoretically be used to digitize any frequency band.

Also, the second harmonic of the input signal would be at 110 kHz. In Figure 2, the alias of this frequency is 10 kHz. The third harmonic is at 165 kHz, which aliases to 35 kHz. If fH is the frequency of the desired harmonic, fC is the conversion rate of the ADC, and fN is the Nyquist frequency of the converter (one-half fC), then the alias frequency, fA, can be calculated from

fA = fH mod fC; if fA > fN, then fA = fC - fA ,

where fH mod fC computes the modulo (or remainder) of fH after fC has been repeatedly subtracted until fH is less than fC. For example, 10 mod 100 gives 10, while 315 mod 10 gives 15. Note that there are ways to express the computation without resorting to the if statement. However, I don't feel that they are as clear.

Finally, I should mention that ADCs can also be used in oversampling applications. Undersampling and oversampling are sometimes confused with each other. When an ADC is used for oversampling, the bandwidth of the input signal is limited to only a portion of the Nyquist bandwidth, such as one-half, one-fourth, one-tenth, etc. Usually, the data from the ADC are then processed in some manner that results in a lower data rate. For example, the processing might involve decimation using a digital low-pass filter. The end result is to either simplify the analog front-end that preceeds the ADC, or, in some cases, increase the resolution of the conversion process. (I hope to cover both undersampling and oversampling in future columns.)

Non-Windowed FFT on Non-Coherent DataAs was mentioned in Part 1 of this series, there are a number of reasons to use coherent testing for calculating AC results. The input signal is coherent with the conversion rate when the data collected for the FFT contain exactly an integer number of cycles of the input signal. If this is not the case, then something similar to Figure 5 will result.

Figure 5 - Input Signal not Coherent with Conversion Rate and Non-Windowed FFT

The area underneath the fundamental is often referred to as "spectral leakage." It is as though the power in the fundamental (which should be confined to a single bin) has "leaked out" into adjacent bins.

Larger FFT Results in Lower Noise FloorFigure 6 shows that when the number of conversions used to compute the FFT is increased, the noise floor decreases. Compare the noise floor of Figure 6 (an 8k point FFT) to that of Figure 2(a 4k point FFT). The noise floor for Figure 6 is 3 dB lower, but the SNR is the same.

Figure 6 - Increasing the Number of Points in the FFT Lowers the Noise Floor

If you compare Figure 6 to Figure 2, you will also notice that SNR is exactly the same in both cases, while THD is slightly different (about 0.5 dB). THD is actually 0.5 dB worse in Figure 6. Since nine harmonics are being used for the THD calculation, and everything after the fourth harmonic is pretty much in the noise floor, you might expect THD to be better. However, the harmonic power is low enough that it is being affected by the random power that appears in the bins used to compute THD. Over the course of several 8k point FFTs, THD varied from 84.6 dBFS to 83.8 dBFS. The one-sigma value for the variation in THD under this particular situation is probably around 0.4 dB. Thus, the variation in THD can be attributed to test repeatability.

"Visual Cheating" with FFTsOccasionally you will find manufacturers of ADCs displaying FFTs similar to that of Figure 7. By placing the input signal at one-fourth of the conversion rate, the harmonics end up near the fundamental or either end of the FFT. This effect visually "hides" the harmonics and makes the ADC look better. However, the THD number still shows that there is harmonic distortion present. In this particular display, the harmonics are actually hidden by the axes of the graph.

Figure 7 - Placing the Input Signal at One-Half the Conversion Rate to Visually Hide the Harmonics

ClippingWhile it is really not of interest relative to AC results, Figure 8 shows what happens when the input of the ADC is overdriven. When the input sine wave digitally clips at plus and minus fullscale, the resulting spectrum contains a large number of harmonics of the fundamental. In Figure 8, these have grouped together to produce the "peaks and valleys" look to the FFT.

Figure 8 - Overdriving (Clipping) the ADC with a +0.5 dBFS Input Signal

Note that the input amplitude is shown to be 0.36 dBFS, while the actual input amplitude was set to 0.5 dBFS. It may seem that it would be impossible for any input signal to exceed 0 dBFS.

However, the input signal is a sine wave, not a plus full-scale to minus full-scale square wave. The power in a single input frequency cannot exceed 0.707 * 0.5 * VPP, where VPP is the peak-to-peak input voltage of the ADC, without clipping the ADC (this is the definition of 0 dBFS).

If the input does clip, the power in a single bin can exceed 0 dBFS. Speaking very loosely, the Fourier transform of the input signal is a sine wave larger than 0.707 * 0.5 * VPP along with a bunch of harmonics that, when summed, clip the sine wave at the peaks, but slightly add to it elsewhere. Notice that the power of the fundamental is not 0.5 dB as expected, but shows a slight error, and is actually 0.36 dB.

As a brief comment, the total power of all the bins in the FFT can add up to 3.01 dBFS if the input signal is a square wave.

16-Bit Performance

Figure 9 - 16-Bit Performance of the ADS8320

Figure 9 shows the 16-bit performance of the ADS8320. The ideal SNR for a 16-bit converter is 98.1 dB, while the ADS8320 shows about 91.4 dB of performance. This is very good compared with other 16-bit converters on the market, as most 16-bit converters show performance in the 86 dB to 92 dB range.

There is one very interesting item in regards to Figure 9. Note the grouping of harmonics near the third harmonic, and the absence of such near the second and fourth harmonics. Near the third harmonic are aliases of the seventh, thirteenth, and seventeenth harmonics as well as additional harmonics farther "out." This is a very interesting clue about the shape of the INL for this particular converter.

Figure 10 - 16-Bit Performance of the ADS8320 (THD calculation is for 99 harmonics)

Figure 10 shows that the SNR of the ADS8320 is actually 0.7 dB "better" than shown in Figure 9. Thus, the SNR given in Figure 9 is slightly limited by the harmonic distortion of the converter. This can be an important observation. If the INL of the converter can be made better, the SNR would improve.

Just in case you were wondering, the SNR is not being improved because 90 bins are now included in the THD calculation and are no longer included in the SNR. The SNR computation takes into account the number of bins that are used relative to the total number of bins in the FFT.

Dynamic RangeIn Part 2 of this series, I mentioned that audio converters use different AC specifications than those used for more general-purpose ADCs. One of those specifications is dynamic range, which is the SNR of the converter (relative to full scale) with a -60 dBFS input signal. While audio converters are not generally tested with FFTs, a conceptual "audio dynamic range" test can be performed on the ADS8320. The result is shown in Figure 11.


Figure 11 - The "Dynamic Range" of the ADS8320 is Given by the SNR Result

Audio ADCs are tested in a manner similar to that shown in Figure 11 because audio dynamic range is not particularly concerned with harmonic distortion. The goal is to exercise the ADC with a small-amplitude signal, but not in such a way that the sample and hold becomes a limitation (audio signals rarely come within a few dB of full scale). As can be seen in the figure, there is some small harmonic distortion, but not much (THD is -109.6 dBFS, first 9 harmonics).

Notice that the SNR of the ADC has improved from Figure 9 (a full-scale input) to Figure 11 (a - 60 dBFS input) by almost 3.3 dB. The major reason for the improvement appears to be the limited SNR of the generator producing the sine wave. For the -60 dBFS test, the generator actually produces a larger signal and then attenuates it. The result is a lowering of the generator's noise floor relative to the noise floor of the ADC. To test the ADS8320 properly, the sine wave generator should possess a signal-to-noise ratio at least 10 dB better than the converter, or roughly 105 dB. This is a very difficult number to achieve, and it is unlikely that this particular generator is that good.

Some of the improvement may also be due to the local DNL in the area being tested. As can be seen in Figure 11, only 68 codes of the converter's 65,536 codes are being tested (codes 32,808 to 32,875). If the DNL is very good for those codes relative to the average DNL for all codes, then the SNR would be better.

It would seem that the ADS8320 actually has excellent SNR for a 16-bit ADC, possibly several dB better than the capability of the test setup.


Part1 | Part2 | | Part4

05/11/20

A Basic Guide to the AC Specifications of ADCs, Part 4


This is the final section of a four-part series concerning the AC Specifications of ADCs. Part1 looked at the basic test requirements for measuring AC performance, Part 2 examined FFT in

In previous columns, the AC specifications associated with ADCs were examined in detail. The ADS8320, a 16-bit, 100 kHz ADC, was used to illustrate various AC specifications and issues related to these specifications (see The ADS8320: a 16-bit, 8-pin, low-power SAR ADC - Part1 and Part 2 for more information about the ADS8320). In this column, the ADS8320 will be used to illustrate how the change in AC performance of an ADC versus various parameters can

As a brief review, this series has focused on four AC specifications: signal-to-noise ratio (SNR), signal-to-(noise ratio plus distortion) (SINAD), total harmonic distortion (THD), and spurious-free dynamic range (SFDR). So, when referring to the "AC performance" of an ADC, the reference is to these four specifications.

Given these specifications, it is possible to graph the change in the measured results as the function of a change in an independent variable. An obvious example is to graph the change in AC performance over temperature. The resulting data can help determine the temperature range over which the ADC should be guaranteed for a given performance by the manufacturer, or the temperature range over which it can be used for a given application by the customer.

For the ADS8320, there are other not-so-obvious variables that can be changed. For example, the independent variable can be conversion rate, input amplitude, input frequency, reference voltage, supply voltage, the voltage levels on the digital inputs, and common-mode voltage. Some of these tests yield very little information, others are quite interesting. The remainder of this column will focus on the more interesting results.

AC Performance vs. Conversion RateThis test is very simple. With an input signal whose frequency and amplitude are fixed, vary the conversion rate of the ADC while measuring its AC performance. As the conversion rate is increased, the sampling period and the conversion time are both decreased. At some point, the sampling period becomes too short, and harmonic distortion increases. At another point, the


conversion time becomes too short and the signal-to-noise ratio begins to degrade. The results from running this test on a single ADS8320 are shown in Figure 1.

Figure 1 - AC Performance of the ADS8320 vs. Conversion Rate

From Figure 1, a number of items can be discovered. First, the harmonic distortion of the converter begins to degrade at around 50 kHz. At 100 kHz, the performance has dropped several decibels. This indicates that the sampling period for the ADS8320 is actually too short to support a good, solid 100 kHz conversion rate. It is likely that the ADS8320 suffers some integral nonlinearity (INL) degradation at 100 kHz, and that the INL of the converter can be improved by lowering the conversion rate (for more information on how THD and INL are related, see The Relationship between Harmonic Distortion and Integral Non-Linearity). (Later, it will be shown that the THD is not any better for lower input frequencies, so the problem here is not the 10 kHz frequency of the input signal.)

Also, the signal-to-noise ratio of the converter begins to degrade for conversion rates beyond 100 kHz. Since the test was done at room temperature, there is some risk that SNR may worsen at the temperature extremes when running at a 100 kHz conversion rate. So, lower conversion rates may help guarantee solid SNR performance over temperature.

It might appear that the SINAD curve shown in Figure 1 does not provide much information. However, I find SINAD very useful as a "worst-case" measurement. It defines a "first-order" boundary of the converter's worst-case performance. The area below the SINAD curve is where the ADC can be used without much concern. The converter can be used for performance "above" the SINAD curve, but only if the application is not concerned with either harmonic distortion or noise.

Likewise, it might appear that the SFDR curve does not provide useful information. Here again, I find SFDR useful, but not as useful as the SINAD curve. The SFDR curve gives a feel for the "complexity" of the harmonic distortion within the ADC. If the SFDR and THD performance are close to being the same, then the harmonic distortion is defined by a single harmonic - typically the second or third harmonic of the input signal. This is a clue to the shape of the converter's INL.


If the SFDR is farther from the THD, then the harmonics of the fundamental are more similar in total power (but it cannot be determined which harmonics are present, only that the number of "significant" harmonics is greater than one).

If the SFDR and THD curves get closer and farther away as the independent variable is changed, then the converter's INL is changing and is, to some degree, dependent on the independent variable. If the two track each other, then INL is not as dependent on the independent variable. This observation proves very useful in a test discussed later.

AC Performance vs. Input FrequencyAn obvious test of the converter's sample-and-hold is to graph AC performance as a function of the frequency of the input signal. This is done in Figure 2.

Figure 2 - AC Performance of the ADS8320 vs. Input Frequency

There are a couple of items of interest here. As has already been determined, the ADS8320 is not intended for undersampling applications (where the input signal will exceed one-half of the sample rate). The converter is good up through about 20 kHz, and then the harmonic distortion begins to worsen.

In a previous column, I made the statement that SNR rarely degrades as the input frequency is increased. In general, this is true. However, I also pointed out that higher order harmonic distortion can worsen for some converters, and that this is particularly true for the ADS8320. So, at around 20 kHz, harmonics that are not included in the THD number begin to increase, and these harmonics add to the RMS power of the "noise." So, the entire AC performance of the converter drops.

Note how the roll-off of all the curves in Figure 2 is about the same. This is a significant clue that the underlying mechanism for the decrease in performance can be traced back to the same source.

AC Performance vs. Input Frequency (with jitter on the conversion clock)As an interesting sidebar, Figure 3 shows the AC performance of the ADS8320 as a function of the input frequency when there is jitter on the conversion clock.


Figure 3 - AC Performance of the ADS8320 vs. Input Frequency with Clock Jitter

Notice how the presence of jitter on the conversion clock significantly affects the noise performance of the converter, but does not affect the harmonic distortion. For clock jitter whose distribution is Gaussian, the SNR of the converter falls off at a rate of 20 dB for every 10x increase in input frequency. If the clock jitter has a different distribution (rectangular, bi-modal, etc.), then the results will be different from those shown in Figure 3. As a general rule, if SNR changes at a rate different from THD as the input frequency is increased, then excessive clock jitter is strongly indicated.

AC Performance vs. Reference VoltageFigure 4 shows the performance of the ADS8320 as the reference voltage is varied. (The results shown in Figure 4 are not terribly useful relative to the ADS8320, but the test can prove very helpful for other converters.)

Figure 4 - AC Performance of the ADS8320 vs. Reference Voltage


As would be expected, the noise performance improves as the reference voltage is increased (the full-scale range of the converter gets larger relative to the thermal noise of the converter). Surprisingly, harmonic distortion worsens significantly at first, and then varies slightly as the reference voltage is increased.

The reason that this is surprising is that the INL of the ADS8320 is very much related to the voltage coefficient of capacitance of the ADS8320's semiconductor process. As the reference voltage is raised, the effect of this nonlinearity increases, and harmonic distortion generally degrades. However, this particular ADS8320 may have a more complex INL. When the reference voltage is around 1.0 V, the INL appears to be flat, and harmonic distortion approaches the noise floor of the FFT. When the reference voltage is raised by half a volt, the INL must change considerably. It's also possible that the voltage coefficient is more pronounced in this region and then levels off as voltage increases further.

Also, this graph shows how the SFDR curve can be useful. Note how the SFDR curve moves closer to or farther from the THD curve. This indicates that the converter's INL is changing shape as the reference voltage is varied.

AC Performance vs. Input AmplitudeFigure 5 gives the performance of the ADS8320 as the amplitude of the input signal is increased.

Figure 5 - AC Performance of the ADS8320 vs. Input Amplitude

As was mentioned in a previous column, it is believed that the SNR of the ADS8320 is somewhat limited at higher amplitudes (as the input signal approaches 0 dBFS) by the performance of the signal generator. So, the roll-off seen on the SNR curve over the last 10 dB may not be real.

Figure 5 can be extremely useful in certain applications, and I wish that more converter manufacturers provided this type of information. As can be seen, if the full-scale range of the signals provided to the ADS8320 were to be limited to only one-half of the converter's full-scale range, then the harmonic distortion of the converter would improve significantly. While the


converter would provide only "15 bits" of useful information, the SNR performance would still be nearly 90 dB, while the THD performance would be almost -95 dB.

Considering the full-scale performance of the ADS8320 (as shown in Figure 5 by the SINAD curve), the converter gives an effective number of bits (ENOB) of approximately 13 bits. However, if the input range is limited to one-half, then ENOB jumps to 14 bits, even with the loss of one bit. (This is a little tricky, but SINAD at full-scale is 81 dBFS, while SINAD at -6 dBFS is 92 dBFS or 86 dB relative to one-half full scale. A SINAD of 81 dBFS gives an ENOB of 13 bits, while a SINAD of 86 dB gives 14 bits. So, one "real" bit was lost, but two "effective" bits were gained, resulting in a total gain of one bit.)

I should note that the results shown in Figure 5 can also be graphed using the dB and dBc results instead of the dBFS numbers. This can make it easier to visualize the performance trade-off of real bits versus effective bits. However, it makes it harder to determine SFDR over the input amplitude (which is useful information in applications involving higher speed converters used for "software radios"). I also prefer seeing the results as shown in Figure 5 because a flat line means no change in performance (and no dependence on the independent variable).

AC Performance vs. EverythingIn an ideal world, ADC data sheets would provide the average, minimum, and maximum AC performance of a large number of ADCs graphed in N dimensions, with all possible variables included (temperature, conversion rate, input amplitude, input frequency, common-mode voltage, reference voltage, etc.). However, we humans have difficulty interpreting anything beyond two independent variables, and the data would be almost impossible to assemble in a timely manner.

Still, I hope that this column has shown the usefulness of certain AC performance graphs for both the manufacturers of ADCs as well as those that design with them. As a user of ADCs, I always want more data than is provided in the data sheet, but isn't that always the case!


Part1 | Part2 | Part3

a basic guide to the ac specifications of adcs

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